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PR 27139
* aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
core system register.
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47a889a4ca20 ("Improve GNU/Hurd support.") fixed detection of shlibpath_overrides_runpath, thus avoiding unnecessary relink. This backports it.
. * libtool.m4: Match gnu* along other GNU systems.
*/ChangeLog:
* configure: Re-generate.
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* m68k-opc.c (chkl): Change minimum architecture requirement to
m68020.
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Add support for the pause hint instruction, as specified in the
Zihintpause extension. The pause instruction is encoded as a
special form of a memory fence (which is available as part of the
base instruction set). The chosen encoding does not mandate any
particular memory ordering and therefore is a true hint.
bfd/
* elfxx-riscv.c (riscv_std_z_ext_strtab): Added zihintpause.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Added
INSN_CLASS_ZIHINTPAUSE.
* testsuite/gas/riscv/pause.d: New testcase. Adding coverage for
the pause hint instruction.
* testsuite/gas/riscv/pause.s: Likewise.
include/
* opcode/riscv-opc.h: Added MATCH_PAUSE, MASK_PAUSE and DECLARE_INSN
for pause hint instruction.
* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZIHINTPAUSE.
opcodes/
* riscv-opc.c (riscv_opcodes): Add pause hint instruction.
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In fact rev8/orc.b/zext.h are the aliases of grevi/gorci/pack[w], so we
should update them to INSN_ALIAS when we have supported their true instruction
in the future. Though we still use the [MATCH|MAKS]_[GREVI|GORCI|PACK|PACKW]
to encode them. Besides, the orc.b has the same encoding both in rv32 and
rv64, so we just keep one of them in the opcode table.
This patch is implemented according to the following link,
https://github.com/riscv/riscv-bitmanip/pull/101
2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
Jim Wilson <jimw@sifive.com>
Andrew Waterman <andrew@sifive.com>
Maxim Blinov <maxim.blinov@embecosm.com>
Kito Cheng <kito.cheng@sifive.com>
Nelson Chu <nelson.chu@sifive.com>
bfd/
* elfxx-riscv.c (riscv_std_z_ext_strtab): Added zba, zbb and zbc.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB*.
(riscv_get_default_ext_version): Do not check the default_isa_spec when
the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_DRAFT.
* testsuite/gas/riscv/bitmanip-insns-32.d: New testcase.
* testsuite/gas/riscv/bitmanip-insns-64.d: Likewise.
* testsuite/gas/riscv/bitmanip-insns.s: Likewise.
include/
* opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for ZBA/ZBB/ZBC.
* opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZB*.
(enum riscv_isa_spec_class): Added ISA_SPEC_CLASS_DRAFT for the
frozen extensions.
opcodes/
* riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
(MASK_RVB_IMM): Used for rev8 and orc.b encoding.
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PR 27116
bfd/
* xcofflink.c: Correct spelling in comments.
binutils/
* coffgrok.c (do_type): Correct spelling of auxiliary in errors.
* doc/binutils.texi: Correct grammar.
* readelf.c (process_version_sections): Correct spelling of auxiliary
in warning.
* testsuite/binutils-all/vax/objdump.exp: Comment grammar fix.
config/
* override.m4: Correct comment grammar.
gas/
* config/tc-i386.c: Correct comment spelling.
* config/tc-riscv.c: Likewise.
* config/tc-s390.c: Correct comment grammar.
* doc/c-i386.texi: Correct spelling.
* doc/c-s390.texi: Correct grammar.
gold/
* tilegx.cc: Correct comment spelling.
gprof/
* README: Correct grammar.
* gprof.texi: Likewise.
include/
* coff/internal.h: Correct comment spelling.
* coff/sym.h: Likewise.
* opcode/aarch64.h: Likewise.
ld/
* configure.tgt: Correct comment grammar.
* emultempl/m68hc1xelf.em: Likewise.
* ld.texi: Correct grammar.
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https://github.com/riscv/riscv-asm-manual/pull/61
We aleady have sext.w, so just add sext.b, sext.h, zext.b, zext.h
and zext.w. In a certain sense, zext.b is not a pseudo - It is an
alias of andi. Similarly, sext.b and sext.h are aliases of other
rvb instructions, when we enable b extension; But they are pseudos
when we just enable rvi. However, this patch does not consider the
rvb cases. Besides, zext.w is only valid in rv64.
gas/
* config/tc-riscv.c (riscv_ext): New function. Use md_assemblef
to expand the zext and sext pseudos, to give them a chance to be
expanded into c-ext instructions.
(macro): Handle M_ZEXTH, M_ZEXTW, M_SEXTB and M_SEXTH.
* testsuite/gas/riscv/ext.s: New testcase.
* testsuite/gas/riscv/ext-32.d: Likewise.
* testsuite/gas/riscv/ext-64.d: Likewise.
include/
* opcode/riscv.h (M_ZEXTH, M_ZEXTW, M_SEXTB, M_SEXTH.): Added.
opcodes/
* riscv-opc.c (riscv_opcodes): Add sext.[bh] and zext.[bhw].
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opcodes/
* disassemble.h (riscv_get_disassembler): Declare.
* disassemble.c (disassembler): Changed to riscv_get_disassembler.
* riscv-dis.c (riscv_get_disassembler): Check the elf privileged spec
attributes before calling print_insn_riscv.
(parse_riscv_dis_option): Same as the assembler, the priority of elf
attributes are higher than the options. If we find the privileged
attributes, but the -Mpriv-spec= is different, then output error/warning
and still use the elf attributes set.
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bfd/
* elfxx-riscv.c (riscv_ext_dont_care_version): New function. Return
TRUE if we don't care the versions of the extensions. These extensions
are added to the subset list for special purposes, with the explicit
versions or the RISCV_UNKNOWN_VERSION versions.
(riscv_parse_add_subset): If we do care the versions of the extension,
and the versions are unknown, then report errors for the non-implicit
extensions, and return directly for the implicit one.
(riscv_arch_str1): Do not output i extension after e, and the extensions
which versions are unknown.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZICSR
and INSN_CLASS_ZIFENCEI.
* testsuite/gas/riscv/march-imply-i.s: New testcase.
* testsuite/gas/riscv/march-imply-i2p0-01.d: New testcase. The version
of i is less than 2.1, and zi* are supported in the chosen spec, so
enable the fence.i and csr instructions, also output the implicit zi* to
the arch string.
* testsuite/gas/riscv/march-imply-i2p0-02.d: Likewise, but the zi* are
not supported in the spec 2.2. Enable the related instructions since
i's version is less than 2.1, but do not output them.
* testsuite/gas/riscv/march-imply-i2p1-01.d: New testcase. The version
of i is 2.1, so don't add it's implicit zi*, and disable the related
instructions.
* testsuite/gas/riscv/march-imply-i2p1-01.l: Likewise.
* testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise, and set the zi*
explicitly, so enable the related instructions.
* testsuite/gas/riscv/march-imply-i2p0.d: Removed.
* testsuite/gas/riscv/march-imply-i2p1.d: Removed.
include/
* opcode/riscv.h: Add INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI.
opcodes/
* riscv-opc.c (riscv_opcodes): Control fence.i and csr instructions by
zifencei and zicsr.
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These two extended mnemonics are documented in the Principles of
Operations manual but currently not supported by Binutils. They
provide aliases for already supported instructions with the zero flag
being set. The flag otherwise is mingled into one of the immediate
operands what makes asm code much harder to read.
opcodes/
* s390-opc.txt: Add risbgz and risbgnz.
* s390-opc.c (U6_26): New operand type.
(INSTR_RIE_RRUUU2, MASK_RIE_RRUUU2): New instruction format and
mask.
gas/
* testsuite/gas/s390/zarch-z10.s: Add tests for risbgz.
* testsuite/gas/s390/zarch-z10.d: Add regexp for risbgz.
* testsuite/gas/s390/zarch-zEC12.s: Add tests for risbgnz.
* testsuite/gas/s390/zarch-zEC12.d: Add regexp for risbgnz.
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Add extended mnemonics used in the HLASM assembler. All of them are
just aliases for instructions we already support and help when
assembling code which was written for the HLASM assembler.
The HLASM mnemonics are documented here:
https://www.ibm.com/support/knowledgecenter/SSENW6_1.6.0/com.ibm.hlasm.v1r6.asm/asmr1023.pdf
See the 'Branching with extended mnemonic codes' chapter.
objdump will still print the existing mnemonics with the exception of
relative nop branches (i.e. conditional branches with an empty
condition code mask). Now we have jnop and jgnop which will be used
by objdump when possible.
The same change have been applied to the LLVM assembler:
https://reviews.llvm.org/D92185
opcodes/
* s390-opc.txt: Add extended mnemonics.
gas/
* testsuite/gas/s390/esa-g5.s: Test new extended mnemonics.
* testsuite/gas/s390/esa-g5.d: Likewise.
* testsuite/gas/s390/esa-z900.s: Likewise.
* testsuite/gas/s390/esa-z900.d: Likewise.
* testsuite/gas/s390/zarch-z900.s: Likewise.
* testsuite/gas/s390/zarch-z900.d: Likewise.
ld/
* testsuite/ld-s390/tlsbin_64.dd: The newly added jgnop mnemonic
replaces long relative branches with empty condition code mask.
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Although spec had defined and ratified p, v and n extensions,
but we don't have any related implementaitons so far, so keep
them in the supported extension table looks weird. Remove them
until we have the related implementations.
opcodes/
* riscv-opc.c (riscv_ext_version_table): Remove the p, v, n
and their versions.
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bfd/
* elfxx-riscv.c (riscv_parse_std_ext): Stop parsing standard
extensions when parsed h keyword.
(riscv_get_prefix_class): Support prefixed h class.
(riscv_std_h_ext_strtab): Likewise.
(riscv_ext_h_valid_p): Likewise.
(parse_config): Likewise.
(riscv_std_z_ext_strtab): Add zifencei.
* elfxx-riscv.h (riscv_isa_ext_class): Add RV_ISA_CLASS_H.
gas/
* testsuite/gas/riscv/march-fail-order-z.d: New testcase, check
orders of prefixed z extensions.
* testsuite/gas/riscv/march-fail-order-z.l: Likewise.
* testsuite/gas/riscv/march-fail-single-char-h.d: New testcase.
* testsuite/gas/riscv/march-fail-single-char.l: Updated.
* testsuite/gas/riscv/march-fail-unknown-h.d: New testcase.
* testsuite/gas/riscv/march-fail-unknown.l: Updated.
opcodes/
* riscv-opc.c (riscv_ext_version_table): Add zifencei.
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The previous change
"x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit mode"
to ignore segment override prefixes in 64-bit mode lead to dumping
branch hints as excessive prefixes:
ffffffff8109d5a0 <vmx_get_rflags>:
...
ffffffff8109d601: 3e 77 0a ds ja,pt ffffffff8109d60e <vmx_get_rflags+0x6e>
^^^^^
In this particular case, those prefixes are not excessive but are used
to provide branch hints - taken/not-taken - to the CPU.
Assign active_seg_prefix in that particular case to consume them.
gas/
2002-11-29 Borislav Petkov <bp@suse.de>
* testsuite/gas/i386/branch.d: Add new branch insns test.
* testsuite/gas/i386/branch.s: Likewise.
* testsuite/gas/i386/i386.exp: Insert the new branch test.
* testsuite/gas/i386/x86-64-branch.d: Test for branch hints insns.
* testsuite/gas/i386/x86-64-branch.s: Likewise.
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
opcodes/
2020-11-28 Borislav Petkov <bp@suse.de>
* i386-dis.c (print_insn): Set active_seg_prefix for branch hint insns
to not dump branch hint prefixes 0x2E and 0x3E as unused prefixes.
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Extract FLAGM (Condition flag manipulation) feature from Armv8.4-A.
Please note that FLAGM stays a Armv8.4-A feature but now can be
assigned to other architectures or CPUs.
New -march option +flagm is added to enable independently this
feature.
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"In 64-bit mode, the CS, DS, ES, and SS segment-override prefixes have
no effect. These four prefixes are not treated as segment-override
prefixes for the purposes of multiple-prefix rules. Instead, they are
treated as null prefixes." (AMD APM v2).
However, objdump disassembles instructions containing those ignored
prefixes by still generating that segment override:
66 66 2e 0f 1f 84 00 data16 nopw %cs:0x0(%rax,%rax,1)
00 00 00 00
Print those segment override prefixes as excessive ones:
66 66 2e 0f 1f 84 00 data16 cs nopw 0x0(%rax,%rax,1)
00 00 00 00
which is what they actually are - they have no effect and the decoding
hardware ignores them.
gas/
2020-11-14 Borislav Petkov <bp@suse.de>
* testsuite/gas/i386/x86-64-segovr.d: Adjust regexes.
* testsuite/gas/i386/x86-64-nops.d: Likewise.
* testsuite/gas/i386/x86-64-nops-1.d: Likewise.
* testsuite/gas/i386/x86-64-nops-1-g64.d: Likewise.
* testsuite/gas/i386/x86-64-nops-1-core2.d: Likewise.
* testsuite/gas/i386/x86-64-nops-1-k8.d: Likewise.
* testsuite/gas/i386/x86-64-nops-2.d: Likewise.
* testsuite/gas/i386/x86-64-nops-3.d: Likewise.
* testsuite/gas/i386/x86-64-nops-4.d: Likewise.
* testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise.
* testsuite/gas/i386/x86-64-nops-4-k8.d: Likewise.
* testsuite/gas/i386/x86-64-nops-5.d: Likewise.
* testsuite/gas/i386/x86-64-nops-5-k8.d: Likewise.
* testsuite/gas/i386/x86-64-nops-7.d: Likewise.
* testsuite/gas/i386/x86-64-nop-1.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-2c.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-6.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-7.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-8.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops-1.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops-2.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops-3.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops-4.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops-5.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops.d:: Likewise.
ld/
2020-11-14 Borislav Petkov <bp@suse.de>
* testsuite/ld-x86-64/pe-x86-64-4.od: Adjust regexes.
* testsuite/ld-x86-64/tlsld3.dd: Likewise.
* testsuite/ld-x86-64/tlsld4.dd: Likewise.
opcodes/
2020-11-14 Borislav Petkov <bp@suse.de>
* i386-dis.c (ckprefix): Do not assign active_seg_prefix in
64-bit addressing mode.
(NOTRACK_Fixup): Test prefixes for PREFIX_DS, instead of
active_seg_prefix.
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Allow users to use LS64 extension with Armv8.6 architecture.
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assembler.
include * opcode/pru.h: Add LMBD (left-most bit detect) opcode index
opcodes * pru-opc.c: Add opcode description for LMBD (left-most bit detect)
gas * testsuite/gas/pru/misc.s: Add tests for lmbd (left-most bit detect)
* testsuite/gas/pru/misc.d: Add tests for lmbd (left-most bit
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This patch:
+ Adds new ACCDATA_EL1 (Accelerator Data) system register, see [0].
+ Adds LS64 instruction tests.
+ Update LS64 feature test with new register.
+ Fix comment for AARCH64_OPND_Rt_LS64.
[0] https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/accdata_el1
Note: as this is register only extension we do not want to hide these
registers behind -march flag going forward (they should be enabled by
default).
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Atomic 64-byte load/store instructions limit Rt register number to
values matching below condition (register <Xt> number must be even
and <= 22):
if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED;
This patch adds check if Rt fulfills above requirement.
For more details regarding atomic 64-byte load/store instruction for
Armv8.7 please refer to Arm A64 Instruction set documentation for
Armv8-A architecture profile, see document page 157 for load
instruction, and pages 414-418 for store instructions of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
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Extract PAC (Pointer Authentication) feature from Armv8.3-A.
Please note that PAC stays a Armv8.3-A feature but now can be
assigned to other architectures or CPUs.
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This patch:
+ updates RAS feature system registers with new RAS 1.1 regs.
+ extends RAS/RAS 1.1 support for all architecture levels of Armv8-A.
Please note that early Armv8-A architectures do not officially support RAS
extension.
Rationale of the patch:
To ease development so that user-friendly RAS system registers operands can be
used. Certain use cases require developers to enable only more generic
architecture (e.g. -march=armv8-a) during system development. Users must use
RAS extension registers bearing in mind that system they use must support it.
The RAS (Reliability, Availability, Serviceability) extension is a
system-level extension that defines a number of system registers.
RAS 1.1 (FEAT_RASv1p1) introduces five new system registers:
ERXPFGCTL_EL1, ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and
ERXPFGF_EL1.
For details see [0].
[0] https://developer.arm.com/docs/ddi0595/i/
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Armv8.7 architecture introduces the "accelerator extension", aka
load/store of 64 bytes. New atomic load/store instructions are: LD64B,
ST64B, ST64BV and ST64BV0.
This patch adds:
+ New feature +ls64 to -march command line.
+ New atomic load/store instructions associated with above feature.
For more details regarding atomic 64-byte load/store instruction for
Armv8.7 please refer to Arm A64 Instruction set documentation for
Armv8-A architecture profile, see document page 157 for load
instruction, and pages 414-418 for store instructions of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
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Patch with missing ChangeLog entries for GAS AArch64 files.
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This patch adds new to Armv8.7 WFIT instruction which take one operand:
WFIT <Xt>
Where:
<Xt> is 64-bit name of the general-purpose source register, encoded in the
"Rd" field.
For more details regarding WFIT (Wait For Interrupt with Timeout) instruction for
Armv8.7-a please refer to Arm A64 Instruction set documentation for Armv8-A
architecture profile, see document pages 570 of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
gas/ChangeLog:
2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update docs.
* testsuite/gas/aarch64/system-5.d: Update test with WFIT insn.
* testsuite/gas/aarch64/system-5.s: Update test with WFIT insn.
opcodes/ChangeLog:
2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-tbl.h (struct aarch64_opcode): New instruction WFIT.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
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This patch adds:
+ New feature +csre to -march command line.
+ New instruction CSR PDEC associated with CSRE feature.
Please note that CSRE system registers were already upstreamed. This patch
should finalize CSRE feature implementation.
CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of
a Call stack record) instruction. Although this instruction has operand
(PDEC) it's instruction's only operand. PDEC forces instruction field Rt
to be set to 0b1111. This results in fixed opcode of the instruction.
gas/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update docs.
* config/tc-aarch64.c (parse_csr_operand): New operand parser.
(parse_operands): Call to CSR operand parser.
* testsuite/gas/aarch64/csre_csr-invalid.d: New test.
* testsuite/gas/aarch64/csre_csr-invalid.l: New test.
* testsuite/gas/aarch64/csre_csr-invalid.s: New test.
* testsuite/gas/aarch64/csre_csr.d: New test.
* testsuite/gas/aarch64/csre_csr.s: New test.
include/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_CSRE): New -march feature.
(enum aarch64_opnd): New CSR instruction field AARCH64_OPND_CSRE_CSR.
opcodes/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
* aarch64-tbl.h (CSRE): New CSRE feature handler.
(_CSRE_INSN): New CSRE instruction type.
(struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
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This patch adds new to Armv8.7 WFET instruction which take one operand:
WFET <Xt>
Where:
<Xt> is 64-bit name of the general-purpose source register, encoded in the
"Rd" field.
For more details regarding WFET (Wait For Event with Timeout) instruction for
Armv8.7-a please refer to Arm A64 Instruction set documentation for Armv8-A
architecture profile, see document pages 565 of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
gas/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update docs.
* testsuite/gas/aarch64/system-5.d: New test.
* testsuite/gas/aarch64/system-5.s: New test.
opcodes/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding
and operand description.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
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This patch adds new variant (nXS) of DSB memory barrier instruction
available in Armv8.7-a. New nXS variant has different encoding in
comparison with pre Armv8.7-a DSB memory barrier variant thus new
instruction and new operand was added.
DSB memory nXS barrier variant specifies the limitation on the barrier
operation. Allowed values are:
DSB SYnXS|#28
DSB ISHnXS|#24
DSB NSHnXS|#20
DSB OSHnXS|#16
Please note that till now, for barriers, barrier operation was encoded in
4-bit unsigned immediate CRm field (in the range 0 to 15).
For DSB memory nXS barrier variant, barrier operation is a 5-bit unsigned
assembly instruction immediate, encoded in instruction in two bits CRm<3:2>:
CRm<3:2> #imm
00 16
01 20
10 24
11 28
This patch extends current AArch64 barrier instructions with above mapping.
Notable patch changes include:
+ New DSB memory barrier variant encoding for Armv8.7-a.
+ New operand BARRIER_DSB_NXS for above instruction in order to
distinguish between existing and new DSB instruction flavour.
+ New set of DSB nXS barrier options.
+ New instruction inserter and extractor map between instruction
immediate 5-bit value and 2-bit CRm field of the instruction itself (see
FLD_CRm_dsb_nxs).
+ Regeneration of aarch64-[asm|dis|opc]-2.c files.
+ Test cases to cover new instruction assembling and disassembling.
For more details regarding DSB memory barrier instruction and its
Armv8.7-a flavour please refer to Arm A64 Instruction set documentation
for Armv8-A architecture profile, see document pages 132-133 of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
gas/ChangeLog:
2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Docs update.
* config/tc-aarch64.c (parse_operands): Add
AARCH64_OPND_BARRIER_DSB_NXS handler.
(md_begin): Add content of aarch64_barrier_dsb_nxs_options to
aarch64_barrier_opt_hsh hash.
* testsuite/gas/aarch64/system-4-invalid.d: New test.
* testsuite/gas/aarch64/system-4-invalid.l: New test.
* testsuite/gas/aarch64/system-4-invalid.s: New test.
* testsuite/gas/aarch64/system-4.d: New test.
* testsuite/gas/aarch64/system-4.s: New test.
include/ChangeLog:
2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New operand
AARCH64_OPND_BARRIER_DSB_NXS.
(aarch64_barrier_dsb_nxs_options): Declare DSB nXS options.
opcodes/ChangeLog:
2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
ins_barrier_dsb_nx.
* aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
ext_barrier_dsb_nx.
* aarch64-opc.c (aarch64_print_operand): New options table
aarch64_barrier_dsb_nxs_options.
* aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
* aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
Armv8.7-a instruction.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
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This patch adds support for AArch64 -march=armv8.7-a command line option
in GAS.
Please note that this change ONLY extends -march= command line interface
with a new "armv8.7-a" option. Architectural changes like new instructions
will be added in following patches.
gas/ChangeLog:
2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Docs update.
* config/tc-aarch64.c (armv8.7-a): New arch.
* doc/c-aarch64.texi (-march=armv8.7-a): Update docs.
include/ChangeLog:
2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_7): New feature bitmask.
(AARCH64_ARCH_V8_7): New arch feature set.
opcodes/ChangeLog:
2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-tbl.h (ARMV8_7): New macro.
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gas/
* testsuite/gas/csky/enhance_dsp.s : Change plsl.u16 to plsl.16.
* testsuite/gas/csky/enhance_dsp.d : Change plsl.u16 to plsl.16.
opcodes/
* csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16.
Change-Id: Ifb43573192e215527355f6541365b9f6a8ec80a4
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gas/
* config/tc-csky.c (get_operand_value): Add handler for
OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
* testsuite/gas/csky/csky_vdsp.d : Fix the disassembling
for vector register.
opcodes/
* csky-dis.c (csky_output_operand): Add handler for
OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
* csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
(OPRND_TYPE_IMM5b_VSH): New enum.
(csky_v2_opcodes): Fix and add some instructions for VDSPV1.
Change-Id: Ia5675d7b716fe5c331e6121ad8f83061ef6454bb
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gas/
* testsuite/gas/i386/avx-vnni.d: Change psuedo prefix from
{vex3} to {vex}
* testsuite/gas/i386/x86-64-avx-vnni.d: Likewise.
opcodes/
* i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.
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This patch introduces BRBE (Branch Record Buffer Extension) system
registers.
Note: as this is register only extension we do not want to hide these
registers behind -march flag going forward (they should be enabled by
default).
gas/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Docs update.
* testsuite/gas/aarch64/brbe-invalid.d: New test.
* testsuite/gas/aarch64/brbe-invalid.l: New test.
* testsuite/gas/aarch64/brbe-invalid.s: New test.
* testsuite/gas/aarch64/brbe.d: New test.
* testsuite/gas/aarch64/brbe.s: New test.
opcodes/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add BRBE system registers.
|
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This patch introduces CSRE (Call Stack Recorder Extension) system
registers.
Note: as this is register only extension we do not want to hide these
registers behind -march flag going forward (they should be enabled by
default).
CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size
of a Call stack record) instruction. This instruction will be added in
a following, separate patch. This change only adds CSRE system
registers.
gas/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Docs update.
* testsuite/gas/aarch64/csre-invalid.d: New test.
* testsuite/gas/aarch64/csre-invalid.l: New test.
* testsuite/gas/aarch64/csre-invalid.s: New test.
* testsuite/gas/aarch64/csre.d: New test.
* testsuite/gas/aarch64/csre.s: New test.
opcodes/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: New CSRE system registers defined.
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Remove the duplicated entry in opcodes/po/es.po:
binutils-gdb/opcodes/po/es.po:749: duplicate message definition...
binutils-gdb/opcodes/po/es.po:742: ...this is the location of the first definition
* po/es.po: Remove the duplicated entry.
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number.
bfd * po/es.po: Fix printf format
binutils * windmc.c: Fix printf format
gas * config/tc-arc.c: Fix printf format
opcodes * po/es.po: Fix printf format
sim * arm/armos.c: Fix printf format
* ppc/emul_netbsd.c: Fix printf format
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
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gas/
* config/tc-i386.c (cpu_arch): Add CPU_ZNVER3_FLAGS flags.
(i386_align_code): Add PROCESSOR_ZNVER cases.
* doc/c-i386.texi: Add znver3, snp, invlpgb and tlbsync.
* gas/i386/i386.exp: Add new znver3 test cases.
* gas/i386/arch-14-znver3.d: New.
* gas/i386/arch-14.d: New.
* gas/i386/arch-14.s: New.
* gas/i386/invlpgb.d: New.
* gas/i386/invlpgb64.d: New.
* gas/i386/invlpgb.s: New.
* gas/i386/snp.d: New.
* gas/i386/snp64.d: New.
* gas/i386/snp.s: New.
* gas/i386/tlbsync.d: New.
* gas/i386/tlbsync.s: New.
* gas/i386/x86-64-arch-4-znver3.d: New.
* gas/i386/x86-64-arch-4.d: New.
* gas/i386/x86-64-arch-4.s: New.
opcodes/
* i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
* i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
Add CPU_ZNVER3_FLAGS.
(cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
* i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
* i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
rmpupdate, rmpadjust.
* i386-init.h: Re-generated.
* i386-tbl.h: Re-generated.
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1. Rename CpuVEX_PREFIX to PseudoVexPrefix and
move it from cpu_flags to opcode_modifiers.
2. Delete {vex2} invalid test.
3. Use VexW0 and VexVVVV in the AVX-VNNI instructions.
gas/
* config/tc-i386.c: Move Pseudo Prefix check to match_template.
* testsuite/gas/i386/avx-vnni-inval.l: New file.
* testsuite/gas/i386/avx-vnni-inval.s: Likewise.
* testsuite/gas/i386/avx-vnni.d: Delete invalid {vex2} test.
* testsuite/gas/i386/avx-vnni.s: Likewise.
* testsuite/gas/i386/i386.exp: Add AVX VNNI invalid tests.
* testsuite/gas/i386/x86-64-avx-vnni-inval.l: New file.
* testsuite/gas/i386/x86-64-avx-vnni-inval.s: Likewise.
* testsuite/gas/i386/x86-64-avx-vnni.d: Delete invalid {vex2} test.
* testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
opcodes/
* i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
and move it from cpu_flags to opcode_modifiers.
Use VexW0 and VexVVVV in the AVX-VNNI instructions.
* i386-gen.c: Likewise.
* i386-opc.h: Likewise.
* i386-opc.h: Likewise.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
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Intel AVX VNNI instructions are marked with CpuVEX_PREFIX. Without the
pseudo {vex} prefix, mnemonics of Intel VNNI instructions are encoded
with the EVEX prefix. The pseudo {vex} prefix can be used to encode
mnemonics of Intel VNNI instructions with the VEX prefix.
gas/
* NEWS: Add Intel AVX VNNI.
* config/tc-i386.c (cpu_arch): Add .avx_vnni and noavx_vnni.
(cpu_flags_match): Support CpuVEX_PREFIX.
* doc/c-i386.texi: Document .avx_vnni, noavx_vnni and how to
encode Intel VNNI instructions with VEX prefix.
* testsuite/gas/i386/avx-vnni.d: New file.
* testsuite/gas/i386/avx-vnni.s: Likewise.
* testsuite/gas/i386/x86-64-avx-vnni.d: Likewise.
* testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
* testsuite/gas/i386/i386.exp: Run AVX VNNI tests.
opcodes/
* i386-dis.c (PREFIX_VEX_0F3850): New.
(PREFIX_VEX_0F3851): Likewise.
(PREFIX_VEX_0F3852): Likewise.
(PREFIX_VEX_0F3853): Likewise.
(VEX_W_0F3850_P_2): Likewise.
(VEX_W_0F3851_P_2): Likewise.
(VEX_W_0F3852_P_2): Likewise.
(VEX_W_0F3853_P_2): Likewise.
(prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
(vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
(putop): Add support for "XV" to print "{vex3}" pseudo prefix.
* i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and
CPU_ANY_AVX_VNNI_FLAGS.
(cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
* i386-opc.h (CpuAVX_VNNI): New.
(CpuVEX_PREFIX): Likewise.
(i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
* i386-opc.tbl: Add Intel AVX VNNI instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
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gas/
* NEWS: Add Intel HRESET.
* config/tc-i386.c (cpu_arch): Add .hreset.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document .hreset, nohreset.
* testsuite/gas/i386/i386.exp: Run HRESET tests.
* testsuite/gas/i386/hreset.d: New file.
* testsuite/gas/i386/x86-64-hreset.d: Likewise.
* testsuite/gas/i386/hreset.s: Likewise.
opcodes/
* i386-dis.c (PREFIX_0F3A0F): New.
(MOD_0F3A0F_PREFIX_1): Likewise.
(REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
(RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
(prefix_table): Add PREFIX_0F3A0F.
(mod_table): Add MOD_0F3A0F_PREFIX_1.
(reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
(rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
* i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
CPU_ANY_HRESET_FLAGS.
(cpu_flags): Add CpuHRESET.
(output_i386_opcode): Allow 4 byte base_opcode.
* i386-opc.h (enum): Add CpuHRESET.
(i386_cpu_flags): Add cpuhreset.
* i386-opc.tbl: Add Intel HRESET instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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gas/
* NEWS: Add Intel UINTR.
* config/tc-i386.c (cpu_arch): Add .uintr.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document .uintr and nouintr.
* testsuite/gas/i386/i386.exp: Run UINTR tests.
* testsuite/gas/i386/x86-64-uintr.d: Likewise.
* testsuite/gas/i386/x86-64-uintr.s: Likewise.
opcodes/
* i386-dis.c (enum): Add
PREFIX_MOD_3_0F01_REG_5_RM_4,
PREFIX_MOD_3_0F01_REG_5_RM_5,
PREFIX_MOD_3_0F01_REG_5_RM_6,
PREFIX_MOD_3_0F01_REG_5_RM_7,
X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
(prefix_table): New instructions (see prefixes above).
(rm_table): Likewise
* i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
CPU_ANY_UINTR_FLAGS.
(cpu_flags): Add CpuUINTR.
* i386-opc.h (enum): Add CpuUINTR.
(i386_cpu_flags): Add cpuuintr.
* i386-opc.tbl: Add UINTR insns.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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Replace the prefix byte in non-VEX/EVEX base_opcode with PREFIX_0X66,
PREFIX_0XF2 or PREFIX_0XF3.
gas/
* config/tc-i386.c (load_insn_p): Check opcodeprefix == 0 for
base_opcode == 0xfc7.
(match_template): Likewise.
(process_suffix): Check opcodeprefix == PREFIX_0XF2 for CRC32.
(check_byte_reg): Likewise.
(output_insn): Don't add the 0xf3 prefix twice for PadLock
instructions. Don't add prefix from non-VEX/EVEX base_opcode.
opcodes/
* i386-gen.c (process_i386_opcode_modifier): Return 1 for
non-VEX/EVEX/prefix encoding.
(output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
has a prefix byte.
* i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
* i386-tbl.h: Regenerated.
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Rename VexOpcode to OpcodePrefix so that OpcodePrefix can be used for
regular encoding prefix.
gas/
* config/tc-i386.c (build_vex_prefix): Replace vexopcode with
opcodeprefix.
(build_evex_prefix): Likewise.
(is_any_vex_encoding): Don't check vexopcode.
(output_insn): Handle opcodeprefix.
opcodes/
* i386-gen.c (opcode_modifiers): Replace VexOpcode with
OpcodePrefix.
* i386-opc.h (VexOpcode): Renamed to ...
(OpcodePrefix): This.
(PREFIX_NONE): New.
(PREFIX_0X66): Likewise.
(PREFIX_0XF2): Likewise.
(PREFIX_0XF3): Likewise.
* i386-opc.tbl (Prefix_0X66): New.
(Prefix_0XF2): Likewise.
(Prefix_0XF3): Likewise.
Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
* i386-tbl.h: Regenerated.
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In 64bit, assembler generates a warning for "sysret":
$ echo sysret | as --64 -o x.o -
{standard input}: Assembler messages:
{standard input}:1: Warning: no instruction mnemonic suffix given and no register operands; using default for `sysret'
Always display suffix for %LQ in 64bit to display "sysretl".
gas/
PR binutils/26704
* testsuite/gas/i386/noreg64-data16.d: Expect sysretl instead of
sysret.
* testsuite/gas/i386/noreg64.d: Likewise.
* testsuite/gas/i386/x86-64-intel64.d: Likewise.
* testsuite/gas/i386/x86-64-opcode.d: Likewise.
opcodes/
PR binutils/26704
* i386-dis.c (putop): Always display suffix for %LQ in 64bit.
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The MODRM byte can be checked to display the instruction name only if the
MODRM byte needed. Clear modrm if the MODRM byte isn't needed so that
modrm field checks in putop like, modrm.mod == N with N != 0, can be done
without checking need_modrm.
gas/
PR binutils/26705
* testsuite/gas/i386/x86-64-suffix.s: Add "mov %rsp,%rbp" before
sysretq.
* testsuite/gas/i386/x86-64-suffix-intel.d: Updated.
* testsuite/gas/i386/x86-64-suffix.d: Likewise.
opcodes/
PR binutils/26705
* i386-dis.c (print_insn): Clear modrm if not needed.
(putop): Check need_modrm for modrm.mod != 3. Don't check
need_modrm for modrm.mod == 3.
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the AArch64 architecture.
gas * testsuite/gas/aarch64/etm-ro-invalid.d: New test.
* testsuite/gas/aarch64/etm-ro-invalid.l: New test.
* testsuite/gas/aarch64/etm-ro-invalid.s: New test.
* testsuite/gas/aarch64/etm-ro.s: New test.
* testsuite/gas/aarch64/etm-wo-invalid.d: New test.
* testsuite/gas/aarch64/etm-wo-invalid.l: New test.
* testsuite/gas/aarch64/etm-wo-invalid.s: New test.
* testsuite/gas/aarch64/etm-wo.s: New test.
* testsuite/gas/aarch64/etm.s: New test.
* testsuite/gas/aarch64/sysreg.d: system register s2_1_c0_c3_0 disassembled
now to trcstatr.
opcodes * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
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