Age | Commit message (Collapse) | Author | Files | Lines |
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Over the years I've seen a number of instances where people used
lea (%reg1), %reg2
or
lea symbol, %reg
despite the same thing being expressable via MOV. Since additionally
LEA often has restrictions towards the ports it can be issued to, while
MOV typically gets dealt with simply by register renaming, transform to
MOV when possible (without growing opcode size and without altering
involved relocation types).
Note that for Mach-O the new 64-bit testcases would fail (for
BFD_RELOC_X86_64_32S not having a representation), and hence get skipped
there.
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st(1) ... st(7) will never be looked up in the hash table, so there's no
point inserting the entries. It's also not really necessary to do a 2nd
hash lookup after parsing the register number, nor is there a real
reason for having both st and st(0) entries. Plus we can easily do away
with the need for st to be first in the table.
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For a long time there hasn't been a need anymore to keep together all
templates with identical mnemonics. Move the MOVQ and MOVABS ones next
to their MOV counterparts. Move the string forms of CMPSD and MOVSD next
to their CMPS / MOVS counterparts. Re-arrange what so fgar was the SSE3
section.
This makes reasonably obvious that MONITOR/MWAIT aren't suitable to
cover by CpuSSE3, but adjusting this is left for another time.
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In commit 79dec6b7baa2 ("x86-64: optimize certain commutative
VEX-encoded insns") I missed the fact that there being subtraction
involved here doesn't matter, as absolute differences get summed up.
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This way not only the overall (source) table size shrinks by quite a
bit and the risk of related templates going out of sync with one another
gets lowered, but also (dis)similarities between neighboring templates
become easier to spot.
Note that for certain SSE2AVX templates this results in benign attribute
changes:
- LDMXCSR and STMXCSR: NoAVX gets set,
- MOVMSKPS, PMOVMSKB, PEXTR{B,W} (register destination), and PINSR{B,W}
(register source): IgnoreSize and NoRex64 get set,
- CVT{DQ,PS}2PD, CVTSD2SS, MOVMSKPD, MOVDDUP, PMOV{S,Z}X{BW,WD,DQ}, and
ROUNDSD: NoRex64 gets set,
- CVTSS2SD, INSERTPS, PEXTRW (memory destination), PINSRW (memory
source), and PMOV{S,Z}X{BD,WQ,BQ}: IgnoreSize gets set.
Similarly the "normal" (non-SSE2AVX)
- non-64-bit CVTS{I,S}2SD forms get NoRex64 set,
- CMP{EQ,ORD,NEQ,UNORD}{P,S}{S,D} forms get C set,
all again in a benign way.
The remaining differences in the generated table are due to re-ordering
of entries in the course of being folded into templates.
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Just like is already done for VEX/XOP/EVEX encoded insns, record the
encoding space information in the respective opcode modifier field. Do
this again without changing the source table, but rather by deriving the
values from their existing source representation.
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While all of MMX, SSE, and SSE2 are included in "generic64", they can be
individually disabled. There are two MOVQ forms lacking respective
attributes. While the MMX one would get refused anyway (due to MMX
registers not recognized with .nommx), the assembler did happily accept
the SSE2 form. Add respective CPU settings to both, paralleling what the
MOVD counterparts have.
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For INVLPGB the operand count was wrong (besides %edx there's also %ecx
which is an input to the insn). In this case I see little sense in
retaining the bogus 2-operand template. Plus swapping of the operands
wasn't properly suppressed for Intel syntax.
For PVALIDATE, RMPADJUST, and RMPUPDATE bogus single operand templates
were specified. These get retained, as the address operand is the only
one really needed to expressed non-default address size, but only for
compatibility reasons. Proper multi-operand insn get introduced and the
testcases get adjusted / extended accordingly.
While at it also drop the redundant definition of __amd64__ - we already
have x86_64 defined (or not) to distinguish 64-bit and non-64-bit cases.
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In the majority of cases we can easily determine the length from the
encoding, irrespective of whether a prefix is specified there as well.
We further don't even need to record the value in the table entries, as
it's easy enough to determine it (without any guesswork, unless an insn
with major opcode 00 appeared that requires a 2nd opcode byte to be
specified explicitly) when installing the chosen template for further
processing.
Should an encoding appear which
- has a major opcode byte of 66, F3, or F2,
- requires a 2nd opcode byte to be specified explicitly,
- doesn't have a mandatory prefix
we'd need to convert all templates presently encoding a mandatory prefix
this way to the Prefix_0X<nn> model to eliminate the respective guessing
i386-gen does.
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Just like is already done for legacy encoded insns, record the mandatory
prefix information in the respective opcode modifier field. Do this
without changing the source table, but rather by deriving the values from
their existing source representation.
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This is in preparation of opcode_length going away as a field in the
templates. Identify pseudo prefixes by a base opcode of zero instead:
No real prefix has an opcode of zero. This at the same time allows
dropping a curious special case from i386-gen.
Since most attributes are identical for all pseudo prefixes, take the
opportunity and also template them.
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In preparation to use PREFIX_0X<nn> attributes also in VEX/XOP/EVEX
encoding templates, renumber the pseudo-enumerators such that their
values can then also be used directly in the respective prefix bit
fields.
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To facilitate a subsequent table parser change, re-order CPU flags and
opcode modifier fields. No functional change intended.
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Commit 8b65b8953af2 ("x86: Remove the prefix byte from non-VEX/EVEX
base_opcode") used the opcodeprefix field for two distinct purposes. In
preparation of having VEX/XOP/EVEX and non-VEX templates become similar
in the representatioon of both encoding space and opcode prefixes, split
the field to have a separate one holding an insn's opcode space.
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RepPrefixOk, HLEPrefixOk, and NoTrackPrefixOk can't be specified
together, so can share an enum-like field. IsLockable can be inferred
from HLE setting and hence only needs specifying when neither of them
is present.
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Despite SYSEXIT being an Intel-only insn in long mode, its behavior
there is similar to SYSRET's: Depending on REX.W execution continues in
either 64-bit or compatibility mode. Hence distinguishing by suffix is
as necessary here as it is there.
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CVTPI2PD with a memory operand, unlike CVTPI2PS, doesn't engage MMX
logic. Therefore it
- has a proper AVX equivalent (CVTDQ2PD) and hence can be subject to
SSE2AVX translation and SSE checking,
- should not record MMX use in the respective ELF note.
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gas/
* config/tc-i386.c (cpu_arch): Add CPU_ZNVER3_FLAGS flags.
(i386_align_code): Add PROCESSOR_ZNVER cases.
* doc/c-i386.texi: Add znver3, snp, invlpgb and tlbsync.
* gas/i386/i386.exp: Add new znver3 test cases.
* gas/i386/arch-14-znver3.d: New.
* gas/i386/arch-14.d: New.
* gas/i386/arch-14.s: New.
* gas/i386/invlpgb.d: New.
* gas/i386/invlpgb64.d: New.
* gas/i386/invlpgb.s: New.
* gas/i386/snp.d: New.
* gas/i386/snp64.d: New.
* gas/i386/snp.s: New.
* gas/i386/tlbsync.d: New.
* gas/i386/tlbsync.s: New.
* gas/i386/x86-64-arch-4-znver3.d: New.
* gas/i386/x86-64-arch-4.d: New.
* gas/i386/x86-64-arch-4.s: New.
opcodes/
* i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
* i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
Add CPU_ZNVER3_FLAGS.
(cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
* i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
* i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
rmpupdate, rmpadjust.
* i386-init.h: Re-generated.
* i386-tbl.h: Re-generated.
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1. Rename CpuVEX_PREFIX to PseudoVexPrefix and
move it from cpu_flags to opcode_modifiers.
2. Delete {vex2} invalid test.
3. Use VexW0 and VexVVVV in the AVX-VNNI instructions.
gas/
* config/tc-i386.c: Move Pseudo Prefix check to match_template.
* testsuite/gas/i386/avx-vnni-inval.l: New file.
* testsuite/gas/i386/avx-vnni-inval.s: Likewise.
* testsuite/gas/i386/avx-vnni.d: Delete invalid {vex2} test.
* testsuite/gas/i386/avx-vnni.s: Likewise.
* testsuite/gas/i386/i386.exp: Add AVX VNNI invalid tests.
* testsuite/gas/i386/x86-64-avx-vnni-inval.l: New file.
* testsuite/gas/i386/x86-64-avx-vnni-inval.s: Likewise.
* testsuite/gas/i386/x86-64-avx-vnni.d: Delete invalid {vex2} test.
* testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
opcodes/
* i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
and move it from cpu_flags to opcode_modifiers.
Use VexW0 and VexVVVV in the AVX-VNNI instructions.
* i386-gen.c: Likewise.
* i386-opc.h: Likewise.
* i386-opc.h: Likewise.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
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Intel AVX VNNI instructions are marked with CpuVEX_PREFIX. Without the
pseudo {vex} prefix, mnemonics of Intel VNNI instructions are encoded
with the EVEX prefix. The pseudo {vex} prefix can be used to encode
mnemonics of Intel VNNI instructions with the VEX prefix.
gas/
* NEWS: Add Intel AVX VNNI.
* config/tc-i386.c (cpu_arch): Add .avx_vnni and noavx_vnni.
(cpu_flags_match): Support CpuVEX_PREFIX.
* doc/c-i386.texi: Document .avx_vnni, noavx_vnni and how to
encode Intel VNNI instructions with VEX prefix.
* testsuite/gas/i386/avx-vnni.d: New file.
* testsuite/gas/i386/avx-vnni.s: Likewise.
* testsuite/gas/i386/x86-64-avx-vnni.d: Likewise.
* testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
* testsuite/gas/i386/i386.exp: Run AVX VNNI tests.
opcodes/
* i386-dis.c (PREFIX_VEX_0F3850): New.
(PREFIX_VEX_0F3851): Likewise.
(PREFIX_VEX_0F3852): Likewise.
(PREFIX_VEX_0F3853): Likewise.
(VEX_W_0F3850_P_2): Likewise.
(VEX_W_0F3851_P_2): Likewise.
(VEX_W_0F3852_P_2): Likewise.
(VEX_W_0F3853_P_2): Likewise.
(prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
(vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
(putop): Add support for "XV" to print "{vex3}" pseudo prefix.
* i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and
CPU_ANY_AVX_VNNI_FLAGS.
(cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
* i386-opc.h (CpuAVX_VNNI): New.
(CpuVEX_PREFIX): Likewise.
(i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
* i386-opc.tbl: Add Intel AVX VNNI instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
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gas/
* NEWS: Add Intel HRESET.
* config/tc-i386.c (cpu_arch): Add .hreset.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document .hreset, nohreset.
* testsuite/gas/i386/i386.exp: Run HRESET tests.
* testsuite/gas/i386/hreset.d: New file.
* testsuite/gas/i386/x86-64-hreset.d: Likewise.
* testsuite/gas/i386/hreset.s: Likewise.
opcodes/
* i386-dis.c (PREFIX_0F3A0F): New.
(MOD_0F3A0F_PREFIX_1): Likewise.
(REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
(RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
(prefix_table): Add PREFIX_0F3A0F.
(mod_table): Add MOD_0F3A0F_PREFIX_1.
(reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
(rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
* i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
CPU_ANY_HRESET_FLAGS.
(cpu_flags): Add CpuHRESET.
(output_i386_opcode): Allow 4 byte base_opcode.
* i386-opc.h (enum): Add CpuHRESET.
(i386_cpu_flags): Add cpuhreset.
* i386-opc.tbl: Add Intel HRESET instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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gas/
* NEWS: Add Intel UINTR.
* config/tc-i386.c (cpu_arch): Add .uintr.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document .uintr and nouintr.
* testsuite/gas/i386/i386.exp: Run UINTR tests.
* testsuite/gas/i386/x86-64-uintr.d: Likewise.
* testsuite/gas/i386/x86-64-uintr.s: Likewise.
opcodes/
* i386-dis.c (enum): Add
PREFIX_MOD_3_0F01_REG_5_RM_4,
PREFIX_MOD_3_0F01_REG_5_RM_5,
PREFIX_MOD_3_0F01_REG_5_RM_6,
PREFIX_MOD_3_0F01_REG_5_RM_7,
X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
(prefix_table): New instructions (see prefixes above).
(rm_table): Likewise
* i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
CPU_ANY_UINTR_FLAGS.
(cpu_flags): Add CpuUINTR.
* i386-opc.h (enum): Add CpuUINTR.
(i386_cpu_flags): Add cpuuintr.
* i386-opc.tbl: Add UINTR insns.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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Replace the prefix byte in non-VEX/EVEX base_opcode with PREFIX_0X66,
PREFIX_0XF2 or PREFIX_0XF3.
gas/
* config/tc-i386.c (load_insn_p): Check opcodeprefix == 0 for
base_opcode == 0xfc7.
(match_template): Likewise.
(process_suffix): Check opcodeprefix == PREFIX_0XF2 for CRC32.
(check_byte_reg): Likewise.
(output_insn): Don't add the 0xf3 prefix twice for PadLock
instructions. Don't add prefix from non-VEX/EVEX base_opcode.
opcodes/
* i386-gen.c (process_i386_opcode_modifier): Return 1 for
non-VEX/EVEX/prefix encoding.
(output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
has a prefix byte.
* i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
* i386-tbl.h: Regenerated.
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Rename VexOpcode to OpcodePrefix so that OpcodePrefix can be used for
regular encoding prefix.
gas/
* config/tc-i386.c (build_vex_prefix): Replace vexopcode with
opcodeprefix.
(build_evex_prefix): Likewise.
(is_any_vex_encoding): Don't check vexopcode.
(output_insn): Handle opcodeprefix.
opcodes/
* i386-gen.c (opcode_modifiers): Replace VexOpcode with
OpcodePrefix.
* i386-opc.h (VexOpcode): Renamed to ...
(OpcodePrefix): This.
(PREFIX_NONE): New.
(PREFIX_0X66): Likewise.
(PREFIX_0XF2): Likewise.
(PREFIX_0XF3): Likewise.
* i386-opc.tbl (Prefix_0X66): New.
(Prefix_0XF2): Likewise.
(Prefix_0XF3): Likewise.
Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
* i386-tbl.h: Regenerated.
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gas/
* NEWS: Add TDX.
* config/tc-i386.c (cpu_arch): Add .tdx.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document tdx.
* testsuite/gas/i386/i386.exp: Run tdx tests.
* testsuite/gas/i386/tdx.d: Likewise.
* testsuite/gas/i386/tdx.s: Likewise.
* testsuite/gas/i386/x86-64-tdx.d: Likewise.
* testsuite/gas/i386/x86-64-tdx.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
X86_64_0F01_REG_1_RM_7_P_2.
(prefix_table): Likewise.
(x86_64_table): Likewise.
(rm_table): Likewise.
* i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
and CPU_ANY_TDX_FLAGS.
(cpu_flags): Add CpuTDX.
* i386-opc.h (enum): Add CpuTDX.
(i386_cpu_flags): Add cputdx.
* i386-opc.tbl: Add TDX insns.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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gas/
* NEWS: Add Key Locker.
* config/tc-i386.c (cpu_arch): Add .kl and .wide_kl.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document kl and wide_kl.
* testsuite/gas/i386/i386.exp: Run keylocker tests.
* testsuite/gas/i386/keylocker-intel.d: New test.
* testsuite/gas/i386/keylocker.d: Likewise.
* testsuite/gas/i386/keylocker.s: Likewise.
* testsuite/gas/i386/x86-64-keylocker-intel.d: Likewise.
* testsuite/gas/i386/x86-64-keylocker.d: Likewise.
* testsuite/gas/i386/x86-64-keylocker.s: Likewise.
* testsuite/gas/i386/x86-64-property-10.d: Likewise.
* testsuite/gas/i386/property-10.d: Likewise.
* testsuite/gas/i386/property-10.s: Likewise.
opcodes/
* i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
(reg_table): New instructions (see prefixes above).
(prefix_table): Likewise.
(three_byte_table): Likewise.
(mod_table): Likewise
* i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
(cpu_flags): Likewise.
(operand_type_init): Likewise.
* i386-opc.h (enum): Add CpuKL and CpuWide_KL.
(i386_cpu_flags): Add cpukl and cpuwide_kl.
* i386-opc.tbl: Add KL and WIDE_KL insns.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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Use Prefix_XXX for pseudo prefixes. Add {disp16} pseudo prefix and
replace {disp32} pseudo prefix with {disp16} in 16-bit mode test.
Check invalid {disp16}/{disp32} pseudo prefixes.
gas/
PR gas/26305
* config/tc-i386.c (_i386_insn::disp_encoding): Add
disp_encoding_16bit.
(parse_insn): Check Prefix_XXX for pseudo prefixes. Handle
{disp16}.
(build_modrm_byte): Handle {disp16}.
(i386_index_check): Check invalid {disp16} and {disp32} pseudo
prefixes.
* doc/c-i386.texi: Update {disp32} documentation and document
{disp16}.
* testsuite/gas/i386/i386.exp: Run x86-64-inval-pseudo.
* testsuite/gas/i386/inval-pseudo.s: Add {disp32}/{disp16}
tests.
* testsuite/gas/i386/pseudos.s: Add {disp8}/{disp32} vmovaps
tests with 128-byte displacement. Add {disp16} tests.
* testsuite/gas/i386/x86-64-pseudos.s: Add {disp8}/{disp32}
vmovaps test. Add (%r13)/(%r13d) tests.
* testsuite/gas/i386/x86-64-inval-pseudo.l: New file.
* testsuite/gas/i386/x86-64-inval-pseudo.s: Likewise.
* testsuite/gas/i386/inval-pseudo.l: Updated.
* testsuite/gas/i386/pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
opcodes/
PR gas/26305
* i386-opc.h (Prefix_Disp8): New.
(Prefix_Disp16): Likewise.
(Prefix_Disp32): Likewise.
(Prefix_Load): Likewise.
(Prefix_Store): Likewise.
(Prefix_VEX): Likewise.
(Prefix_VEX3): Likewise.
(Prefix_EVEX): Likewise.
(Prefix_REX): Likewise.
(Prefix_NoOptimize): Likewise.
* i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
* i386-tbl.h: Regenerated.
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gas/
* doc/c-i386.texi: Document amx_int8, amx_bf16 and amx_tile.
* config/tc-i386.c (i386_error): Add invalid_sib_address.
(cpu_arch): Add .amx_int8, .amx_bf16 and .amx_tile.
(cpu_noarch): Add noamx_int8, noamx_bf16 and noamx_tile.
(match_simd_size): Add tmmword check.
(operand_type_match): Add tmmword.
(type_names): Add rTMM.
(i386_error): Add invalid_tmm_register_set.
(check_VecOperands): Handle invalid_sib_address and
invalid_tmm_register_set.
(match_template): Handle invalid_sib_address.
(build_modrm_byte): Handle non-vector SIB and zmmword.
(i386_index_check): Disallow RegIP for non-vector SIB.
(check_register): Handle zmmword.
* testsuite/gas/i386/i386.exp: Add AMX new tests.
* testsuite/gas/i386/intel-regs.d: Add tmm.
* testsuite/gas/i386/intel-regs.s: Add tmm.
* testsuite/gas/i386/x86-64-amx-intel.d: New.
* testsuite/gas/i386/x86-64-amx-inval.l: New.
* testsuite/gas/i386/x86-64-amx-inval.s: New.
* testsuite/gas/i386/x86-64-amx.d: New.
* testsuite/gas/i386/x86-64-amx.s: New.
* testsuite/gas/i386/x86-64-amx-bad.d: New.
* testsuite/gas/i386/x86-64-amx-bad.s: New.
opcodes/
* i386-dis.c (TMM): New.
(EXtmm): Likewise.
(VexTmm): Likewise.
(MVexSIBMEM): Likewise.
(tmm_mode): Likewise.
(vex_sibmem_mode): Likewise.
(REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
(MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
(MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
(MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
(MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
(MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
(MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
(MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
(MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
(MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
(MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
(MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
(RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
(PREFIX_VEX_0F3849_X86_64): Likewise.
(PREFIX_VEX_0F384B_X86_64): Likewise.
(PREFIX_VEX_0F385C_X86_64): Likewise.
(PREFIX_VEX_0F385E_X86_64): Likewise.
(X86_64_VEX_0F3849): Likewise.
(X86_64_VEX_0F384B): Likewise.
(X86_64_VEX_0F385C): Likewise.
(X86_64_VEX_0F385E): Likewise.
(VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
(VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
(VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
(VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
(VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
(VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
(VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
(VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
(VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
(VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
(VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
(VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
(VEX_W_0F3849_X86_64_P_0): Likewise.
(VEX_W_0F3849_X86_64_P_2): Likewise.
(VEX_W_0F3849_X86_64_P_3): Likewise.
(VEX_W_0F384B_X86_64_P_1): Likewise.
(VEX_W_0F384B_X86_64_P_2): Likewise.
(VEX_W_0F384B_X86_64_P_3): Likewise.
(VEX_W_0F385C_X86_64_P_1): Likewise.
(VEX_W_0F385E_X86_64_P_0): Likewise.
(VEX_W_0F385E_X86_64_P_1): Likewise.
(VEX_W_0F385E_X86_64_P_2): Likewise.
(VEX_W_0F385E_X86_64_P_3): Likewise.
(names_tmm): Likewise.
(att_names_tmm): Likewise.
(intel_operand_size): Handle void_mode.
(OP_XMM): Handle tmm_mode.
(OP_EX): Likewise.
(OP_VEX): Likewise.
* i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
CpuAMX_BF16 and CpuAMX_TILE.
(operand_type_shorthands): Add RegTMM.
(operand_type_init): Likewise.
(operand_types): Add Tmmword.
(cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
(cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
* i386-opc.h (CpuAMX_INT8): New.
(CpuAMX_BF16): Likewise.
(CpuAMX_TILE): Likewise.
(SIBMEM): Likewise.
(Tmmword): Likewise.
(i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
(i386_opcode_modifier): Extend width of fields vexvvvv and sib.
(i386_operand_type): Add tmmword.
* i386-opc.tbl: Add AMX instructions.
* i386-reg.tbl: Add AMX registers.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
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Just like other VEX-encoded scalar insns do.
Besides a testcase for this behavior also introduce one to verify that
XOP scalar insns don't honor -mavxscalar=256, as they don't ignore
XOP.L.
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We check register-only source operand to decide if two source operands of
VEX encoded instructions should be swapped. But source operands in AMX
instructions with two source operands swapped are all register-only
operand. Add SwapSources to indicate two source operands should be
swapped.
gas/
* config/tc-i386.c (build_modrm_byte): Check vexswapsources to
swap two source operands.
opcodes/
* i386-gen.c (opcode_modifiers): Add VexSwapSources.
* i386-opc.h (VexSwapSources): New.
(i386_opcode_modifier): Add vexswapsources.
* i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
with two source operands swapped.
* i386-tbl.h: Regenerated.
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The correct mnemonic is xsusldtrk, not xsuspldtrk.
gas/
PR gas/26115
* testsuite/gas/i386/tsxldtrk.d: Replace xsuspldtrk with
xsusldtrk.
* testsuite/gas/i386/tsxldtrk.s: Likewise.
* testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise.
* testsuite/gas/i386/x86-64-tsxldtrk.s: Likewise.
opcodes/
PR gas/26115
* i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
* i386-opc.tbl: Likewise.
* i386-tbl.h: Regenerated.
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gas/
* config/tc-i386.c (cpu_arch): Add .TSXLDTRK.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document TSXLDTRK.
* testsuite/gas/i386/i386.exp: Run TSXLDTRK tests.
* testsuite/gas/i386/tsxldtrk.d: Likewise.
* testsuite/gas/i386/tsxldtrk.s: Likewise.
* testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
(prefix_table): New instructions (see prefixes above).
(rm_table): Likewise.
* i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
CPU_ANY_TSXLDTRK_FLAGS.
(cpu_flags): Add CpuTSXLDTRK.
* i386-opc.h (enum): Add CpuTSXLDTRK.
(i386_cpu_flags): Add cputsxldtrk.
* i386-opc.tbl: Add XSUSPLDTRK insns.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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gas/
* config/tc-i386.c (cpu_arch): Add .serialize.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document serialize.
* testsuite/gas/i386/i386.exp: Run serialize tests
* testsuite/gas/i386/serialize.d: Likewise.
* testsuite/gas/i386/x86-64-serialize.d: Likewise.
* testsuite/gas/i386/serialize.s: Likewise.
opcodes/
* i386-dis.c (prefix_table): New instructions serialize.
* i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
CPU_ANY_SERIALIZE_FLAGS.
(cpu_flags): Add CpuSERIALIZE.
* i386-opc.h (enum): Add CpuSERIALIZE.
(i386_cpu_flags): Add cpuserialize.
* i386-opc.tbl: Add SERIALIZE insns.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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These all follow a common pattern.
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These all follow common patterns.
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These all follow an almost common pattern, again with the exception of
being commutative, which can be easily taken care of.
Note that, as an intended side effect (and in fact one of the reason to
introduce templates), AVX long-form pseudo-ops get introduced alongside
the already existing AVX512 ones.
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These all follow an almost common pattern, with the exception of being
commutative. This exception can be easily taken care of.
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In order to reduce redundancy as well as the chance of things going out
of sync (see a later patch for an example), make the opcode table
generator capable of recognizing and expanding templated templates. Use
the new capability for compacting the general purpose conditional insns.
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Presumably as a result of various changes over the last several months,
and - for some of them - with a generalization of logic in
match_mem_size() plus mirroring of this generalization into the
broadcast handling logic of check_VecOperands(), various register-only
templates can be foled into their respective memory forms. This in
particular then also allows dropping a few more instances of IgnoreSize.
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Even after commit dc2be329b950 ("i386: Only check suffix in instruction
mnemonic"), by which many of its uses have become unnecessary (some were
unnecessary even before), IgnoreSize is still used for various slightly
different purposes:
- to suppress emission of an operand size prefix,
- in Intel syntax mode to zap "derived" suffixes in certain cases and to
skip certain checks of remaining "derived" suffixes,
- to suppress ambiguous operand size / missing suffix diagnostics,
- for prefixes to suppress the "stand-alone ... prefix" warning.
Drop entirely unnecessary ones and where possible also replace instances
by the more focused (because of having just a single purpose) NoRex64.
To further restrict when IgnoreSize is needed, also generalize the logic
when to skip a template because of a present or derived L or Q suffix,
by skipping immediate operands. Additionally consider mask registers and
VecSIB there.
Note that for the time being the attribute needs to be kept in place on
MMX/SSE/etc insns (but not on VEX/EVEX encoded ones unless an operand
template of them allows for only non-SIMD-register actuals) allowing for
Dword operands - the logic when to emit a data size prefix would need
further adjustment first.
Note also that the memory forms of {,v}pinsrw get their permission for
an L or Q suffix dropped. I can only assume that it being this way was a
cut-and-paste mistake from the register forms, as the latter
specifically have NoRex64 set, and the {,v}pextrw counterparts don't
allow these suffixes either.
Convert VexW= again to their respective VexW* on lines touched anyway.
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As of commit dc2be329b950 ("i386: Only check suffix in instruction
mnemonic") these have been accepted even with "qword ptr" operand size
specifier, but in 64-bit mode they're now wrongly having a REX prefix
(with REX.W set) emitted in this case. These aren't Intel syntax
mnemonics, so rather than fixing code generation, let's simply reject
them. As a result, the Qword attribute can then be dropped, too.
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When the template specifies any of the possible VexW settings, we can
use this instead of a separate NoRex64 to suppress the setting of REX_W.
Note that this ends up addressing an inconsistency between VEX- and
EVEX-encoded VEXTRACTPS, VPEXTR{B,W}, and VPINSR{B,W} - while the former
avoided setting VEX.W, the latter pointlessly set EVEX.W when there is a
64-bit GPR operand. Adjust the testcase to cover both cases.
Convert VexW= to their respective VexW* on lines touched anyway.
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It is almost entirely redundant with Size64, and the sole case (CRC32)
where direct replacement isn't possible can easily be taken care of in
another way.
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For proper code generation in 16-bit mode (or to avoid the "same type of
prefix used twice" diagnostic there), IgnoreSize is needed on certain
templates allowing for just 32-(and maybe 64-)bit operands.
Beyond adding tests for the previously broken cases, also add ones for
the previously working cases where IgnoreSize is needed for the same
reason (leaving out MPX for now, as that'll require an assembler change
first). Some minor adjustments to tests get done such that re-use of the
same code for 16-bit code generation testing becomes easier.
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Allowing 64-bit registers is misleading here: Elsewhere these get allowed
when there's no difference between either variant, because of 32-bit
destination registers having their upper halves zeroed in 64-bit mode.
Here, however, they're source registers, and hence specifying 64-bit
registers would lead to the ambiguity of whether the upper 32 bits
actually matter.
Additionally, for proper code generation in 16-bit mode, IgnoreSize is
needed on both.
And finally, just like for e.g. MONITOR/MWAIT, add variants with all
input registers explicitly specified.
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It has been publicly documented for quite some time, albeit not in the
"General-Purpose and System Instructions" volume:
https://www.amd.com/system/files/TechDocs/24593.pdf.
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Since an instruction template can't have both IgnoreSize and DefaultSize,
this patch replaces IgnoreSize and DefaultSize with MnemonicSize.
gas/
* config/tc-i386.c (match_template): Replace ignoresize and
defaultsize with mnemonicsize.
(process_suffix): Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
with MnemonicSize.
* i386-opc.h (IGNORESIZE): New.
(DEFAULTSIZE): Likewise.
(IgnoreSize): Removed.
(DefaultSize): Likewise.
(MnemonicSize): New.
(i386_opcode_modifier): Replace ignoresize/defaultsize with
mnemonicsize.
* i386-opc.tbl (IgnoreSize): New.
(DefaultSize): Likewise.
* i386-tbl.h: Regenerated.
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According to gas manual, suffix in instruction mnemonics isn't always
required:
When there is no sizing suffix and no (suitable) register operands to
deduce the size of memory operands, with a few exceptions and where long
operand size is possible in the first place, operand size will default
to long in 32- and 64-bit modes.
This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and
vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they
must be allowed without suffix in AT&T syntax.
gas/
PR gas/25622
* testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
x86-64-default-suffix-avx.
* testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
* testsuite/gas/i386/noreg64.d: Updated.
* testsuite/gas/i386/noreg64.l: Likewise.
* testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
* testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
* testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
opcodes/
PR gas/25622
* i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
* i386-tbl.h: Regenerated.
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AMD ABM has 2 instructions: popcnt and lzcnt. ABM CPUID feature bit has
been reused for lzcnt and a POPCNT CPUID feature bit is added for popcnt
which used to be the part of SSE4.2. This patch removes CpuABM and adds
CpuPOPCNT. It changes ABM to enable both lzcnt and popcnt, changes SSE4.2
to also enable popcnt.
gas/
* config/tc-i386.c (cpu_arch): Add .popcnt.
* doc/c-i386.texi: Remove abm and .abm. Add popcnt and .popcnt.
Add a tab before @samp{.sse4a}.
opcodes/
* i386-gen.c (cpu_flag_init): Replace CpuABM with
CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
CPU_POPCNT_FLAGS.
(cpu_flags): Remove CpuABM. Add CpuPOPCNT.
* i386-opc.h (CpuABM): Removed.
(CpuPOPCNT): New.
(i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
* i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
popcnt. Remove CpuABM from lzcnt.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
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