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path: root/opcodes/i386-tbl.h
AgeCommit message (Expand)AuthorFilesLines
2022-08-16x86: template-ize certain vector conversion insnsJan Beulich1-80/+97
2022-08-16x86: template-ize vector packed byte/word integer insnsJan Beulich1-618/+618
2022-08-16x86: re-order AVX512 S/G templatesJan Beulich1-157/+157
2022-08-16x86: template-ize vector packed dword/qword integer insnsJan Beulich1-419/+419
2022-08-16x86: template-ize packed/scalar vector floating point insnsJan Beulich1-3143/+3143
2022-08-09x86-64: adjust MOVQ to/from SReg attributesJan Beulich1-2/+2
2022-08-09x86: adjust MOVSD attributesJan Beulich1-2/+2
2022-08-09x86: fold AVX VGATHERDPD / VPGATHERDQJan Beulich1-40/+6
2022-08-09x86: allow use of broadcast with X/Y/Z-suffixed AVX512-FP16 insnsJan Beulich1-36/+36
2022-08-09x86/Intel: split certain AVX512-FP16 VCVT*2PH templatesJan Beulich1-6/+96
2022-08-03x86: properly mark i386-only insnsJan Beulich1-21/+21
2022-08-03x86: also use D for MOVBEJan Beulich1-16/+1
2022-08-02x86: XOP shift insns don't really allow B suffixJan Beulich1-16/+16
2022-08-01x86: SKINIT with operand needs IgnoreSizeJan Beulich1-1/+1
2022-07-29x86: drop stray NoRex64 from KeyLocker insnsJan Beulich1-3/+3
2022-07-21x86: replace wrong attributes on VCVTDQ2PH{X,Y}Jan Beulich1-2/+2
2022-07-21x86/Intel: correct AVX512F scatter insn element sizesJan Beulich1-4/+4
2022-07-18x86: correct VMOVSH attributesJan Beulich1-3/+3
2022-07-18x86: re-order insn template fieldsJan Beulich1-3715/+3715
2022-07-06x86: make D attribute usable for XOP and FMA4 insnsJan Beulich1-656/+34
2022-07-04x86: fold Disp32S and Disp32Jan Beulich1-12785/+12800
2022-06-29x86: drop stray NoRex64 from XBEGINJan Beulich1-1/+1
2022-05-27x86: re-work AVX512 embedded rounding / SAEJan Beulich1-10941/+591
2022-04-27x86: VFPCLASSSH is Evex.LLIGJan Beulich1-1/+1
2022-04-19x86: VCMPSH is Evex.LLIGJan Beulich1-94/+94
2022-04-19x86: drop stray CheckRegSize from VFPCLASSPHJan Beulich1-1/+1
2022-03-18x86: also fold remaining multi-vector-size shift insnsJan Beulich1-339/+50
2022-03-18x86: drop stray CheckRegSize from VEXTRACT{F,I}32X4Jan Beulich1-2/+2
2022-03-18x86: fold certain AVX2 templates into their AVX counterpartsJan Beulich1-2092/+462
2022-03-17x86: drop L1OM/K1OM support from gasJan Beulich1-5440/+5440
2022-01-06x86: drop NoAVX insn attributeJan Beulich1-4472/+4472
2022-01-06x86: drop NoAVX from POPCNTJan Beulich1-1/+1
2022-01-06x86: drop some "comm" template parametersJan Beulich1-48/+48
2022-01-06x86: templatize FMA insn templatesJan Beulich1-747/+747
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili1-15911/+23504
2021-07-14x86: Add int1 as one byte opcode 0xf1H.J. Lu1-0/+13
2021-04-26x86: optimize LEAJan Beulich1-1/+1
2021-03-30x86: adjust st(<N>) parsingJan Beulich1-5/+1
2021-03-29x86: move some opcode table entriesJan Beulich1-459/+459
2021-03-29x86: VPSADBW's source operands are also commutativeJan Beulich1-3/+3
2021-03-29x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich1-356/+356
2021-03-29x86: derive opcode encoding space attribute from base opcodeJan Beulich1-1596/+1596
2021-03-26x86-64: don't accept supposedly disabled MOVQ formsJan Beulich1-2/+2
2021-03-25x86: fix AMD Zen3 insnsJan Beulich1-1/+52
2021-03-24x86: derive opcode length from opcode valueJan Beulich1-4034/+4034
2021-03-24x86: derive mandatory prefix attribute from base opcodeJan Beulich1-4974/+4974
2021-03-24x86: don't use opcode_length to identify pseudo prefixesJan Beulich1-11/+11
2021-03-23x86: re-number PREFIX_0X<nn>Jan Beulich1-148/+148
2021-03-23x86: re-order two fields of struct insn_templateJan Beulich1-12099/+12099
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