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path: root/opcodes/i386-opc.tbl
AgeCommit message (Expand)AuthorFilesLines
2022-07-21x86: replace wrong attributes on VCVTDQ2PH{X,Y}Jan Beulich1-2/+2
2022-07-21x86/Intel: correct AVX512F scatter insn element sizesJan Beulich1-4/+4
2022-07-18x86: correct VMOVSH attributesJan Beulich1-2/+2
2022-07-06x86: make D attribute usable for XOP and FMA4 insnsJan Beulich1-50/+25
2022-07-04x86: fold Disp32S and Disp32Jan Beulich1-7/+8
2022-06-29x86: drop stray NoRex64 from XBEGINJan Beulich1-1/+1
2022-05-27x86: re-work AVX512 embedded rounding / SAEJan Beulich1-512/+262
2022-04-27x86: VFPCLASSSH is Evex.LLIGJan Beulich1-2/+1
2022-04-19x86: VCMPSH is Evex.LLIGJan Beulich1-4/+4
2022-04-19x86: drop stray CheckRegSize from VFPCLASSPHJan Beulich1-1/+1
2022-03-18x86: also fold remaining multi-vector-size shift insnsJan Beulich1-36/+17
2022-03-18x86: drop stray CheckRegSize from VEXTRACT{F,I}32X4Jan Beulich1-2/+2
2022-03-18x86: fold certain AVX2 templates into their AVX counterpartsJan Beulich1-192/+96
2022-01-06x86: drop NoAVX insn attributeJan Beulich1-44/+44
2022-01-06x86: drop NoAVX from POPCNTJan Beulich1-1/+1
2022-01-06x86: drop some "comm" template parametersJan Beulich1-42/+42
2022-01-06x86: templatize FMA insn templatesJan Beulich1-269/+83
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili1-0/+366
2021-07-14x86: Add int1 as one byte opcode 0xf1H.J. Lu1-0/+1
2021-04-26x86: optimize LEAJan Beulich1-1/+1
2021-03-29x86: move some opcode table entriesJan Beulich1-30/+31
2021-03-29x86: VPSADBW's source operands are also commutativeJan Beulich1-3/+3
2021-03-29x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich1-567/+281
2021-03-29x86: undo Prefix_0X<nn> use in opcode tableJan Beulich1-369/+365
2021-03-26x86-64: don't accept supposedly disabled MOVQ formsJan Beulich1-2/+2
2021-03-25x86: fix AMD Zen3 insnsJan Beulich1-3/+7
2021-03-24x86: derive opcode length from opcode valueJan Beulich1-3409/+3409
2021-03-24x86: don't use opcode_length to identify pseudo prefixesJan Beulich1-13/+8
2021-03-23x86: split opcode prefix and opcode space representationJan Beulich1-2142/+2149
2021-03-09x86: fold some prefix related attributes into a single oneJan Beulich1-41/+48
2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich1-1/+1
2021-03-03x86: infer operand count of templatesJan Beulich1-3419/+3419
2021-02-16x86: CVTPI2PD has special behaviorJan Beulich1-1/+3
2021-02-16x86: have preprocessor expand macrosJan Beulich1-0/+5
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-0/+26
2020-10-16Enhancement for avx-vnni patchCui,Lili1-4/+4
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-0/+10
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-0/+6
2020-10-14x86: Support Intel UINTRLili Cui1-0/+10
2020-10-14x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu1-344/+344
2020-10-13x86: Rename VexOpcode to OpcodePrefixH.J. Lu1-2140/+2144
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-0/+9
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-0/+16
2020-07-30x86: Add {disp16} pseudo prefixH.J. Lu1-10/+11
2020-07-10x86: Add support for Intel AMX instructionsLili Cui1-0/+23
2020-07-08x86: FMA4 scalar insns ignore VEX.LJan Beulich1-16/+16
2020-07-02x86: Add SwapSourcesH.J. Lu1-5/+5
2020-06-26i386-opc.tbl: Add a blank lineH.J. Lu1-0/+1
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