aboutsummaryrefslogtreecommitdiff
path: root/opcodes/i386-opc.tbl
AgeCommit message (Expand)AuthorFilesLines
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu1-1/+1
2016-11-09X86: Merge AVX512F vmovqH.J. Lu1-8/+4
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-0/+12
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist1-0/+16
2016-10-21X86: Remove pcommit instructionH.J. Lu1-6/+0
2016-08-24X86: Add ptwrite instructionH.J. Lu1-0/+6
2016-07-01x86: allow suffix-less movzw and 64-bit movzbJan Beulich1-12/+3
2016-07-01x86: remove stray instruction attributesJan Beulich1-44/+44
2016-07-01x86/Intel: fix operand checking for MOVSDJan Beulich1-2/+2
2016-06-03Handle indirect branches for AMD64 and Intel64H.J. Lu1-2/+4
2016-05-27Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu1-4/+4
2016-05-10Enable Intel RDPID instruction.Alexander Fomin1-0/+7
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-09Implement Intel OSPKE instructionsH.J. Lu1-0/+7
2015-06-30Add support for monitorx/mwaitx instructionsAmit Pawar1-0/+13
2015-06-01x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}Jan Beulich1-0/+6
2015-05-18Remove Disp32 from AMD64 direct call/jmpH.J. Lu1-2/+2
2015-05-15Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu1-2/+4
2015-05-11Remove Disp16|Disp32 from 64-bit direct branchesH.J. Lu1-2/+3
2015-03-17Add znver1 processorGanesh Gopalasubramanian1-0/+7
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-11-17Add AVX512VBMI instructionsIlya Tocar1-0/+17
2014-11-17Add AVX512IFMA instructionsIlya Tocar1-0/+11
2014-11-17Add pcommit instructionIlya Tocar1-0/+6
2014-11-17Add clwb instructionIlya Tocar1-0/+6
2014-07-22Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar1-0/+212
2014-07-22Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar1-0/+385
2014-07-22Add support for AVX512VL versions of AVX512CD instructions.Ilya Tocar1-0/+20
2014-07-22Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.Ilya Tocar1-0/+944
2014-04-04Add support for Intel SGX instructionsIlya Tocar1-0/+7
2014-03-20Fix memory size for gather/scatter instructionsIlya Tocar1-8/+8
2014-03-05Update copyright yearsAlan Modra1-2/+1
2014-02-25Remove bogus vcvtps2ph variant.Ilya Tocar1-1/+0
2014-02-21Add support for CPUID PREFETCHWT1Ilya Tocar1-2/+6
2014-02-20Change cpu for vptestnmd and vptestnmq instructions.Ilya Tocar1-4/+3
2014-02-12Add clflushopt, xsaves, xsavec, xrstorsIlya Tocar1-0/+22
2013-10-12Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcnH.J. Lu1-8/+11
2013-10-08opcodes/Jan Beulich1-9/+9
2013-09-30Add Size64 to movq/vmovq with Reg64 operandH.J. Lu1-8/+8
2013-07-26Add Intel AVX-512 supportH.J. Lu1-0/+1209
2013-07-25Support Intel SHAH.J. Lu1-0/+10
2013-07-24Support Intel MPXH.J. Lu1-41/+54
2013-07-08Replace Xmmword with Qword on cvttps2piH.J. Lu1-1/+1
2013-04-08gas/testsuite/Jan Beulich1-2/+1
2013-02-19Implement Intel SMAP instructionsH.J. Lu1-0/+4
2012-11-20Fix opcode for 64-bit jecxzH.J. Lu1-1/+1
2012-09-20Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu1-1/+1
2012-08-17Add AMD btver1 and btver2 supportH.J. Lu1-1/+1
2012-08-07There were several cases where the registers in the REX encoded rangeJan Beulich1-5/+0
2012-07-31VMOVNTDQA was both misplaced and improperly tagged as being an AVXJan Beulich1-1/+1
generated by cgit v1.1 at 2024-07-25 18:51:21 +0000