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path: root/opcodes/i386-init.h
AgeCommit message (Expand)AuthorFilesLines
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-193/+229
2020-10-16Enhancement for avx-vnni patchCui,Lili1-242/+242
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-241/+259
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-192/+210
2020-10-14x86: Support Intel UINTRLili Cui1-187/+392
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-204/+220
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-181/+213
2020-07-10x86: Add support for Intel AMX instructionsLili Cui1-227/+279
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili1-173/+189
2020-04-02Add support for intel SERIALIZE instructionLiliCui1-171/+187
2020-03-04x86: support VMGEXITJan Beulich1-170/+178
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu1-116/+124
2020-02-16x86: Don't disable SSE3 when disabling SSE4aH.J. Lu1-1/+1
2020-02-16x86: Don't disable SSE4a when disabling SSE4H.J. Lu1-2/+2
2020-02-13x86: fix SSE4a dependencies of ".arch .nosse*"Jan Beulich1-2/+10
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-11-14x86: make JumpAbsolute an insn attributeJan Beulich1-61/+57
2019-11-12x86: fold EsSeg into IsStringJan Beulich1-60/+56
2019-11-12x86: introduce operand type "instance"Jan Beulich1-84/+84
2019-11-08x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich1-87/+87
2019-11-08x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich1-87/+87
2019-11-08x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich1-83/+83
2019-11-08x86: convert SReg from bitfield to enumeratorJan Beulich1-78/+78
2019-11-08x86: introduce operand type "class"Jan Beulich1-0/+4
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich1-166/+182
2019-07-16x86: make RegMem an opcode modifierJan Beulich1-48/+48
2019-07-16x86: fold SReg{2,3}Jan Beulich1-124/+71
2019-07-01x86: drop Vec_Imm4Jan Beulich1-55/+50
2019-06-25x86: correct / adjust debug printingJan Beulich1-9/+14
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-184/+200
2019-06-04Add support for Intel ENQCMD[S] instructionsH.J. Lu1-162/+178
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo1-181/+197
2019-03-19ix86: Disable AVX512F when disabling AVX2H.J. Lu1-6/+6
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-08-11x86: Add CpuCMOV and CpuFXSRH.J. Lu1-417/+449
2018-08-03x86: drop "mem" operand type attributeJan Beulich1-62/+62
2018-07-31x86: drop CpuVREXJan Beulich1-216/+216
2018-07-11x86: drop {,reg16_}inoutportreg variablesJan Beulich1-10/+0
2018-05-30Add znver2 support.Amit Pawar1-0/+8
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu1-151/+183
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist1-183/+151
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist1-151/+183
2018-04-26x86: CpuXSAVE is a prereq for various other featuresJan Beulich1-24/+24
2018-04-26x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich1-151/+151
2018-04-26x86: x87-related adjustmentsJan Beulich1-21/+21
2018-04-17Enable Intel CLDEMOTE instruction.Igor Tsimbalist1-174/+182
2018-04-11Enable Intel WAITPKG instructions.Igor Tsimbalist1-204/+212
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist1-203/+211
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist1-203/+211
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist1-204/+228
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