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path: root/opcodes/i386-dis.c
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2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-11-29x86: Do not dump DS/CS segment overrides for branch hintsBorislav Petkov1-2/+11
2020-11-14x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit modeBorislav Petkov1-5/+20
2020-10-26Change avxvnni disassembler output from {vex3} to {vex}Cui,Lili1-1/+0
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-0/+41
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-6/+37
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-1/+24
2020-10-14x86: Support Intel UINTRLili Cui1-6/+69
2020-10-05x86-64: Always display suffix for %LQ in 64bitH.J. Lu1-1/+1
2020-10-05x86: Clear modrm if not neededH.J. Lu1-4/+8
2020-09-25Put together MOD_VEX_0F38* in i386-dis.c,Cui,Lili1-62/+62
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-4/+61
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-7/+100
2020-09-02ubsan: i386-dis.cAlan Modra1-13/+13
2020-07-21Revert "x86: Don't display eiz with no scale"Jan Beulich1-1/+1
2020-07-15x86: Don't display eiz with no scaleH.J. Lu1-1/+1
2020-07-15x86: move putop() case labels to restore alphabetic sortingJan Beulich1-49/+48
2020-07-15x86: make PUSH/POP disassembly uniformJan Beulich1-30/+20
2020-07-15x86: avoid attaching suffixes to unambiguous insnsJan Beulich1-99/+44
2020-07-14x86-64: Zero-extend lower 32 bits displacement to 64 bitsH.J. Lu1-2/+7
2020-07-14x86/Intel: debug registers are named DRnJan Beulich1-1/+1
2020-07-14x86: drop Rm and the 'L' macroJan Beulich1-74/+54
2020-07-14x86: drop Rdq, Rd, and MaskRJan Beulich1-56/+60
2020-07-14x86: simplify decode of opcodes valid only without any (embedded) prefixJan Beulich1-135/+42
2020-07-14x86: also use %BW / %DQ for kshift*Jan Beulich1-65/+17
2020-07-14x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich1-3474/+788
2020-07-14x86: drop further EVEX table entries that can be served by VEX onesJan Beulich1-12/+8
2020-07-14x86: drop need_vex_regJan Beulich1-48/+15
2020-07-14x86: drop Vex128 and Vex256Jan Beulich1-53/+45
2020-07-14x86: replace %LW by %DQJan Beulich1-9/+9
2020-07-14x86: merge/move logic determining the EVEX disp8 shiftJan Beulich1-29/+16
2020-07-14x86: extend %BW use to VP{COMPRESS,EXPAND}{B,W}Jan Beulich1-12/+7
2020-07-14x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel modeJan Beulich1-37/+15
2020-07-14x86: fold VCMP_Fixup() into CMP_Fixup()Jan Beulich1-70/+45
2020-07-14x86: don't disassemble MOVBE with two suffixesJan Beulich1-43/+5
2020-07-14x86: avoid attaching suffix to register-only CRC32Jan Beulich1-75/+2
2020-07-14x86-64: don't hide an empty but meaningless REX prefixJan Beulich1-5/+9
2020-07-14x86: drop dead code from OP_IMREG()Jan Beulich1-40/+6
2020-07-10x86: Add support for Intel AMX instructionsLili Cui1-5/+346
2020-07-08x86: various XOP insns lack L and/or W bit decodingJan Beulich1-123/+573
2020-07-08x86: FMA4 scalar insns ignore VEX.LJan Beulich1-69/+14
2020-07-08x86: re-work operand swapping for XOP shift/rotate insnsJan Beulich1-74/+24
2020-07-08x86: re-work operand handling for 5-operand XOP insnsJan Beulich1-194/+9
2020-07-08x86: re-work operand swapping for FMA4 and 4-operand XOP insnsJan Beulich1-65/+42
2020-07-07x86: introduce %BW to avoid going through vex_w_table[]Jan Beulich1-11/+3
2020-07-06x86: adjust/correct VFRCZ{P,S}{S,D} decodingJan Beulich1-12/+36
2020-07-06x86: use %LW / %XW instead of going through vex_w_table[]Jan Beulich1-102/+48
2020-07-06x86: most VBROADCAST{F,I}{32,64}x* only accept memory operandsJan Beulich1-8/+16
2020-07-06x86: drop EVEX table entries that can be made served by VEX onesJan Beulich1-30/+15
2020-07-06x86: AVX512 VPERM{D,Q,PS,PD} insns need to honor EVEX.L'LJan Beulich1-0/+4
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