| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-01-08 | Treat the AArch64 register id_aa64mmfr2_el1 as a core system register. | Nick Clifton | 1 | -1/+1 |
| 2021-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2020-11-09 | aarch64: Update LS64 feature with system register | Przemyslaw Wirkus | 1 | -0/+2 |
| 2020-11-09 | aarch64: Limit Rt register number for LS64 load/store instructions | Przemyslaw Wirkus | 1 | -0/+1 |
| 2020-11-04 | aarch64: Update feature RAS system registers | Przemyslaw Wirkus | 1 | -0/+5 |
| 2020-10-28 | aarch64: Add CSR PDEC instruction | Przemyslaw Wirkus | 1 | -0/+4 |
| 2020-10-28 | aarch64: Add DSB instruction Armv8.7-a variant | Przemyslaw Wirkus | 1 | -0/+10 |
| 2020-10-22 | [PATCH][GAS][AArch64] Define BRBE system registers | Przemyslaw Wirkus | 1 | -0/+106 |
| 2020-10-22 | aarch64: Define CSRE system registers | Przemyslaw Wirkus | 1 | -0/+13 |
| 2020-09-28 | This patch introduces ETMv4 (Embedded Trace Macrocell) system registers for t... | Przemyslaw Wirkus | 1 | -0/+216 |
| 2020-09-28 | This patch introduces ETE (Embedded Trace Extension) system registers for the... | Przemyslaw Wirkus | 1 | -0/+6 |
| 2020-09-28 | This patch introduces TRBE (Trace Buffer Extension) system registers for the ... | Przemyslaw Wirkus | 1 | -0/+8 |
| 2020-09-08 | aarch64: Add support for Armv8-R system registers | Alex Coplan | 1 | -9/+70 |
| 2020-08-12 | aarch64: Add support for MPAM system registers | Alex Coplan | 1 | -0/+17 |
| 2020-08-10 | [aarch64] GAS doesn't validate the architecture version for any tlbi register... | Przemyslaw Wirkus | 1 | -102/+96 |
| 2020-06-11 | [PATCH]: aarch64: Refactor representation of system registers | Alex Coplan | 1 | -623/+448 |
| 2020-04-30 | AArch64: add GAS support for UDF instruction | Alex Coplan | 1 | -0/+3 |
| 2020-04-20 | [AArch64, Binutils] Add missing TSB instruction | Sudakshina Das | 1 | -0/+3 |
| 2020-02-26 | Indent labels | Alan Modra | 1 | -1/+1 |
| 2020-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2019-12-17 | ubsan: aarch64: left shift cannot be represented in type 'int64_t' | Alan Modra | 1 | -12/+11 |
| 2019-11-11 | Arm64: fix build with old glibc | Jan Beulich | 1 | -10/+7 |
| 2019-11-07 | [binutils][aarch64] Matrix Multiply extension enablement [8/X] | Matthew Malcomson | 1 | -0/+2 |
| 2019-11-07 | [binutils][aarch64] Bfloat16 enablement [2/X] | Matthew Malcomson | 1 | -0/+1 |
| 2019-10-30 | Modify the ARNM assembler to accept the omission of the immediate argument fo... | Delia Burduv | 1 | -1/+6 |
| 2019-08-22 | [AArch64][gas] Update MTE system register encodings | Kyrylo Tkachov | 1 | -10/+10 |
| 2019-07-23 | [AArch64] Add support for GMID_EL1 register for +memtag | Kyrylo Tkachov | 1 | -1/+3 |
| 2019-07-02 | [AArch64] Fix bogus MOVPRFX warning for GPR form of CPY | Richard Sandiford | 1 | -5/+0 |
| 2019-05-09 | [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand. | Matthew Malcomson | 1 | -0/+2 |
| 2019-05-09 | [binutils][aarch64] New SVE_Zm4_11_INDEX operand. | Matthew Malcomson | 1 | -0/+3 |
| 2019-05-09 | [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand. | Matthew Malcomson | 1 | -6/+12 |
| 2019-05-09 | [binutils][aarch64] New sve_size_sd2 iclass. | Matthew Malcomson | 1 | -0/+1 |
| 2019-05-09 | [binutils][aarch64] New SVE_ADDR_ZX operand. | Matthew Malcomson | 1 | -0/+18 |
| 2019-05-09 | [binutils][aarch64] New SVE_Zm3_11_INDEX operand. | Matthew Malcomson | 1 | -0/+4 |
| 2019-05-09 | [binutils][aarch64] New iclass sve_size_hsd2. | Matthew Malcomson | 1 | -0/+1 |
| 2019-05-09 | [binutils][aarch64] Introduce SVE_IMM_ROT3 operand. | Matthew Malcomson | 1 | -0/+3 |
| 2019-05-09 | [binutils][aarch64] Allow movprfx for SVE2 instructions. | Matthew Malcomson | 1 | -1/+3 |
| 2019-05-01 | [BINUTILS, AArch64] Enable Transactional Memory Extension | Sudakshina Das | 1 | -0/+2 |
| 2019-04-11 | [BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions | Sudakshina Das | 1 | -0/+2 |
| 2019-02-07 | AArch64: Add verifier for By elem Single and Double sized instructions. | Tamar Christina | 1 | -0/+24 |
| 2019-01-25 | AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte... | Sudi Das | 1 | -6/+0 |
| 2019-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2018-12-18 | Include bfd_stdint.h in bfd.h | Alan Modra | 1 | -1/+1 |
| 2018-11-12 | [BINUTILS, AARCH64, 8/8] Add data cache instructions for Memory Tagging Exten... | Sudakshina Das | 1 | -0/+40 |
| 2018-11-12 | [BINUTILS, AARCH64, 7/8] Add system registers for Memory Tagging Extension | Sudakshina Das | 1 | -0/+26 |
| 2018-11-12 | [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 1 | -0/+6 |
| 2018-11-12 | [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten... | Sudakshina Das | 1 | -0/+35 |
| 2018-11-12 | [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex... | Sudakshina Das | 1 | -0/+19 |
| 2018-10-16 | AArch64: Fix error checking for SIMD udot (by element) | Matthew Malcomson | 1 | -1/+2 |
| 2018-10-09 | [PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS | Sudakshina Das | 1 | -0/+14 |
