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path: root/opcodes/aarch64-dis-2.c
AgeCommit message (Expand)AuthorFilesLines
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh1-899/+900
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina1-2924/+3464
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-89/+95
2017-07-24[AArch64] Fix the bit pattern order in the comments in auto-generated fileJiong Wang1-1686/+1686
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina1-179/+203
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-1856/+2294
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li1-2/+2
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-2121/+2158
2016-11-18[AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy1-1151/+1184
2016-11-18[AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy1-1270/+1281
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-1197/+1221
2016-11-11[AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy1-1508/+1640
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy1-1430/+1442
2016-11-11[AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy1-1442/+1640
2016-11-11[AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy1-786/+799
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-115/+7931
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-10/+16
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-25/+32
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-38/+62
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-18/+27
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-19/+57
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-6/+8
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-5/+7
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-0/+20
2016-09-21[AArch64][SVE 16/32] Use specific insert/extract methods for fpimmRichard Sandiford1-1/+2
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-14[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru...Matthew Wahab1-674/+682
2015-12-14[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab1-898/+903
2015-12-14[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab1-754/+809
2015-12-14[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.Matthew Wahab1-1154/+1156
2015-12-14[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.Matthew Wahab1-1264/+1308
2015-12-14[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.Matthew Wahab1-863/+907
2015-12-14[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.Matthew Wahab1-1184/+1228
2015-12-14[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.Matthew Wahab1-874/+1094
2015-12-14[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.Matthew Wahab1-1385/+1704
2015-12-14[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.Matthew Wahab1-727/+826
2015-12-14[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab1-978/+1242
2015-12-11[AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab1-18/+21
2015-12-10[AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab1-18/+19
2015-11-27[AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab1-437/+537
2015-11-27[AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab1-494/+496
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab1-548/+549
2015-11-27[AArch64] Let aliased instructions be their preferred form.Matthew Wahab1-0/+95
2015-06-02[AArch64] Support for ARMv8.1a Adv.SIMD instructionsMatthew Wahab1-1005/+1093
2015-06-02[AArch64] Support for ARMv8.1a Limited Ordering Regions extensionMatthew Wahab1-264/+321
2015-03-10[AARCH64] Remove Load/Store register (unscaled immediate) alias.Jiong Wang1-286/+274
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-09-03[PATCH/AArch64] Generic support for all system registers using mrs and msrJiong Wang1-99/+21
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