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AgeCommit message (Expand)AuthorFilesLines
2020-03-26Re: H8300 use of uninitialised valueAlan Modra1-0/+13
2020-03-26Re: ARC: Use of uninitialised valueAlan Modra1-0/+4
2020-03-25Uninitialised memory read in z80-dis.cAlan Modra1-0/+4
2020-03-22H8300 use of uninitialised valueAlan Modra1-0/+5
2020-03-22ARC: Use of uninitialised valueAlan Modra1-0/+6
2020-03-22NS32K arg_bufs uninitialisedAlan Modra1-0/+7
2020-03-22s12z disassembler tidyAlan Modra1-0/+31
2020-03-20metag uninitialized memory readAlan Modra1-0/+5
2020-03-20NDS32 disassembly of odd sized sectionsAlan Modra1-0/+7
2020-03-20PowerPC disassembly of odd sized sectionsAlan Modra1-0/+7
2020-03-17Replace a couple of assertions in the BFD library that can be triggered by at...Nick Clifton1-0/+5
2020-03-13x86-64: correct mis-named X86_64_0D enumeratorJan Beulich1-0/+5
2020-03-09x86: Also pass -P to $(CPP) when processing i386-opc.tblH.J. Lu1-0/+5
2020-03-09x86: use template for AVX512 integer comparison insnsJan Beulich1-0/+6
2020-03-09x86: use template for XOP integer comparison, shift, and rotate insnsJan Beulich1-0/+6
2020-03-09x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich1-0/+6
2020-03-09x86: use template for SSE floating point comparison insnsJan Beulich1-0/+7
2020-03-09x86: allow opcode templates to be templatedJan Beulich1-0/+10
2020-03-06x86: reduce amount of various VCVT* templatesJan Beulich1-0/+8
2020-03-06x86: drop/replace IgnoreSizeJan Beulich1-0/+6
2020-03-06x86: don't accept FI{LD,STP,STTP}LL in Intel syntax modeJan Beulich1-0/+5
2020-03-06x86: replace NoRex64 on VEX-encoded insnsJan Beulich1-0/+12
2020-03-06x86: drop Rex64 attributeJan Beulich1-0/+9
2020-03-06x86: correct MPX insn w/o base or index encoding in 16-bit modeJan Beulich1-0/+6
2020-03-06x86: add missing IgnoreSizeJan Beulich1-0/+8
2020-03-06x86: refine TPAUSE and UMWAITJan Beulich1-0/+6
2020-03-04x86: support VMGEXITJan Beulich1-0/+12
2020-03-03x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu1-0/+15
2020-03-03The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble...Sergey Belyashov1-0/+6
2020-03-03x86: Allow integer conversion without suffix in AT&T syntaxH.J. Lu1-0/+7
2020-02-26Indent labelsAlan Modra1-0/+12
2020-02-25[ARC][committed] Update int_vector_base aux register.Claudiu Zissulescu1-0/+5
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu1-0/+5
2020-02-19RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.Jim Wilson1-0/+5
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu1-0/+14
2020-02-17x86: fold certain VCVT{,U}SI2S{S,D} templatesJan Beulich1-0/+7
2020-02-17x86: fold AddrPrefixOpReg templatesJan Beulich1-0/+8
2020-02-17x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich1-0/+11
2020-02-16x86: Don't disable SSE3 when disabling SSE4aH.J. Lu1-0/+5
2020-02-17Re: x86: Don't disable SSE4a when disabling SSE4Alan Modra1-0/+4
2020-02-16x86: Don't disable SSE4a when disabling SSE4H.J. Lu1-0/+5
2020-02-14Remove Intel syntax comments on movsx and movzxH.J. Lu1-0/+5
2020-02-14x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich1-0/+8
2020-02-13x86: fix SSE4a dependencies of ".arch .nosse*"Jan Beulich1-0/+7
2020-02-12x86: correct VFPCLASSP{S,D} operand size handlingJan Beulich1-0/+6
2020-02-12x86: fold two JMP templatesJan Beulich1-0/+5
2020-02-12x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich1-0/+10
2020-02-11x86: drop ShortForm attributeJan Beulich1-0/+12
2020-02-11x86: drop stray ShortForm attributesJan Beulich1-0/+6
2020-02-11Ensure *valuep always written by extract_normal returnAlan Modra1-0/+8
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