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2016-01-01Copyright update for binutilsAlan Modra352-443/+447
2016-01-01New 2016 binutils ChangeLog filesAlan Modra1-0/+14
Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01binutils ChangeLog rotationAlan Modra2-0/+0
2015-12-30Fix assorted ChangeLog errorsAlan Modra2-62/+61
2015-12-26Add test for ARMv6-M farcall with no profile infoThomas Preud'homme5-0/+52
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> ld/testsuite/ * ld-arm/arm-elf.exp: Run new test "Thumb-Thumb farcall v6-M (no profile)". * ld-arm/farcall-thumb-thumb-m-no-profile-a.s: New file. * ld-arm/farcall-thumb-thumb-m-no-profile-b.s: Likewise. * ld-arm/farcall-thumb-thumb-m-no-profile.d: Likewise.
2015-12-24Add support for linking ARMv8-M object filesThomas Preud'homme11-0/+77
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * elf32-arm.c (using_thumb_only): Check that profile is 'M' and update logic around Tag_CPU_arch values to return TRUE for ARMv8-M architectures. (tag_cpu_arch_combine): Define v8m_baseline and v8m_mainline and update v4t_plus_v6_m and comb to deal with ARMv8-M Tag_CPU_arch merging logic. (elf32_arm_merge_eabi_attributes): Add Tag_CPU_name values for ARMv8-M. bfd/testsuite/ * ld-arm/arm-elf.exp (armeabitests_common): Run new tests "Thumb-Thumb farcall v8-M", "EABI attribute merging 8", "EABI attribute merging 9" and "EABI attribute merging 10". (Thumb-Thumb farcall v8-M): Renamed to ... (Thumb-Thumb farcall v8-M Mainline): This. (Thumb-Thumb farcall v8-M Baseline): New test. * ld-arm/attr-merge-8a.s: New file. * ld-arm/attr-merge-8b.s: Likewise. * ld-arm/attr-merge-8.attr: Likewise. * ld-arm/attr-merge-9a.s: Likewise. * ld-arm/attr-merge-9b.s: Likewise. * ld-arm/attr-merge-9.out: Likewise. * ld-arm/attr-merge-10a.s: Likewise. * ld-arm/attr-merge-10b.s: Likewise. * ld-arm/attr-merge-10.attr: Likewise.
2015-12-22ARM: Fix exidx coverage for relocatable builds.Yury Usishchev8-46/+117
bfd * elf-bfd.h: Add callback to count additional relocations. * elf32-arm.c (_arm_elf_section_data): Add new counter. (insert_cantunwind_after): Increment relocations counter. (elf32_arm_fix_exidx_coverage): Remove exidx entries and add terminating CANTUNWIND entry only in final builds. (elf32_arm_add_relocation): New function. (elf32_arm_write_section): Add relocations in relocatable builds. (elf32_arm_count_additional_relocs): New function. (elf_backend_count_additional_relocs): New define. * bfd/elflink.c (bfd_elf_final_link): Use callback and adjust size of .rel section. * bfd/elfxx-target.h (elf_backend_count_additional_relocs): New define. ld * emultempl/armelf.em (gld${EMULATION_NAME}_after_allocation): Call elf32_arm_fix_exidx_coverage for relocatable builds. ld/testsuite * ld-arm/arm-elf.exp: New test. * ld-arm/unwind-rel.d: New file. * ld-arm/unwind-rel1.s: New file. * ld-arm/unwind-rel2.s: New file. * ld-arm/unwind-rel3.s: New file.
2015-12-22Add support for ARM's NOREAD section flag.Mickael Guene11-0/+141
include/elf * arm.h: Add arm SHF_ARM_NOREAD section flag. bfd * bfd-in2.h: Regenerate. * section.c: Add SEC_ELF_NOREAD. * elf32-arm.c (elf32_arm_post_process_headers): Only set PF_X attribute if a segment only contains section with SHF_ARM_NOREAD flag. (elf32_arm_fake_sections): Add SEC_ELF_NOREAD conversion. (elf32_arm_section_flags): New function to convert SHF_ARM_NOREAD to bfd flag. (elf32_arm_lookup_section_flags): New function to allow INPUT_SECTION_FLAGS directive with SHF_ARM_NOREAD flag. (elf32_arm_special_sections): Add special sections array to catch section prefix by '.text.noread' pattern. ld/testsuite * ld-arm/arm-elf.exp: New tests. * ld-arm/thumb1-input-section-flag-match.d: New * ld-arm/thumb1-input-section-flag-match.s: New * ld-arm/thumb1-noread-not-present-mixing-two-section.d: New * ld-arm/thumb1-noread-not-present-mixing-two-section.s: New * ld-arm/thumb1-noread-present-one-section.d: New * ld-arm/thumb1-noread-present-one-section.s: New * ld-arm/thumb1-noread-present-two-section.d: New * ld-arm/thumb1-noread-present-two-section.s: New binutils * readelf.c (get_elf_section_flags): Add support for ARM specific section flags.
2015-12-17Add forgotten ChangeLog updates for 72d98d16ed09584660d0cbb759d90f8dfeef2343:Christophe Lyon1-0/+9
2015-12-16 Mickael Guene <mickael.guene@st.com> bfd/ * bfd-in2.h: Regenerate. * reloc.c: Add new relocations. * libbfd.h (bfd_reloc_code_real_names): Add new relocations display names. * elf32-arm.c (elf32_arm_howto_table_1): Add HOWTO for new relocations. (elf32_arm_reloc_map): Add bfd/arm mapping for new relocations. (elf32_arm_final_link_relocate): Implement new relocations resolution. gas/ * doc/c-arm.texi: Add documentation about new directives * config/tc-arm.c (group_reloc_table): Add mapping between gas syntax and new relocations. (do_t_add_sub): Keep new relocations for add operand. (do_t_mov_cmp): Keep new relocations for mov operand. (insns): Use 'shifter operand with possible group relocation' operand parse code for movs operand. (md_apply_fix): Implement mov and add encoding when new relocations on them. (tc_gen_reloc): Add new relocations. (arm_fix_adjustable): Since offset has a limited range ([0:255]) we disable adjust_reloc_syms() for new relocations. gas/testsuite/ * gas/arm/adds-thumb1-reloc-local.d: New * gas/arm/adds-thumb1-reloc-local.s: New * gas/arm/movs-thumb1-reloc-local.d: New * gas/arm/movs-thumb1-reloc-local.s: New include/ * elf/arm.h: Add new arm relocations. ld/testsuite/ * ld-arm/arm-elf.exp (armelftests_common): Add new relocations tests. * ld-arm/thumb1-adds.d: New * ld-arm/thumb1-adds.s: New * ld-arm/thumb1-movs.d: New * ld-arm/thumb1-movs.s: New
2015-12-16[ARM] Add support for thumb1 pcrop relocations.Mickael Guene5-0/+168
To support thumb1 execute-only code we need to support four new relocations (R_ARM_THM_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G2_NC and R_ARM_THM_ALU_ABS_G3_NC). These relocations allow the static linker to finalize construction of symbol address. Typical sequence of code to get address of the symbol foo is then the following : movs r3, #:upper8_15:#foo lsls r3, #8 adds r3, #:upper0_7:#foo lsls r3, #8 adds r3, #:lower8_15:#foo lsls r3, #8 adds r3, #:lower0_7:#foo This will give following sequence of text and relocations after assembly : 4: 2300 movs r3, #0 4: R_ARM_THM_ALU_ABS_G3_NC foo 6: 021b lsls r3, r3, #8 8: 3300 adds r3, #0 8: R_ARM_THM_ALU_ABS_G2_NC foo a: 021b lsls r3, r3, #8 c: 3300 adds r3, #0 c: R_ARM_THM_ALU_ABS_G1_NC foo e: 021b lsls r3, r3, #8 10: 3300 adds r3, #0 10: R_ARM_THM_ALU_ABS_G0_NC foo
2015-12-10ld -r doesn't need plugin for slim lto objectH.J. Lu4-0/+31
Plugin isn't required on slim lto object for relocatable link. bfd/ PR ld/19317 * linker.c (_bfd_generic_link_add_one_symbol): Don't complain plugin needed to handle slim lto object for relocatable link. ld/testsuite/ PR ld/19317 * ld-plugin/lto.exp (lto_no_fat): New. (lto_link_tests): Add a test for PR ld/19317. (lto_run_tests): Likewise. (run_ld_link_tests): Likewise.
2015-12-10ld: Fix LTO for MinGW targetsKwok Cheung Yeung2-2/+11
When creating a dummy BFD for an IR file, the output BFD is used as a template for the new BFD, when it needs to be the input BFD passed into the function when not dealing with a BFD plugin. On most targets this is not an issue as the input and output formats are the same anyway, but on MinGW targets, there are two variant formats used (pe-i386/pe-x86-64 and pei-i386/pei-x86-64) which are similar but not interchangeable here. PR ld/18199 * plugin.c (plugin_get_ir_dummy_bfd): Use srctemplate as the template when calling bfd_create if it does not use the BFD plugin target vector.
2015-12-07ld: relax alignment requirements of compressed .debug_* section checksJan Beulich3-2/+7
This fixes a failure of the gabinormal linking test on some distros (where e.g. crt1.o has a .debug_aranges section with larger alignment).
2015-12-04Optimize R_386_GOT32/R_386_GOT32X only if addend is 0H.J. Lu13-0/+169
Linker can't optimize R_386_GOT32 and R_386_GOT32X relocations if addend isn't 0. It isn't valid to convert movl foo@GOT+1(%ecx), %eax to leal foo@GOTOFF+1(%ecx), %eax nor to convert movq foo@GOTPCREL+1(%rip), %rax to leaq foo(%rip), %rax for x86-64. We should check if addend is 0 before optimizing R_386_GOT32 and R_386_GOT32X relocations. Testcases are added for i386 and x86-64. bfd/ * elf32-i386.c (elf_i386_convert_load): Skip if addend isn't 0. (elf_i386_relocate_section): Skip R_386_GOT32X optimization if addend isn't 0. ld/testsuite/ * ld-i386/i386.exp: Run mov2a, mov2b and mov3. * ld-i386/mov2.s: New file. * ld-i386/mov2a.d: Likewise. * ld-i386/mov2b.d: Likewise. * ld-i386/mov3.d: Likewise. * ld-i386/mov3.s: Likewise. * ld-x86-64/mov2.s: Likewise. * ld-x86-64/mov2a.d: Likewise. * ld-x86-64/mov2b.d: Likewise. * ld-x86-64/mov2c.d: Likewise. * ld-x86-64/mov2d.d: Likewise. * ld-x86-64/x86-64.exp: Run mov2a, mov2b, mov2c and mov2d.
2015-12-02Make --enable-initfini-array the defaultAlan Modra3-54/+17
* configure.ac (--enable-initfini-array): Remove run test. Default to "yes". Change help string to --disable-initfini-array. * configure: Regenerate.
2015-12-01Properly check symbol defined by assignment in linker scriptH.J. Lu9-0/+96
Symbol defined by a linker assignment may have type bfd_link_hash_new or bfd_link_hash_undefined. And h->def_regular is always set. elf_i386_convert_load and elf_x86_64_convert_load should check h->def_regular as well as bfd_link_hash_undefined and bfd_link_hash_new to see if a symbol is defined by a linker script. bfd/ PR ld/19319 * elf32-i386.c (elf_i386_convert_load): Check h->def_regular instead of bfd_link_hash_new. * elf64-x86-64.c (elf_x86_64_convert_load): Likewise. Skip relocation overflow for bfd_link_hash_undefined and bfd_link_hash_new if h->def_regular is set. ld/testsuite/ PR ld/19319 * ld-i386/i386.exp: Run pr19319 test. * ld-x86-64/x86-64.exp: Likewise. * ld-i386/pr19319.dd: New file. * ld-i386/pr19319a.S: Likewise. * ld-i386/pr19319b.S: Likewise. * ld-x86-64/pr19319.dd: Likewise. * ld-x86-64/pr19319a.S: Likewise. * ld-x86-64/pr19319b.S: Likewise.
2015-11-20MIPS/LD: Fix little-endian `mti' and `img' ELF emulationsMaciej W. Rozycki2-1/+7
Make the little-endian emulation the default for the `mips*el-mti-elf*' and `mips*el-img-elf*' targets, fixing the issue of LD rejecting, in its default configuration, object files produced by GAS also in its default configuration. ld/ * configure.tgt <mips*el-mti-elf*, mips*el-img-elf*>: Add targets.
2015-11-19Account for .tbss alignment when adjusting start of relroAlan Modra2-5/+16
Another option might be to not bump "dot" for .tbss alignment in the main section sizing loop, but that could leak some of the following section into the TLS segment. Leakage shouldn't matter since it will be to bytes past the end of .tdata, but for now this is a safer option. PR ld/19264 * ldlang.c (lang_size_sections): Don't ignore .tbss when adjusting start of relro region.
2015-11-16Fixes an invalid warning about memory region overflow on the ARM.Nick Clifton2-0/+21
PR ld/19106 * emultempl/armelf.em (_set_symbols): New function. Enables relaxation for non-relocatable links. (LDEMUL_SET_SYMBOLS): Define.
2015-11-14Bump version to 2.26.51Tristan Gingold2-10/+14
bfd/ 2015-11-13 Tristan Gingold <gingold@adacore.com> * version.m4: Bump version to 2.26.51 * configure: Regenerate. binutils/ 2015-11-13 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gas/ 2015-11-13 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gprof/ 2015-11-13 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. ld/ 2015-11-13 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. opcodes/ 2015-11-13 Tristan Gingold <gingold@adacore.com> * configure: Regenerate.
2015-11-13Add markers for release 2.26Tristan Gingold2-0/+7
binutils/ 2015-11-13 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.26. gas/ 2015-11-13 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.26. ld/ 2015-11-13 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.26.
2015-11-12Revert "[LD][AARCH64]Add TLSIE relaxation support under large memory model."Marcus Shawcroft4-40/+0
This reverts commit 3ebe65c0ff9f8f76c9971b1cc078273298f0c693. Reverted due to PR19188
2015-11-11Add assembler, disassembler and linker support for power9.Peter Bergner4-0/+40
include/opcode/ * ppc.h (PPC_OPCODE_POWER9): New define. (PPC_OPCODE_VSX3): Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries. Add PPC_OPCODE_VSX3 to the vsx entry. (powerpc_init_dialect): Set default dialect to power9. * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1, extract_l1 insert_xtq6, extract_xtq6): New static functions. (insert_esync): Test for illegal L operand value. (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6, XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA, XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK, XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3, PPCVSX3): New defines. (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu, fcmpo, ftdiv, ftsqrt>: Use XBF_MASK. <mcrxr>: Use XBFRARB_MASK. <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq., bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc., cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first, cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx, lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll, lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw, modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last, rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx, stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx, subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh, vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh., vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd, vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d, vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx, vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq, vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd, vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait, xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp, xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp, xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz, xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp, xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp, xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo, xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo, xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo, xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp, xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp, xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp, xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw, xxinsertw, xxperm, xxpermr, xxspltib>: New instructions. <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9. <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands. include/elf/ * ppc.h (R_PPC_REL16DX_HA): New reloction. * ppc64.h (R_PPC64_REL16DX_HA): Likewise. bfd/ * elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA. (ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA. (ppc_elf_addr16_ha_reloc): Likewise. (ppc_elf_check_relocs): Likewise. (ppc_elf_relocate_section): Likewise. (is_insn_dq_form): Handle lxv and stxv instructions. * elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA. (ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA. (ppc64_elf_ha_reloc): Likewise. (ppc64_elf_check_relocs): Likewise. (ppc64_elf_relocate_section): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. * reloc.c (BFD_RELOC_PPC_REL16DX_HA): New. elfcpp/ * powerpc.h (R_POWERPC_REL16DX_HA): Define. gas/ * doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * config/tc-ppc.c (md_show_usage): Likewise. (md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA. (md_apply_fix): Likewise. (ppc_handle_align): Handle power9's group ending nop. gas/testsuite/ * gas/ppc/altivec3.s: New test. * gas/ppc/altivec3.d: Likewise. * gas/ppc/vsx3.s: Likewise. * gas/ppc/vsx3.d: Likewise. * gas/ppc/power9.s: Likewise. * gas/ppc/power9.d: Likewise. * gas/ppc/ppc.exp: Run them. * gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests. * gas/ppc/power8.d: Likewise. * gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ... <lxvd2x, stxvd2x>: ...to this. * gas/ppc/vsx.d: Likewise. gold/ * gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function. (Powerpc_relocate_functions::addr16dx_ha): Likewise. (Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA. (Target_powerpc::Scan::global): Likewise. (Target_powerpc::Relocate::relocate): Likewise. ld/testsuite/ * ld-powerpc/addpcis.d: New test. * ld-powerpc/addpcis.s: New test. * ld-powerpc/powerpc.exp: Run it.
2015-11-05Regenerate ld/Makefile.inAlan Modra2-0/+6
* Makefile.in: Regenerate.
2015-11-05DATA_SEGMENT_ALIGN documentation is not consistent with behaviourAlan Modra2-1/+7
PR ld/19203 * ld.texinfo (DATA_SEGMENT_ALIGN): Correct second expression.
2015-11-03[LD][AARCH64]Add test cases for big-endian.Renlin Li24-0/+316
ld/testsuite 2015-11-03 Renlin Li <renlin.li@arm.com> * ld-aarch64/aarch64-elf.exp: Run newly added test cases. * ld-aarch64/emit-relocs-301.d: Skip aarch64_be. * ld-aarch64/emit-relocs-302.d: Likwise. * ld-aarch64/emit-relocs-310.d: Likwise. * ld-aarch64/emit-relocs-515.d: Likwise. * ld-aarch64/emit-relocs-516.d: Likwise. * ld-aarch64/tls-large-desc.d: Likwise. * ld-aarch64/tls-large-ie.d: Likwise. * ld-aarch64/tls-relax-large-desc-ie.d: Likwise. * ld-aarch64/tls-relax-large-desc-le.d: Likwise. * ld-aarch64/tls-relax-large-gd-ie.d: Likwise. * ld-aarch64/tls-relax-large-gd-le.d: Likwise. * ld-aarch64/emit-relocs-301-be.d: New for aarch64_be. * ld-aarch64/emit-relocs-302-be.d: Likewise. * ld-aarch64/emit-relocs-310-be.d: Likewise. * ld-aarch64/emit-relocs-515-be.d: Likewise. * ld-aarch64/emit-relocs-516-be.d: Likewise. * ld-aarch64/tls-large-desc-be.d: Likewise. * ld-aarch64/tls-large-ie-be.d: Likewise. * ld-aarch64/tls-relax-large-desc-ie-be.d: Likewise. * ld-aarch64/tls-relax-large-desc-le-be.d: Likewise. * ld-aarch64/tls-relax-large-gd-ie-be.d: Likewise. * ld-aarch64/tls-relax-large-gd-le-be.d: Likewise.
2015-10-30Updated (simplified) Chinese translations for ld, bfd, binutils and gold.Nick Clifton2-3/+7
* po/zh_CN.po: Updated (simplified) Chinese translation.
2015-10-29Also check GOTPCRELXH.J. Lu2-1/+5
* ld-x86-64/plt-main3.rd: Also check GOTPCRELX.
2015-10-292015-10-29 Catherine Moore <clm@codesourcery.com>Catherine Moore6-3/+124
bfd/ * elfxx-mips.c (mips_elf_check_mips16_stubs): Set a stub's output section to bfd_abs_section_ptr if the stub is discarded. ld/testsuite/ * ld-mips-elf/mips16-fp-stub-1.s: New. * ld-mips-elf/mips16-fp-stub-2.s: New. * ld-mips-elf/mips16-fp-stub.d: New. * ld-mips-elf/mips-elf.exp: Run new tests. * ld-mips-elf/mips16-intermix.d: Update expected output. https://sourceware.org/ml/binutils/2015-10/msg00137.html
2015-10-29Add support for AArch64 CloudABI binaries.Ed Schouten6-0/+71
ld * Makefile.am (ALL_64_EMULATION_SOURCES): Add support for CloudABI on aarch64. For this target we have to make sure we use ELFOSABI_CLOUDABI instead of ELFOSABI_NONE. * configure.tgt (targ_emul): Likewise. * emulparams/aarch64cloudabi.sh: New file. * emulparams/aarch64cloudabib.sh: New file. * Makefile.in: Regenerate. bfd * config.bfd (targ_defvec): Add support for CloudABI on aarch64. For this target we have to make sure we use ELFOSABI_CLOUDABI instead of ELFOSABI_NONE. * configure.ac (tb): Likewise. * elfnn-aarch64.c: Likewise. * targets.c (_bfd_target_vector): Likewise. * configure: Regenerate. gas * config/tc-aarch64.c (elf64_aarch64_target_format): Select the cloudabi format if the TARGET_OS is cloudabi.
2015-10-29Fix reporting of command line options that need an argument, but which occur ↵Nick Clifton2-4/+32
as the last option on the command line. PR ld/19146 * lexsup.c (parse_args): Correct error message for an option that is missing its argument if that option is the last one on the command line.
2015-10-29Re: Orphan output section with multiple input sectionsAlan Modra7-18/+76
The last patch missed handling the case where the ideal place to put an orphan was after a non-existent output section statement, as can happen when not using the builtin linker scripts. This patch uses the updated flags for that case too, and extends the support to mmo and pe. PR ld/19162 * emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Pass updated flags to lang_output_section_find_by_flags. * emultempl/mmo.em (mmo_place_orphan): Merge flags for any other input sections that might match a new output section to decide placement. * emultempl/pe.em (gld_${EMULATION_NAME}_place_orphan): Likewise. * emultempl/pep.em (gld_${EMULATION_NAME}_place_orphan): Likewise. * ldlang.c (lang_output_section_find_by_flags): Add sec_flags param. * ldlang.h (lang_output_section_find_by_flags): Update prototype.
2015-10-29fix typo in ld's texinfoMatthias Klose2-1/+5
* ld.texinfo (Options <-rpath>): Fix typo.
2015-10-28Add a test for PR ld/19162H.J. Lu5-0/+23
PR ld/19162 * ld-x86-64/x86-64.exp: Run pr19162. * ld-x86-64/pr19162.d: New file. * ld-x86-64/pr19162a.s: Likewise. * ld-x86-64/pr19162b.s: Likewise.
2015-10-28Orphan output section with multiple input sectionsAlan Modra2-14/+37
If given input sections with differing flags, we'd like to place the section according to the final output section flags. bfd/ PR ld/19162 * elflink.c (_bfd_elf_gc_mark_reloc): Move code iterating over linker input bfds.. * section.c (bfd_get_next_section_by_name): ..to here. Add ibfd param. (bfd_get_linker_section): Adjust bfd_get_next_section_by_name call. * tekhex.c (first_phase): Likewise. * elflink.c (bfd_elf_gc_sections): Likewise. * bfd-in2.h: Regenerate. ld/ PR ld/19162 * emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Check flags before calling _bfd_elf_match_sections_by_type. Merge flags for any other input sections that might match a new output section to decide placement.
2015-10-27Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time ↵Laurent Alfonsi18-2/+996
workaround for a bug in the bus matrix / memory controller for some of the STM32 Cortex-M4 based products (STM32L4xx). bfd * bfd-in2.h: Regenerate. * bfd-in.h (bfd_arm_stm32l4xx_fix): New enum. Specify how STM32L4XX instruction scanning should be done. (bfd_elf32_arm_set_stm32l4xx_fix) (bfd_elf32_arm_stm32l4xx_erratum_scan) (bfd_elf32_arm_stm32l4xx_fix_veneer_locations): Add prototypes. (bfd_elf32_arm_set_target_relocs): Add stm32l4xx fix type argument to prototype. * elf32-arm.c (STM32L4XX_ERRATUM_VENEER_SECTION_NAME) (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME): Define macros. (elf32_stm32l4xx_erratum_type): New enum. (elf32_stm32l4xx_erratum_list): New struct. List of veneers or jumps to veneers. (_arm_elf_section_data): Add stm32l4xx_erratumcount, stm32l4xx_erratumlist. (elf32_arm_link_hash_table): Add stm32l4xx_erratum_glue_size, stm32l4xx_fix and num_stm32l4xx_fixes fields. (ctz): New function. (popcount): New function. (elf32_arm_link_hash_table_create): Initialize stm32l4xx_fix. (put_thumb2_insn): New function. (STM32L4XX_ERRATUM_LDM_VENEER_SIZE): Define. Size of a veneer for LDM instructions. (STM32L4XX_ERRATUM_VLDM_VENEER_SIZE): Define. Size of a veneer for VLDM instructions. (bfd_elf32_arm_allocate_interworking_sections): Initialise erratum glue section. (record_stm32l4xx_erratum_veneer) : New function. Create a single veneer, and its associated symbols. (bfd_elf32_arm_add_glue_sections_to_bfd): Add STM32L4XX erratum glue. (bfd_elf32_arm_set_stm32l4xx_fix): New function. Set the type of erratum workaround required. (bfd_elf32_arm_stm32l4xx_fix_veneer_locations): New function. Find out where veneers and branches to veneers have been placed in virtual memory after layout. (is_thumb2_ldmia): New function. (is_thumb2_ldmdb): Likewise. (is_thumb2_vldm ): Likewise. (stm32l4xx_need_create_replacing_stub): New function. Decide if a veneer must be emitted. (bfd_elf32_arm_stm32l4xx_erratum_scan): Scan the sections of an input BFD for potential erratum-triggering insns. Record results. (bfd_elf32_arm_set_target_relocs): Set stm32l4xx_fix field in global hash table. (elf32_arm_size_dynamic_sections): Collect glue information. (create_instruction_branch_absolute): New function. (create_instruction_ldmia): Likewise. (create_instruction_ldmdb): Likewise. (create_instruction_mov): Likewise. (create_instruction_sub): Likewise. (create_instruction_vldmia): Likewise. (create_instruction_vldmdb): Likewise. (create_instruction_udf_w): Likewise. (create_instruction_udf): Likewise. (push_thumb2_insn32): Likewise. (push_thumb2_insn16): Likewise. (stm32l4xx_fill_stub_udf): Likewise. (stm32l4xx_create_replacing_stub_ldmia): New function. Expands the replacing stub for ldmia instructions. (stm32l4xx_create_replacing_stub_ldmdb): Likewise for ldmdb. (stm32l4xx_create_replacing_stub_vldm): Likewise for vldm. (stm32l4xx_create_replacing_stub): New function. Dispatches the stub emission to the appropriate functions. (elf32_arm_write_section): Output veneers, and branches to veneers. ld * ld.texinfo: Description of the STM32L4xx erratum workaround. * emultempl/armelf.em (stm32l4xx_fix): New. (arm_elf_before_allocation): Choose the type of fix, scan for erratum. (gld${EMULATION_NAME}_finish): Fix veneer locations. (arm_elf_create_output_section_statements): Propagate stm32l4xx_fix value. (PARSE_AND_LIST_PROLOGUE): Define OPTION_STM32L4XX_FIX. (PARSE_AND_LIST_LONGOPTS): Add entry for handling --fix-stm32l4xx-629360. (PARSE_AND_LIST_OPTION): Add entry for helping on --fix-stm32l4xx-629360. (PARSE_AND_LIST_ARGS_CASES): Treat OPTION_STM32L4XX_FIX. tests * ld-arm/arm-elf.exp (armelftests_common): Add STM32L4XX tests. * ld-arm/stm32l4xx-cannot-fix-far-ldm.d: New. * ld-arm/stm32l4xx-cannot-fix-far-ldm.s: Likewise. * ld-arm/stm32l4xx-cannot-fix-it-block.d: Likewise. * ld-arm/stm32l4xx-cannot-fix-it-block.s: Likewise. * ld-arm/stm32l4xx-fix-all.d: Likewise. * ld-arm/stm32l4xx-fix-all.s: Likewise. * ld-arm/stm32l4xx-fix-it-block.d: Likewise. * ld-arm/stm32l4xx-fix-it-block.s: Likewise. * ld-arm/stm32l4xx-fix-ldm.d: Likewise. * ld-arm/stm32l4xx-fix-ldm.s: Likewise. * ld-arm/stm32l4xx-fix-vldm.d: Likewise. * ld-arm/stm32l4xx-fix-vldm.s: Likewise.
2015-10-27xfail pr19161 test on hppa-linuxAlan Modra2-1/+6
HPPA linux needs libgcc.a for millicode routine $$dyncall. * ld-gc/pr19161.d: xfail hppa-*-*.
2015-10-27Evaluate __start_* and __stop_* symbol PROVIDE expressions earlyAlan Modra3-9/+32
Makes these symbols defined before bfd_elf_size_dynamic_sections, to avoid horrible hacks elsewhere. The exp_fold_tree undefweak change is necessary to define undefweak symbols early too. The comment was wrong. PROVIDE in fact defines undefweak symbols, via bfd_elf_record_link_assignment. PR ld/19175 * ldlang.c (lang_insert_orphan): Evaluate __start_* and __stop_* symbol PROVIDE expressions. * ldexp.c (exp_fold_tree_1 <etree_provide>): Define undefweak references.
2015-10-26Check symbol defined by assignment in linker scriptH.J. Lu9-0/+72
Symbol symbol defined by an assignment in a linker script has type bfd_link_hash_new. elf_i386_convert_load and elf_x86_64_convert_load should check bfd_link_hash_new to see if a symbol is defined by a linker script. bfd/ PR ld/19175 * elf32-i386.c (elf_i386_convert_load): Check bfd_link_hash_new instead of calling bfd_link_get_defined_symbol. * elf64-x86-64.c (elf_x86_64_convert_load): Likewise. Skip relocation overflow for bfd_link_hash_new. * linker.c (bfd_link_get_defined_symbol): Removed. * bfd-in2.h: Regenerated. ld/testsuite/ PR ld/19175 * ld-i386/i386.exp: Run pr19175. * ld-x86-64/x86-64.exp: Likewise. * ld-i386/pr19175.d: New file. * ld-i386/pr19175.s: Likewise. * ld-i386/pr19175.t: Likewise. * ld-x86-64/pr19175.d: Likewise. * ld-x86-64/pr19175.s: Likewise. * ld-x86-64/pr19175.t: Likewise.
2015-10-26Properly convert address load of __start_XXX/__stop_XXXH.J. Lu20-0/+70
Since __start_XXX and __stop_XXX symbols aren't defined when address load is being converted, we need to check if there is an XXX output section to get their section and value. This patch adds a new function, bfd_link_get_defined_symbol, to search for the XXX output section to check if __start_XXX and __stop_XXX symbols are defined. bfd/ PR ld/19171 * elf32-i386.c (elf_i386_convert_load): Call bfd_link_get_defined_symbol to check if a symbol is defined. * elf64-x86-64.c (elf_x86_64_convert_load): Call bfd_link_get_defined_symbol to get defined symbol section and value. * linker.c (bfd_link_get_defined_symbol): New function. * bfd-in2.h: Regenerated. ld/testsuite/ PR ld/19171 * ld-i386/lea1.s: Add tests for address load of __start_XXX and __stop_XXX. * ld-i386/mov1.s: Likewise. * ld-x86-64/lea1.s: Likewise. * ld-x86-64/mov1.s: Likewise. * ld-i386/lea1a.d: Updated. * ld-i386/lea1b.d: Likewise. * ld-i386/lea1c.d: Likewise. * ld-i386/mov1a.d: Likewise. * ld-i386/mov1b.d: Likewise. * ld-x86-64/lea1a.d: Likewise. * ld-x86-64/lea1b.d: Likewise. * ld-x86-64/lea1c.d: Likewise. * ld-x86-64/lea1d.d: Likewise. * ld-x86-64/lea1e.d: Likewise. * ld-x86-64/lea1f.d: Likewise. * ld-x86-64/mov1a.d: Likewise. * ld-x86-64/mov1b.d: Likewise. * ld-x86-64/mov1c.d: Likewise. * ld-x86-64/mov1d.d: Likewise.
2015-10-23Add a test for PR ld/19167H.J. Lu5-0/+28
PR ld/19167 * ld-gc/gc.exp: Run pr19167 test. * ld-gc/pr19167.d: New file. * ld-gc/pr19167a.s: Likewise. * ld-gc/pr19167b.s: Likewise.
2015-10-22Always keep sections marked with SEC_KEEPH.J. Lu5-0/+49
SEC_KEEP check in elf_gc_sweep was missing in commit: commit bde6f3eb6dff94cea1d471e15c6154d55d49820f Author: H.J. Lu <hjl.tools@gmail.com> Date: Fri Jan 8 01:43:23 2010 +0000 Set SEC_KEEP on section XXX for undefined __start_XXX/__stop_XXX bfd/ 2010-01-07 H.J. Lu <hongjiu.lu@intel.com> PR ld/11133 * elflink.c (_bfd_elf_gc_mark_hook): Check section XXX for undefined __start_XXX/__stop_XXX in all input files and set SEC_KEEP. This patch adds SEC_KEEP check to elf_gc_sweep. bfd/ PR ld/19161 * elflink.c (elf_gc_sweep): Always keep sections marked with SEC_KEEP. ld/testsuite/ PR ld/19161 * ld-gc/gc.exp: Run pr19161 test. * ld-gc/pr19161-1.c: New file. * ld-gc/pr19161-2.c: Likewise. * ld-gc/pr19161.d: Likewise.
2015-10-22Properly check --enable-compressed-debug-sections={yes,all}H.J. Lu3-2/+8
gas/ * configure.ac: Properly check --enable-compressed-debug-sections={yes,all}. * configure: Regenerated. ld/ * configure.ac: Properly check --enable-compressed-debug-sections={yes,all}. * configure: Regenerated.
2015-10-22Allow mmix-knuth-mmixware adjustments to objcopy --extract-symbols test.Hans-Peter Nilsson2-1/+22
* ld-scripts/script.exp (extract_symbol_test): Allow nm output of objcopy --extract-symbols result to differ from original on mmix-knuth-mmixware.
2015-10-22Handle --enable-compressed-debug-sections=ld,gasH.J. Lu3-12/+18
gas/ PR gas/19109 * configure.ac: Handle --enable-compressed-debug-sections=*,gas,*. * configure: Regenerated. ld/ PR gas/19109 * configure.ac: Handle --enable-compressed-debug-sections=*,ld,*. * configure: Regenerated.
2015-10-22Add "-z call-nop=PADDING" option to ldH.J. Lu46-0/+658
The ld linker can transform indirect call to a locally defined function, foo, via its GOT slot, to either "NOP call foo" or "call foo NOP" where NOP is a 1-byte NOP padding. This patch adds a "-z call-nop=PADDING" option to x86 ld to control 1-byte NOP padding for x86 call instruction. PADDING is one of prefix-addr, prefix-nop, suffix-nop, prefix-NUMBER or suffix-NUMBER. bfd/ * elf32-i386.c (elf_i386_convert_load): Use call_nop_byte and check call_nop_as_suffix for 1-byte NOP padding to pad call. * elf64-x86-64.c (elf_x86_64_convert_load): Likewise. include/ * bfdlink.h (bfd_link_info): Add call_nop_as_suffix and call_nop_byte. ld/ * ld/ld.texinfo: Document "-z call-nop=PADDING" option. * emulparams/call_nop.sh: New file. * emulparams/elf_i386_be.sh: Source ${srcdir}/emulparams/call_nop.sh. * emulparams/elf_i386_chaos.sh: Likewise. * emulparams/elf_i386_ldso.sh: Likewise. * emulparams/elf_i386_vxworks.sh: Likewise. * emulparams/elf_iamcu.sh: Likewise. * emulparams/elf_k1om.sh: Likewise. * emulparams/elf_l1om.sh: Likewise. * emulparams/elf_x86_64.sh: Likewise. * emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set link_info.call_nop_byte if $CALL_NOP_BYTE isn't empty. ld/testsuite/ * ld-i386/call3.s: New file. * ld-i386/call3a.d: Likewise. * ld-i386/call3b.d: Likewise. * ld-i386/call3c.d: Likewise. * ld-i386/call3d.d: Likewise. * ld-i386/call3e.d: Likewise. * ld-i386/call3f.d: Likewise. * ld-i386/call3g.d: Likewise. * ld-i386/call3h.d: Likewise. * ld-i386/load1-nacl.d: Likewise. * ld-x86-64/call1.s: Likewise. * ld-x86-64/call1a.d: Likewise. * ld-x86-64/call1b.d: Likewise. * ld-x86-64/call1c.d: Likewise. * ld-x86-64/call1d.d: Likewise. * ld-x86-64/call1e.d: Likewise. * ld-x86-64/call1f.d: Likewise. * ld-x86-64/call1g.d: Likewise. * ld-x86-64/call1h.d: Likewise. * ld-x86-64/call1i.d: Likewise. * ld-x86-64/load1a-nacl.d: Likewise. * ld-x86-64/load1b-nacl.d: Likewise. * ld-x86-64/load1c-nacl.d: Likewise. * ld-x86-64/load1d-nacl.d: Likewise.
2015-10-22Add R_X86_64_[REX_]GOTPCRELX support to gas and ldH.J. Lu17-4/+390
This patch adds support for the R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX relocations proposed in https://groups.google.com/forum/#!topic/x86-64-abi/n9AWHogmVY0 to gas and ld. It updates gas to generate R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX if there is a REX prefix, relocation for memory operand, foo@GOTPCREL(%rip). With the locally defined symbol, foo, we convert mov foo@GOTPCREL(%rip), %reg to lea foo(%rip), %reg and convert call/jmp *foo@GOTPCREL(%rip) to nop call foo/jmp foo nop When PIC is false, convert test %reg, foo@GOTPCREL(%rip) to test $foo, %reg and convert binop foo@GOTPCREL(%rip), %reg to binop $foo, %reg where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions. bfd/ * elf64-x86-64.c: Include opcode/i386.h. (x86_64_elf_howto_table): Add R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. (R_X86_64_standard): Replace R_X86_64_PLT32_BND with R_X86_64_REX_GOTPCRELX. (x86_64_reloc_map): Add BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. (need_convert_mov_to_lea): Renamed to ... (need_convert_load): This. (elf_x86_64_check_relocs): Handle R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. Replace need_convert_mov_to_lea with need_convert_load. (elf_x86_64_gc_sweep_hook): Handle R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. (elf_x86_64_size_dynamic_sections): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_convert_mov_to_lea): Renamed to ... (elf_x86_64_convert_load): This. Replace need_convert_mov_to_lea with need_convert_load. Support R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX transformations. * reloc.c (BFD_RELOC_X86_64_GOTPCRELX): New. (BFD_RELOC_X86_64_REX_GOTPCRELX): Likewise. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. (tc_gen_reloc): Likewise. (i386_validate_fix): Generate BFD_RELOC_X86_64_GOTPCRELX or BFD_RELOC_X86_64_REX_GOTPCRELX if fx_tcbit2 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Also return true for BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. gas/testsuite/ * gas/i386/i386.exp: Run x86-64-gotpcrel. * gas/i386/x86-64-gotpcrel.d: New file. * gas/i386/x86-64-gotpcrel.s: Likewise. * gas/i386/ilp32/x86-64-gotpcrel.d: Likewise. * gas/i386/x86-64-localpic.d: Replace R_X86_64_GOTPCREL with R_X86_64_REX_GOTPCRELX. * gas/i386/ilp32/x86-64-localpic.d: Likewise. include/elf/ * x86-64.h (R_X86_64_GOTPCRELX): New. (R_X86_64_REX_GOTPCRELX): Likewise. ld/testsuite/ * ld-ifunc/ifunc-5r-local-x86-64.d: Replace R_X86_64_GOTPCREL with R_X86_64_REX_GOTPCRELX. * ld-x86-64/plt-main1.rd: Likewise. * ld-x86-64/plt-main3.rd: Likewise. * ld-x86-64/plt-main4.rd: Likewise. * ld-x86-64/gotpcrel1.dd: New file. * ld-x86-64/gotpcrel1.out: Likewise. * ld-x86-64/gotpcrel1a.S: Likewise. * ld-x86-64/gotpcrel1b.c: Likewise. * ld-x86-64/gotpcrel1c.c: Likewise. * ld-x86-64/gotpcrel1d.S: Likewise. * ld-x86-64/load1.s: Likewise. * ld-x86-64/load1a.d: Likewise. * ld-x86-64/load1b.d: Likewise. * ld-x86-64/load1c.d: Likewise. * ld-x86-64/load1d.d: Likewise. * ld-x86-64/x86-64.exp: Run load1a, load1b, load1c and load1d tests. Run gotpcrel1 test.
2015-10-22Add R_386_GOT32X support to gas and ldH.J. Lu36-5/+519
This patch adds support for the R_386_GOT32X relocation proposed in https://groups.google.com/forum/#!topic/ia32-abi/GbJJskkid4I to gas and ld. It updates gas to generate R_386_GOT32X relocation for memory operand, foo@GOT[(%reg)]. We must encode "mov foo@GOT, %eax" with the 0x8b opcode, instead of the 0xb8 opcode, so that it can be transformed to "lea foo, %eax". With the locally defined symbol, foo, we convert mov foo@GOT[(%reg1)], %reg2 to lea foo[@GOTOFF(%reg1)], %reg2 and convert call/jmp *foo@GOT[(%reg)] to nop call foo/jmp foo nop When PIC is false, convert test %reg1, foo@GOT[(%reg2)] to test $foo, %reg1 and convert binop foo@GOT[(%reg1)], %reg2 to binop $foo, %reg2 where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions. bfd/ * elf32-i386.c: Include opcode/i386.h. (elf_howto_table): Add R_386_GOT32X. (R_386_ext2): Replace R_386_IRELATIVE with R_386_GOT32X. (elf_i386_reloc_type_lookup): Handle BFD_RELOC_386_GOT32X. (need_convert_mov_to_lea): Renamed to ... (need_convert_load): This. (elf_i386_check_relocs): Handle R_386_GOT32X. Replace need_convert_mov_to_lea with need_convert_load. (elf_i386_gc_sweep_hook): Handle R_386_GOT32X. (elf_i386_size_dynamic_sections): Likewise. (elf_i386_relocate_section): Likewise. (elf_i386_convert_mov_to_lea): Renamed to ... (elf_i386_convert_load): This. Replace need_convert_mov_to_lea with need_convert_load. Support R_386_GOT32X transformations. * reloc.c (BFD_RELOC_386_GOT32X): New. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_386_GOT32X. (tc_gen_reloc): Likewise. (match_template): Force 0x8b encoding for "mov foo@GOT, %eax". (output_disp): Check for "call/jmp *mem", "mov mem, %reg", "test %reg, mem" and "binop mem, %reg" where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions. Set fx_tcbit if the REX prefix is generated. Set fx_tcbit2 if BFD_RELOC_386_GOT32X should be generated. (i386_validate_fix): Generate BFD_RELOC_386_GOT32X if fx_tcbit2 is set. gas/testsuite/ * gas/i386/got.d: New file. * gas/i386/got.s: Likewise. * gas/i386/i386.exp: Run got. * gas/i386/localpic.d: Replace R_386_GOT32 with R_386_GOT32X. * gas/i386/mixed-mode-reloc32.d: Likewise. * gas/i386/reloc32.d: Likewise. include/elf/ * i386.h (R_386_GOT32X): New relocation. ld/testsuite/ * ld-i386/branch1.d: New file. * ld-i386/branch1.s: Likewise. * ld-i386/call1.d: Likewise. * ld-i386/call1.s: Likewise. * ld-i386/call2.d: Likewise. * ld-i386/call2.s: Likewise. * ld-i386/got1.dd: Likewise. * ld-i386/got1.out: Likewise. * ld-i386/got1a.S: Likewise. * ld-i386/got1b.c: Likewise. * ld-i386/got1c.c: Likewise. * ld-i386/got1d.S: Likewise. * ld-i386/jmp1.d: Likewise. * ld-i386/jmp1.s: Likewise. * ld-i386/jmp2.d: Likewise. * ld-i386/jmp2.s: Likewise. * ld-i386/load1.d: Likewise. * ld-i386/load1.s: Likewise. * ld-i386/load2.d: Likewise. * ld-i386/load2.s: Likewise. * ld-i386/load3.d: Likewise. * ld-i386/load3.s: Likewise. * ld-i386/load4.s: Likewise. * ld-i386/load4a.d: Likewise. * ld-i386/load4b.d: Likewise. * ld-i386/load5.s: Likewise. * ld-i386/load5a.d: Likewise. * ld-i386/load5b.d: Likewise. * ld-i386/load6.d: Likewise. * ld-i386/load6.s: Likewise. * ld-i386/i386.exp: Run branch1, call1, call2, jmp1, jmp2, load1, load2, load3, load4a, load4b, load5a, load5b and load6 tests. Run got1 test.
2015-10-22S/390: ifunc: Enable the ifunc tests.Andreas Krebbel2-2/+7
ld/testsuite/ChangeLog: * ld-ifunc/ifunc.exp: Run ifunc tests on s390* targets.
2015-10-21Extend description of the --enable-compressed-debug-sections configure ↵Nick Clifton3-3/+4
option in gas and ld.
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