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AgeCommit message (Expand)AuthorFilesLines
2016-07-20Add support to the ARC disassembler for selecting instruction classes.Claudiu Zissulescu2-0/+5
2016-07-15Add support for creating ELF import librariesThomas Preud'homme2-0/+11
2016-07-15Pass SIGLIBRT directly to child processes.John Baldwin2-1/+7
2016-07-14[ARC] Fix/improve small data support.Claudiu Zissulescu2-1/+5
2016-07-11Fixes done to TLS.Cupertino Miranda1-1/+1
2016-07-05[ARM] Change noread to purecode.Andre Vieria2-1/+6
2016-07-01[AArch64] Fix +nofp16 handlingSzabolcs Nagy2-4/+14
2016-06-30[ARM][GAS] ARMv8.2 should enable ARMv8.1 NEON instructions.Matthew Wahab2-1/+6
2016-06-29sparc: make SPARC_OPCODE_ARCH_MAX part of its enumTrevor Saunders2-2/+6
2016-06-28[AArch64] Make register indices be full 64-bit valuesRichard Sandiford2-3/+7
2016-06-28MIPS16: Add R_MIPS16_PC16_S1 branch relocation supportMaciej W. Rozycki2-1/+6
2016-06-25xtensa: prototype xtensa_make_property_section in elf/xtensa.hTrevor Saunders2-0/+6
2016-06-24Add constants for FreeBSD-specific auxiliary vector entry types.John Baldwin2-0/+17
2016-06-23[ARC] Misc minor edits/fixesGraham Markall2-3/+7
2016-06-22addmore extern CTrevor Saunders4-0/+30
2016-06-22tilegx: move TILEGX_NUM_PIPELINE_ENCODINGS to tilegx_pipeline enumTrevor Saunders2-3/+6
2016-06-21Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall3-2/+9
2016-06-17bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine nu...Jose E. Marchesi2-0/+13
2016-06-14Change the size field of MSP430_Opcode_Decoded to a plain integer.John Baldwin2-8/+6
2016-06-14[ARC] Add deep packet inspection instructions for npsGraham Markall1-0/+1
2016-06-11sparc-coff writing uninitialized memoryAlan Modra2-0/+12
2016-06-09sparc: add missing comment about hyperprivileged register operandsJose E. Marchesi2-0/+7
2016-06-07PowerPC VLEAlan Modra2-0/+20
2016-06-07[ARM] Add command line option for RAS extension.Matthew Wahab2-3/+10
2016-06-02Add support for 48 and 64 bit ARC instructions.Andrew Burgess2-1/+32
2016-06-01add more extern CTrevor Saunders11-0/+91
2016-05-28Return void from linker callbacksAlan Modra2-15/+19
2016-05-26metag: add extern C to headerTrevor Saunders2-0/+12
2016-05-23[ARC] Update instruction type and delay slot info.Claudiu Zissulescu2-1/+10
2016-05-23[ARC] Rename "class" named attributes.Claudiu Zissulescu2-2/+8
2016-05-23tic54x: rename typedef of struct symbol_Trevor Saunders2-4/+9
2016-05-17Add DW_LANG_RustTom Tromey2-1/+10
2016-05-11Add MIPS32 DSPr3 support.Matthew Fortune3-1/+9
2016-05-10Use getters/setters to access ARM branch typeThomas Preud'homme2-3/+34
2016-05-10Add support for ARMv8-M Mainline with DSP extensionThomas Preud'homme2-0/+5
2016-05-10Allow extension availability to depend on several architecture bitsThomas Preud'homme2-0/+10
2016-05-10Add support for ARMv8-M security extensions instructionsThomas Preud'homme2-1/+11
2016-05-04[ARC] Add SYNTAX_NOP and SYNTAX_1OP for extension instructionsClaudiu Zissulescu2-2/+18
2016-04-28Add support to AArch64 disassembler for verifying instructions. Add verifier...Nick Clifton2-0/+8
2016-04-27Cache result of scan for __start_* and __stop_* sectionsAlan Modra2-6/+20
2016-04-21Add support for non-ELF targets to check their relocs.Nick Clifton2-0/+9
2016-04-20Check ELF relocs after opening all input filesH.J. Lu2-0/+8
2016-04-20arc: Fix relocation formula for ARC_NPS_CMEM16 relocationAndrew Burgess2-1/+5
2016-04-19opcodes/arc: Add yet more nps instructionsAndrew Burgess2-1/+5
2016-04-19opcodes/arc: Add more nps instructionsAndrew Burgess2-0/+6
2016-04-14arc/nps400 : New cmem instructions and associated relocationAndrew Burgess3-0/+15
2016-04-12Add support for .extCondCode, .extCoreRegister and .extAuxRegister.Claudiu Zissulescu2-3/+32
2016-04-12Add support for .extInstruction pseudo-op.Claudiu Zissulescu2-24/+90
2016-04-05[ARC] Fix support for double assist instructions.Claudiu Zissulescu2-3/+16
2016-04-05[ARC] 24 bit reloc and overflow detection fix.Claudiu Zissulescu2-1/+21
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