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2023-06-15Add MIPS Allegrex CPU as a MIPS2-based CPUDavid Guillen Fandos2-0/+7
2023-06-15Revert "MIPS: add MT ASE support for micromips32"Maciej W. Rozycki1-25/+10
2023-06-15Revert "MIPS: sync oprand char usage between mips and micromips"Maciej W. Rozycki1-12/+2
2023-06-09ecoff find_nearest_line and final link leaksAlan Modra1-1/+4
2023-06-06libsframe: fix cosmetic issues and typosIndu Bhagat1-1/+1
2023-06-05MIPS: sync oprand char usage between mips and micromipsYunQiang Su1-2/+12
2023-06-05MIPS: add MT ASE support for micromips32YunQiang Su1-10/+25
2023-06-01libsframe: avoid using magic numberIndu Bhagat1-1/+4
2023-06-01RISC-V: PR30449, Add lga assembler macro support.Jim Wilson1-0/+1
2023-05-30LoongArch: include: Add support for linker relaxation.mengqinggang2-0/+23
2023-05-30Define IMAGE_FILE_MACHINE_ARMNTAlan Modra1-0/+1
2023-05-30Delete include/aout/encap.hAlan Modra1-135/+0
2023-05-26Remove duplicate definitionAndreas Schwab2-2/+6
2023-05-22Re: readelf: Support SHT_RELR/DT_RELR for -rAlan Modra1-1/+4
2023-05-19RISC-V: Support subtraction of .uleb128.Kuan-Lin Chen1-0/+3
2023-05-17PR29961, plugin-api.h: "Could not detect architecture endianess"Alan Modra1-22/+23
2023-05-17gcc-4.5 build fixesAlan Modra1-2/+0
2023-05-11Add LDPT_REGISTER_CLAIM_FILE_HOOK_V2 linker plugin hook [GCC PR109128]Joseph Myers1-0/+16
2023-04-28Re: Keeping track of rs6000-coff archive element pointersAlan Modra1-5/+5
2023-04-26 RISC-V: Support XVentanaCondOps extensionPhilipp Tomsich2-0/+9
2023-04-21Keeping track of rs6000-coff archive element pointersAlan Modra1-22/+34
2023-04-19sframe: correct some typosIndu Bhagat1-2/+2
2023-03-30aarch64: Remove stray reglist variableRichard Sandiford1-1/+1
2023-03-30aarch64: Add the RPRFM instructionRichard Sandiford1-0/+2
2023-03-30aarch64: Add new SVE dot-product instructionsRichard Sandiford1-1/+2
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford1-0/+3
2023-03-30aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford1-0/+1
2023-03-30aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford1-0/+5
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford1-0/+4
2023-03-30aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford1-0/+2
2023-03-30aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford1-0/+1
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford1-0/+3
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford1-0/+11
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford1-0/+11
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford1-0/+3
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford1-0/+10
2023-03-30aarch64: Add support for predicate-as-counter registersRichard Sandiford1-0/+5
2023-03-30aarch64; Add support for vector offset rangesRichard Sandiford1-4/+19
2023-03-30aarch64: Add support for vgx2 and vgx4Richard Sandiford1-0/+13
2023-03-30aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford1-3/+3
2023-03-30aarch64: Add +sme2Richard Sandiford1-0/+1
2023-03-30aarch64: Add support for strided register listsRichard Sandiford1-12/+26
2023-03-30aarch64: Add a aarch64_cpu_supports_inst_p helperRichard Sandiford1-0/+3
2023-03-30aarch64: Add an operand class for SVE register listsRichard Sandiford1-0/+1
2023-03-30aarch64: Add an error code for out-of-range registersRichard Sandiford1-1/+9
2023-03-30aarch64: Deprioritise AARCH64_OPDE_REG_LISTRichard Sandiford1-5/+9
2023-03-30aarch64: Update operand_mismatch_kind_namesRichard Sandiford1-1/+4
2023-03-30aarch64: Move ZA range checks to aarch64-opc.cRichard Sandiford1-0/+1
2023-03-30aarch64: Make indexed_za use 64-bit immediatesRichard Sandiford1-1/+1
2023-03-30aarch64: Rename za_tile_vector to za_indexRichard Sandiford1-10/+13
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