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AgeCommit message (Expand)AuthorFilesLines
2016-07-05[ARM] Change noread to purecode.Andre Vieria1-0/+5
2016-07-01[AArch64] Fix +nofp16 handlingSzabolcs Nagy1-0/+7
2016-06-30[ARM][GAS] ARMv8.2 should enable ARMv8.1 NEON instructions.Matthew Wahab1-0/+5
2016-06-29sparc: make SPARC_OPCODE_ARCH_MAX part of its enumTrevor Saunders1-0/+5
2016-06-28[AArch64] Make register indices be full 64-bit valuesRichard Sandiford1-0/+4
2016-06-28MIPS16: Add R_MIPS16_PC16_S1 branch relocation supportMaciej W. Rozycki1-0/+4
2016-06-25xtensa: prototype xtensa_make_property_section in elf/xtensa.hTrevor Saunders1-0/+4
2016-06-24Add constants for FreeBSD-specific auxiliary vector entry types.John Baldwin1-0/+7
2016-06-23[ARC] Misc minor edits/fixesGraham Markall1-0/+4
2016-06-22addmore extern CTrevor Saunders1-0/+6
2016-06-22tilegx: move TILEGX_NUM_PIPELINE_ENCODINGS to tilegx_pipeline enumTrevor Saunders1-0/+5
2016-06-21Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall1-0/+7
2016-06-17bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine nu...Jose E. Marchesi1-0/+7
2016-06-14Change the size field of MSP430_Opcode_Decoded to a plain integer.John Baldwin1-0/+5
2016-06-11sparc-coff writing uninitialized memoryAlan Modra1-0/+4
2016-06-09sparc: add missing comment about hyperprivileged register operandsJose E. Marchesi1-0/+5
2016-06-07PowerPC VLEAlan Modra1-0/+7
2016-06-07[ARM] Add command line option for RAS extension.Matthew Wahab1-0/+6
2016-06-02Add support for 48 and 64 bit ARC instructions.Andrew Burgess1-0/+7
2016-06-01add more extern CTrevor Saunders1-0/+13
2016-05-28Return void from linker callbacksAlan Modra1-0/+7
2016-05-26metag: add extern C to headerTrevor Saunders1-0/+4
2016-05-23[ARC] Update instruction type and delay slot info.Claudiu Zissulescu1-0/+5
2016-05-23[ARC] Rename "class" named attributes.Claudiu Zissulescu1-0/+6
2016-05-23tic54x: rename typedef of struct symbol_Trevor Saunders1-0/+5
2016-05-17Add DW_LANG_RustTom Tromey1-0/+5
2016-05-11Add MIPS32 DSPr3 support.Matthew Fortune1-0/+6
2016-05-10Use getters/setters to access ARM branch typeThomas Preud'homme1-0/+12
2016-05-10Add support for ARMv8-M Mainline with DSP extensionThomas Preud'homme1-0/+4
2016-05-10Allow extension availability to depend on several architecture bitsThomas Preud'homme1-0/+4
2016-05-10Add support for ARMv8-M security extensions instructionsThomas Preud'homme1-0/+7
2016-05-04[ARC] Add SYNTAX_NOP and SYNTAX_1OP for extension instructionsClaudiu Zissulescu1-0/+8
2016-04-28Add support to AArch64 disassembler for verifying instructions. Add verifier...Nick Clifton1-0/+5
2016-04-27Cache result of scan for __start_* and __stop_* sectionsAlan Modra1-0/+5
2016-04-21Add support for non-ELF targets to check their relocs.Nick Clifton1-0/+4
2016-04-20Check ELF relocs after opening all input filesH.J. Lu1-0/+4
2016-04-20arc: Fix relocation formula for ARC_NPS_CMEM16 relocationAndrew Burgess1-0/+4
2016-04-19opcodes/arc: Add yet more nps instructionsAndrew Burgess1-0/+4
2016-04-19opcodes/arc: Add more nps instructionsAndrew Burgess1-0/+4
2016-04-14arc/nps400 : New cmem instructions and associated relocationAndrew Burgess1-0/+5
2016-04-12Add support for .extCondCode, .extCoreRegister and .extAuxRegister.Claudiu Zissulescu1-0/+11
2016-04-12Add support for .extInstruction pseudo-op.Claudiu Zissulescu1-23/+40
2016-04-05[ARC] Fix support for double assist instructions.Claudiu Zissulescu1-1/+7
2016-04-05[ARC] 24 bit reloc and overflow detection fix.Claudiu Zissulescu1-0/+5
2016-03-29[ARC] Add support for Quarkse opcodes.Claudiu Zissulescu1-0/+17
2016-03-22make more variables constTrevor Saunders1-0/+5
2016-03-21arc/nps400: Add first nps400 instructionsAndrew Burgess1-0/+4
2016-03-21arc/opcodes: Use flag operand class to handle multiple flag matchesAndrew Burgess1-0/+5
2016-03-21arc: Add nps400 machine type, and assembler flag.Andrew Burgess1-0/+5
2016-03-21arc: Remove EF_ARC_CPU_GENERIC constant.Andrew Burgess1-0/+4
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