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2020-03-06Stop the assembler from complaining that the input and output files are the ↵Nick Clifton2-1/+13
same, if neither of them are regular files. PR 25572 * as.c (main): Allow matching input and outputs when they are not regular files.
2020-03-06x86: reduce amount of various VCVT* templatesJan Beulich2-5/+23
Presumably as a result of various changes over the last several months, and - for some of them - with a generalization of logic in match_mem_size() plus mirroring of this generalization into the broadcast handling logic of check_VecOperands(), various register-only templates can be foled into their respective memory forms. This in particular then also allows dropping a few more instances of IgnoreSize.
2020-03-06x86: drop/replace IgnoreSizeJan Beulich2-5/+16
Even after commit dc2be329b950 ("i386: Only check suffix in instruction mnemonic"), by which many of its uses have become unnecessary (some were unnecessary even before), IgnoreSize is still used for various slightly different purposes: - to suppress emission of an operand size prefix, - in Intel syntax mode to zap "derived" suffixes in certain cases and to skip certain checks of remaining "derived" suffixes, - to suppress ambiguous operand size / missing suffix diagnostics, - for prefixes to suppress the "stand-alone ... prefix" warning. Drop entirely unnecessary ones and where possible also replace instances by the more focused (because of having just a single purpose) NoRex64. To further restrict when IgnoreSize is needed, also generalize the logic when to skip a template because of a present or derived L or Q suffix, by skipping immediate operands. Additionally consider mask registers and VecSIB there. Note that for the time being the attribute needs to be kept in place on MMX/SSE/etc insns (but not on VEX/EVEX encoded ones unless an operand template of them allows for only non-SIMD-register actuals) allowing for Dword operands - the logic when to emit a data size prefix would need further adjustment first. Note also that the memory forms of {,v}pinsrw get their permission for an L or Q suffix dropped. I can only assume that it being this way was a cut-and-paste mistake from the register forms, as the latter specifically have NoRex64 set, and the {,v}pextrw counterparts don't allow these suffixes either. Convert VexW= again to their respective VexW* on lines touched anyway.
2020-03-06x86: fold (supposed to be) identical codeJan Beulich2-27/+20
The Q and L suffix exclusion checks in match_template() ought to be (kept) in sync as far as their FPU and SIMD aspects go. This was already violated by only the Q one checking for active broadcast. Convert the code such that there'll be only one instance of the logic, the more that subsequently the logic is liable to need further refinement / extension. (The alternative would be to drop all SIMD-ness from the L part, but it is in principle possible to enable all sorts of SIMD support with just a pre-386 CPU, via suitable .arch directives.)
2020-03-06x86: replace NoRex64 on VEX-encoded insnsJan Beulich8-50/+64
When the template specifies any of the possible VexW settings, we can use this instead of a separate NoRex64 to suppress the setting of REX_W. Note that this ends up addressing an inconsistency between VEX- and EVEX-encoded VEXTRACTPS, VPEXTR{B,W}, and VPINSR{B,W} - while the former avoided setting VEX.W, the latter pointlessly set EVEX.W when there is a 64-bit GPR operand. Adjust the testcase to cover both cases. Convert VexW= to their respective VexW* on lines touched anyway.
2020-03-06x86: drop Rex64 attributeJan Beulich2-3/+10
It is almost entirely redundant with Size64, and the sole case (CRC32) where direct replacement isn't possible can easily be taken care of in another way.
2020-03-06x86: correct MPX insn w/o base or index encoding in 16-bit modeJan Beulich5-0/+182
Since 16-bit addressing isn't allowed, Disp32 needs to be forced; Disp16 fails to match the templates. The SDM leaves open whether BNDC[LNU] with a GPR operand require an operand size override; this aspect is therefore left untouched here.
2020-03-06x86: add missing IgnoreSizeJan Beulich31-22/+274
For proper code generation in 16-bit mode (or to avoid the "same type of prefix used twice" diagnostic there), IgnoreSize is needed on certain templates allowing for just 32-(and maybe 64-)bit operands. Beyond adding tests for the previously broken cases, also add ones for the previously working cases where IgnoreSize is needed for the same reason (leaving out MPX for now, as that'll require an assembler change first). Some minor adjustments to tests get done such that re-use of the same code for 16-bit code generation testing becomes easier.
2020-03-06x86: refine TPAUSE and UMWAITJan Beulich8-16/+70
Allowing 64-bit registers is misleading here: Elsewhere these get allowed when there's no difference between either variant, because of 32-bit destination registers having their upper halves zeroed in 64-bit mode. Here, however, they're source registers, and hence specifying 64-bit registers would lead to the ambiguity of whether the upper 32 bits actually matter. Additionally, for proper code generation in 16-bit mode, IgnoreSize is needed on both. And finally, just like for e.g. MONITOR/MWAIT, add variants with all input registers explicitly specified.
2020-03-04RISC-V: Support assembler modifier %got_pcrel_hi.Nelson Chu7-7/+45
gas/ * config/tc-riscv.c: Support the modifier %got_pcrel_hi. * doc/c-riscv.texi: Add documentation. * testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new modifier %got_pcrel_hi. * testsuite/gas/riscv/no-relax-reloc.s: Likewise. * testsuite/gas/riscv/relax-reloc.d: Likewise. * testsuite/gas/riscv/relax-reloc.s: Likewise.
2020-03-04RISC-V: Add description for RISC-V Modifiers to as doc.Nelson Chu2-1/+117
gas/ * doc/c-riscv.texi (relocation modifiers): Add documentation. (RISC-V-Formats): Update the section name from "Instruction Formats" to "RISC-V Instruction Formats".
2020-03-04Generate a warning in the ARM assembler if a PC-relative thumb load ↵Alexandre Oliva7-6/+24
instruction is detected in a section with insufficient alignment. * config/tc-arm.c (md_apply_fix): Warn if a PC-relative load is detected in a section which does not have at least 4 byte alignment. * testsuite/gas/arm/armv8-ar-it-bad.s: Add alignment directive. * testsuite/gas/arm/ldr-t.s: Likewise. * testsuite/gas/arm/sp-pc-usage-t.s: Likewise. * testsuite/gas/arm/sp-pc-usage-t.d: Finish test at end of disassembly, ignoring any NOPs that may have been inserted because of section alignment. * testsuite/gas/arm/ldr-t.d: Likewise.
2020-03-04x86: support VMGEXITJan Beulich7-4/+21
It has been publicly documented for quite some time, albeit not in the "General-Purpose and System Instructions" volume: https://www.amd.com/system/files/TechDocs/24593.pdf.
2020-03-03x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu2-13/+21
Since an instruction template can't have both IgnoreSize and DefaultSize, this patch replaces IgnoreSize and DefaultSize with MnemonicSize. gas/ * config/tc-i386.c (match_template): Replace ignoresize and defaultsize with mnemonicsize. (process_suffix): Likewise. opcodes/ * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize with MnemonicSize. * i386-opc.h (IGNORESIZE): New. (DEFAULTSIZE): Likewise. (IgnoreSize): Removed. (DefaultSize): Likewise. (MnemonicSize): New. (i386_opcode_modifier): Replace ignoresize/defaultsize with mnemonicsize. * i386-opc.tbl (IgnoreSize): New. (DefaultSize): Likewise. * i386-tbl.h: Regenerated.
2020-03-03The patch fixed invalid compilation of instruction LD IY,(HL) and ↵Sergey Belyashov6-4/+54
disassemble of this and LD (HL),IX instruction. Also it update testsuit. PR 25627 opcodes * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX instructions. gas * config/tc-z80.c (emit_ld_rr_m): Fix invalid compilation of instruction LD IY,(HL). * testsuite/gas/z80/ez80_adl_all.d: Update expected disassembly. * testsuite/gas/z80/ez80_adl_all.s: Add tests of the instruction. * testsuite/gas/z80/ez80_z80_all.d: Update expected disassembly. * testsuite/gas/z80/ez80_z80_all.s: Add tests of the instruction.
2020-03-03x86: Allow integer conversion without suffix in AT&T syntaxH.J. Lu8-24/+61
According to gas manual, suffix in instruction mnemonics isn't always required: When there is no sizing suffix and no (suitable) register operands to deduce the size of memory operands, with a few exceptions and where long operand size is possible in the first place, operand size will default to long in 32- and 64-bit modes. This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they must be allowed without suffix in AT&T syntax. gas/ PR gas/25622 * testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and x86-64-default-suffix-avx. * testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries. * testsuite/gas/i386/noreg64.d: Updated. * testsuite/gas/i386/noreg64.l: Likewise. * testsuite/gas/i386/x86-64-default-suffix-avx.d: New file. * testsuite/gas/i386/x86-64-default-suffix.d: Likewise. * testsuite/gas/i386/x86-64-default-suffix.s: Likewise. opcodes/ PR gas/25622 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax. * i386-tbl.h: Regenerated.
2020-03-03x86: Improve -malign-branchHongtao Liu7-32/+378
According to intel SDM manual, not all compare flag-modifying instructions are marcro-fusible with subsequent jcc instructions. For those non-fusible instructions, -malign-branch doesn't need to align them, only jcc itself needs to be aligned. Here are 2 restrictions which separate macro-fusible instruction from not Restriction 1: If TEST/AND/CMP/ADD/SUB/INC/DEC is one of the following format: cmp m, imm add m, imm sub m, imm test m, imm and m, imm inc m dec m it is unfusible with any jcc instruction. Restriction 2: /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture Note it also works for Skylake and Cascadelake. --------------------------------------------------------------------- | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | ------ | ----------- | ------- | -------- | | Jo | N | N | Y | | Jno | N | N | Y | | Jc/Jb | Y | N | Y | | Jae/Jnb | Y | N | Y | | Je/Jz | Y | Y | Y | | Jne/Jnz | Y | Y | Y | | Jna/Jbe | Y | N | Y | | Ja/Jnbe | Y | N | Y | | Js | N | N | Y | | Jns | N | N | Y | | Jp/Jpe | N | N | Y | | Jnp/Jpo | N | N | Y | | Jl/Jnge | Y | Y | Y | | Jge/Jnl | Y | Y | Y | | Jle/Jng | Y | Y | Y | | Jg/Jnle | Y | Y | Y | Update maybe_fused_with_jcc_p to check if operands of CMP like instructions can be fused with condition jump. * gas/config/tc-i386.h (i386_tc_frag_data): Add member mf_type. (TC_FRAG_INIT): Init mf_type. * gas/config/tc-i386.c (enum mf_jcc_kind): New enum. (enum mf_cmp_kind): Ditto. (maybe_fused_with_jcc_p): Add argument mf_cmp_p to get mf_type of corresponding instructons, exclude unfusible instructions. (add_fused_jcc_padding_frag_p): Likewise. (add_branch_padding_frag_p): Likewise. (output_insn): Record mf_type for corresponding instructions. (i386_macro_fusible_p): New function. (i386_next_fusible_jcc_frag): Rename from i386_next_jcc_frag, add argument cmp_fragP to return next fusible jcc frag only. (i386_classify_machine_dependant_frag): Seperate macro-fusible instructions from condition jump. * gas/testsuite/gas/i386/align-branch-9.s: New file. * gas/testsuite/gas/i386/align-branch-9.d: Ditto. * gas/testsuite/gas/i386/x86-64-align-branch-9.s: Ditto. * gas/testsuite/gas/i386/x86-64-align-branch-9.d: Ditto. * gas/testsuite/gas/i386/i386.exp: Run new tests.
2020-03-03Fix a potential illegal memory access in the Z80 assembler.Sergey Belyashov2-8/+30
PR 25604 * config/tc-z80.c (contains_register): Prevent an illegal memory access when checking an expression for a register name.
2020-03-03Tidy obj-coff.hAlan Modra2-14/+5
* config/obj-coff.h: Remove vestiges of coff-m68k and pe-mips support.
2020-03-02miscellaneous SEC_SMALL_DATAAlan Modra6-56/+34
This patch arranges for symbols defined in .sdata and .sbss to be reported by nm with 'g' and 's' flags, for coff targets that support .sdata and .sbss. The assembler changes regarding SEC_SMALL_DATA are really just documentation. As far as I'm aware, this won't change any assembler output. bfd/ * coff-alpha.c (alpha_ecoff_le_vec): Add SEC_SMALL_DATA to applicable section flags. * coff-mips.c (mips_ecoff_le_vec, mips_ecoff_be_vec): Likewise. (mips_ecoff_bele_vec): Likewise. * coffcode.h (sec_to_styp_flags): Set SEC_SMALL_DATA for .sdata and .sbss sections. * ecoff.c (_bfd_ecoff_new_section_hook): Likewise. (_bfd_ecoff_styp_to_sec_flags): Likewise. gas/ * config/tc-m32r.c (md_begin): Set SEC_SMALL_DATA on .scommon section. * config/tc-mips.c (s_change_sec): Set SEC_SMALL_DATA for .sdata and .sbss sections. * config/tc-score.c: Delete !BFD_ASSEMBLER code throughout. (s3_s_change_sec): Set SEC_SMALL_DATA for .sbss section. (s3_s_score_lcomm): Likewise. * config/tc-score7.c: Similarly. * read.c (bss_alloc): Set SEC_SMALL_DATA for .sbss section.
2020-02-28MIPS/fix_loongson3_llsc: fix when target has multi labelsYunQiang Su2-5/+51
When there is multi-labels on the same insn, the current code will take care about the last one. it may cause that no sync is added at the target. Here we scan all labels with same value of S_GET_VALUE(label_list->label) by label_list->next. 2020-02-28 YunQiang Su <syq@debian.org> PR gas/25539 * config/tc-mips.c (fix_loongson3_llsc): Compare label value to handle multi-labels. (has_label_name): New.
2020-02-26[binutils][arm] Arm CDE CX*A instructions allow condition codeMatthew Malcomson5-46/+50
The implementation of the Arm CDE CX*A instructions doesn't allow a condition code on the instructions but does allow the instruction in an ITBlock. The specification has been recently updated, though this is yet to be published. The instructions now should allow a suffix, and should behave in the standard way around ITBlocks. This patch removes the custom pred_instruction_type and handling for these instructions, and uses the standard INSIDE_IT_INSN predication type to describe the new instructions. gas/ChangeLog: 2020-02-26 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (enum pred_instruction_type): Remove NEUTRAL_IT_NO_VPT_INSN predication type. (cxn_handle_predication): Modify to require condition suffixes. (handle_pred_state): Remove NEUTRAL_IT_NO_VPT_INSN cases. * testsuite/gas/arm/cde-scalar.s: Update test. * testsuite/gas/arm/cde-warnings.l: Update test. * testsuite/gas/arm/cde-warnings.s: Update test.
2020-02-26gas gettext warningAlan Modra2-1/+6
gettext("") returns the header entry with meta information, not the empty string. * config/tc-arm.c (reg_expected_msgs[REG_TYPE_RNB]): Don't use N_() on empty string.
2020-02-26gas strncpy warningAlan Modra2-1/+7
Avoid a warning that the buffer may not be zero terminated. * read.c (read_a_source_file): Call strncpy with length one less than size of original_case_string.
2020-02-26Indent labelsAlan Modra22-63/+87
Labels don't go in the first column according to standard emacs C indent rules, and I got annoyed enough at seeing diff -p show a label rather than the function name to fix this. bfd/ * aoutx.h: Indent labels correctly. Format error strings. * archive.c: Likewise. * archive64.c: Likewise. * coff-arm.c: Likewise. * coff-rs6000.c: Likewise. * coff-stgo32.c: Likewise. * cpu-arm.c: Likewise. * dwarf2.c: Likewise. * elf-ifunc.c: Likewise. * elf-properties.c: Likewise. * elf-s390-common.c: Likewise. * elf-strtab.c: Likewise. * elf.c: Likewise. * elf32-arm.c: Likewise. * elf32-bfin.c: Likewise. * elf32-cr16.c: Likewise. * elf32-csky.c: Likewise. * elf32-i386.c: Likewise. * elf32-m68k.c: Likewise. * elf32-msp430.c: Likewise. * elf32-nds32.c: Likewise. * elf32-nios2.c: Likewise. * elf32-pru.c: Likewise. * elf32-xtensa.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-x86-64.c: Likewise. * elfcode.h: Likewise. * elfcore.h: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * elfnn-riscv.c: Likewise. * elfxx-mips.c: Likewise. * elfxx-sparc.c: Likewise. * elfxx-x86.c: Likewise. * i386lynx.c: Likewise. * merge.c: Likewise. * pdp11.c: Likewise. * plugin.c: Likewise. * reloc.c: Likewise. binutils/ * elfedit.c: Indent labels correctly. * readelf.c: Likewise. * resres.c: Likewise. gas/ * config/obj-elf.c: Indent labels correctly. * config/obj-macho.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-frv.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-nds32.c: Likewise. * config/tc-riscv.c: Likewise. * config/tc-s12z.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * read.c: Likewise. * symbols.c: Likewise. * write.c: Likewise. ld/ * emultempl/cskyelf.em: Indent labels correctly. * ldfile.c: Likewise. * ldlang.c: Likewise. * plugin.c: Likewise. opcodes/ * aarch64-asm.c: Indent labels correctly. * aarch64-dis.c: Likewise. * aarch64-gen.c: Likewise. * aarch64-opc.c: Likewise. * alpha-dis.c: Likewise. * i386-dis.c: Likewise. * nds32-asm.c: Likewise. * nfp-dis.c: Likewise. * visium-dis.c: Likewise.
2020-02-20RISC-V: Support the read-only CSR checking.Nelson Chu8-0/+543
CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of CSR address is 0x3. The read-only CSR can not be written by the CSR instructions. gas/ * config/tc-riscv.c (riscv_ip): New boolean insn_with_csr to indicate we are assembling instruction with CSR. Call riscv_csr_read_only_check after parsing all arguments. (enum csr_insn_type): New enum is used to classify the CSR instruction. (riscv_csr_insn_type, riscv_csr_read_only_check): New functions. These are used to check if we write a read-only CSR by the CSR instruction. * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: New testcase. Test all CSR for the read-only CSR checking. * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-02.s: New testcase. Test all CSR instructions for the read-only CSR checking. * testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
2020-02-20RISC-V: Disable the CSR checking by default.Nelson Chu5-3/+50
Add new .option `csr-check/no-csr-check` and GAS option `-mcsr-check /-mno-csr-check` to enbale/disable the CSR checking. Disable the CSR checking by default. gas/ * config/tc-riscv.c: Add new .option and GAS options to enbale/disable the CSR checking. We disable the CSR checking by default. (reg_lookup_internal): Check the `riscv_opts.csr_check` before we doing the CSR checking. * doc/c-riscv.texi: Add description for the new .option and assembler options. * testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable the CSR checking. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu8-9/+198
According to the riscv privilege spec, some CSR are only valid when rv32 or the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS to record more informaton we need, and then check whether the CSR is valid according to these information. We report warning message when the CSR is invalid, so we have a choice between error and warning by --fatal-warnings option. Also, a --no-warn/-W option is used to turn the warnings off, if people don't want the warnings. gas/ * config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide whether or not this CSR is legal in the current ISA string. (struct riscv_csr_extra): New structure to hold all extra information of CSR. (riscv_init_csr_hash): New function. According to the DECLARE_CSR and DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash. Call hash_reg_name to insert CSR address into reg_names_hash. (md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR. (reg_csr_lookup_internal, riscv_csr_class_check): New functions. Decide whether the CSR is valid according to the csr_extra_hash. (init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is not a boolean. This is same as riscv_init_csr_hash, so keep the consistent usage. * testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option. * testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option. * testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the f-ext CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv64if, so the rv32-only CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. include/ * opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to record riscv_csr_class. opcodes/ * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed. gdb/ * riscv-tdep.c: Updated since the DECLARE_CSR is changed. * riscv-tdep.h: Likewise. * features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without rv32-only CSR. * features/riscv/64bit-csr.xml: Regernated. binutils/ * dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-21pdp11 reloc processingAlan Modra2-13/+22
This allows pdp11 to handle 32-bit fixups that can be applied by gas, and improves the error message emitted when the required reloc isn't available. * config/tc-pdp11.c (md_apply_fix): Handle BFD_RELOC_32. (tc_gen_reloc): Only give a BAD_CASE assertion on pcrel relocs.
2020-02-21PR25569, PDP11 ld -s clobbers last data byteAlan Modra2-20/+35
This patch fixes an ancient wart in aout support, in that text and data section sizes are rounded up for alignment rather that just the corresponding header sizes. Changing section sizes could conceivably result in buffer overflows if section contents were held in memory. Also, keeping the original section sizes allows this PR to be fixed nicely. bfd/ PR 25569 * aoutx.h (adjust_o_magic, adjust_z_magic, adjust_n_magic): Use "text", "data" and "bss" section pointer vars. Don't update section size, just exec header sizes. (adjust_sizes_and_vmas): Don't update text section size. Set initial exec header a_text. Print exec headers sizes. * pdp11.c (adjust_o_magic, adjust_z_magic, adjust_n_magic), (adjust_sizes_and_vmas): Similarly. Formatting. (final_link): Correct final file extension. gas/ PR 25569 * config/obj-aout.c (obj_aout_frob_file_before_fix): Don't loop on section size adjustment, instead perform another write if exec header size is larger than section size.
2020-02-19RISC-V: Add description for -march-attr/-mno-arch-attr options in gas doc.Nelson Chu2-0/+19
gas/ * doc/c-riscv.texi: Add the doc entries for -march-attr/ -mno-arch-attr command line options.
2020-02-19RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.Jim Wilson3-0/+19
2020-02-19 Nelson Chu <nelson.chu@sifive.com> gas/ * testsuite/gas/riscv/c-add-addi.d: New testcase. * testsuite/gas/riscv/c-add-addi.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed c.mv/c.li if rs1 is zero. Change-Id: Id939b5e6db80d267a832545f3ffef7b9ba881f7d
2020-02-19Various fixes for the Z80 support.Sergey Belyashov25-229/+209
PR 25537 ld * emultempl/z80.em: Remove machine compatability checking. PR 25517 * testsuite/ld-z80/arch_ez80_adl.d: Update command line. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80n.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z80_ez80.d: Likewise. * testsuite/ld-z80/comb_arch_z80_z180.d: Likewise. * testsuite/ld-z80/comb_arch_z80_z80n.d: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_ez80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80n.d: Likewise. bfd * cpu-z80.c: Add machine type compatibility checking. gas * config/tc-z80.c (md_parse_option): Do not use an underscore prefix for local labels in SDCC compatability mode. (z80_start_line_hook): Remove SDCC dollar label support. * testsuite/gas/z80/sdcc.d: Update expected disassembly. * testsuite/gas/z80/sdcc.s: Likewise. * config/tc-z80.c: Add -march option. * doc/as.texi: Update Z80 documentation. * doc/c-z80.texi: Likewise. * testsuite/gas/z80/ez80_adl_all.d: Update command line. * testsuite/gas/z80/ez80_adl_suf.d: Likewise. * testsuite/gas/z80/ez80_pref_dis.d: Likewise. * testsuite/gas/z80/ez80_z80_all.d: Likewise. * testsuite/gas/z80/ez80_z80_suf.d: Likewise. * testsuite/gas/z80/gbz80_all.d: Likewise. * testsuite/gas/z80/r800_extra.d: Likewise. * testsuite/gas/z80/r800_ii8.d: Likewise. * testsuite/gas/z80/r800_z80_doc.d: Likewise. * testsuite/gas/z80/sdcc.d: Likewise. * testsuite/gas/z80/z180.d: Likewise. * testsuite/gas/z80/z180_z80_doc.d: Likewise. * testsuite/gas/z80/z80_doc.d: Likewise. * testsuite/gas/z80/z80_ii8.d: Likewise. * testsuite/gas/z80/z80_in_f_c.d: Likewise. * testsuite/gas/z80/z80_op_ii_ld.d: Likewise. * testsuite/gas/z80/z80_out_c_0.d: Likewise. * testsuite/gas/z80/z80_sli.d: Likewise. * testsuite/gas/z80/z80n_all.d: Likewise. * testsuite/gas/z80/z80n_reloc.d: Likewise.
2020-02-19x86: Mark cvtpi2ps and cvtpi2pd as MMXH.J. Lu6-1/+36
* config/tc-i386.c (output_insn): Mark cvtpi2ps and cvtpi2pd with GNU_PROPERTY_X86_FEATURE_2_MMX. * testsuite/gas/i386/i386.exp: Run property-3 and x86-64-property-3. * testsuite/gas/i386/property-3.d: New file. * testsuite/gas/i386/property-3.s: Likewise. * testsuite/gas/i386/x86-64-property-3.d: Likewise.
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu3-5/+14
AMD ABM has 2 instructions: popcnt and lzcnt. ABM CPUID feature bit has been reused for lzcnt and a POPCNT CPUID feature bit is added for popcnt which used to be the part of SSE4.2. This patch removes CpuABM and adds CpuPOPCNT. It changes ABM to enable both lzcnt and popcnt, changes SSE4.2 to also enable popcnt. gas/ * config/tc-i386.c (cpu_arch): Add .popcnt. * doc/c-i386.texi: Remove abm and .abm. Add popcnt and .popcnt. Add a tab before @samp{.sse4a}. opcodes/ * i386-gen.c (cpu_flag_init): Replace CpuABM with CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add CPU_POPCNT_FLAGS. (cpu_flags): Remove CpuABM. Add CpuPOPCNT. * i386-opc.h (CpuABM): Removed. (CpuPOPCNT): New. (i386_cpu_flags): Remove cpuabm. Add cpupopcnt. * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on popcnt. Remove CpuABM from lzcnt. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2020-02-17x86: fold AddrPrefixOpReg templatesJan Beulich2-48/+72
There's no need to have separate Cpu64 and CpuNo64 templates: There already is special logic handling the attribute, and all that's needed is rejecting 16-bit address registers in 64-bit mode. Suppress suffix guessing and group all involved logic together, outside of suffix processing (arguably it doesn't even belong in process_suffix()). Also, since no AddrPrefixOpReg template permits any suffixes, move the No_*Suf specifiers for them to a central place. Along with this drop the no longer relevant NoRex64 from there.
2020-02-17x86/Intel: don't swap operands of MONITOR{,X} and MWAIT{,X}Jan Beulich9-4/+124
Generally, the documentation doesn't allow for any explicit operands to be specified with MONITOR/MWAIT. To permit the more legible overriding of the address size via specifying operands, the option is being retained even in Intel mode, but operand swapping is being suppressed by this patch. This is both because it makes no sense here (all of the operands are inputs) and because, as a result, old gcc (prior to 4.8) actually expects it this way with -mintel-syntax (and hence gets fixed by this change rather than, as claimed by a reply in the bug report, broken).
2020-02-17x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich10-45/+115
Conversions which shrink element size and which have a memory source can't be disambiguated between their 128- and 256-bit variants by looking at the register operand. "operand size mismatch", however, is a pretty misleading diagnostic. Generalize the logic introduced for VFPCLASSP{S,D} such that, with suitable similar adjustments to the respective templates, it'll cover these cases too. For VCVTNEPS2BF16 also fold the two previously separate AVX512VL templates to achieve the intended effect. This is then also accompanied by a respective addition to the inval-avx512f testcase.
2020-02-16x86: Don't disable SSE4a when disabling SSE4H.J. Lu3-2/+13
commit 7deea9aad8 changed nosse4 to include CpuSSE4a. But AMD SSE4a is a superset of SSE3 and Intel SSE4 is a superset of SSSE3. Disable Intel SSE4 shouldn't disable AMD SSE4a. This patch restores nosse4. It also adds .sse4a and nosse4a. gas/ * config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a. Restore nosse4. * doc/c-i386.texi: Document sse4a and nosse4a. opcodes/ * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove CPU_ANY_SSE4_FLAGS.
2020-02-14Remove the old movsx and movzx documentation for AT&T syntaxH.J. Lu2-16/+5
* doc/c-i386.texi: Remove the old movsx and movzx documentation for AT&T syntax.
2020-02-14x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich29-87/+1673
For these to get treatment consistent with other operand size checking the special logic shouldn't live in md_assemble(), but process_suffix(). And there's more logic involved than simply zapping the suffix. Note however that MOVS[BW]* and MOVZ[BW]* still won't be fully consistent, due to the objection to fold MOVS* templates just like was done for MOVZ* in c07315e0c6 ("x86: allow suffix-less movzw and 64-bit movzb"). Note further that it is against my own intentions to have MOVSX/MOVZX silently default to a byte source in AT&T mode. This should happen only when the destination register is a 16-bit one. In all other cases there is an ambiguity, and the user should be warned. But it was explicitly requested for this to be done in a way inconsistent with everything else. Note finally that the assembler change points out (and this patch fixes) a wrong Intel syntax test introduced by bc31405ebb2c ("x86-64: Properly encode and decode movsxd"): When source code specifies a 16-bit destination register, disassembly expectations shouldn't have been to find a 32-bit one.
2020-02-14x86: adjust segment override prefix emissionJan Beulich4-6/+29
Since we already suppress the prefix altogether when it's the default one for the chosen addressing mode, let's do so also when instruction prefix and override specified with the memory operand match. (Note that insn prefix specified segment overrides never get discarded.)
2020-02-14x86: optimize away pointless segment overridesJan Beulich4-3/+31
When optimizing there's no point keeping the segment overrides when we warn about their presence in the first place.
2020-02-14x86: extend LEA's segment override warningJan Beulich6-3/+33
For one both possible forms should be warned about. And then, to guard against future surprises, qualify the original opcode check by excluding VEX/EVEX-like templates.
2020-02-14x86: Document movsx/movsxd/movzx for AT&T syntaxH.J. Lu2-0/+59
Document different mnemonics of movsx, movsxd and movzx in AT&T syntax. PR gas/25438 * doc/c-i386.texi: Document movsx, movsxd and movzx for AT&T syntax.
2020-02-13x86: Resolve PLT32 reloc aganst local symbol to sectionH.J. Lu7-2/+62
Since PLT entry isn't needed for branch to local symbol, we can resolve R_386_PLT32/R_X86_64_PLT32 relocation aganst local symbol to section, similar to R_386_PC32/R_X86_64_PC32. 2020-02-13 Fangrui Song <maskray@google.com> H.J. Lu <hongjiu.lu@intel.com> PR gas/25551 * config/tc-i386.c (tc_i386_fix_adjustable): Don't check BFD_RELOC_386_PLT32 nor BFD_RELOC_X86_64_PLT32. * testsuite/gas/i386/i386.exp: Run relax-5 and x86-64-relax-4. * testsuite/gas/i386/relax-5.d: New file. * testsuite/gas/i386/relax-5.s: Likewise. * testsuite/gas/i386/x86-64-relax-4.d: Likewise. * testsuite/gas/i386/x86-64-relax-4.s: Likewise.
2020-02-13x86: fix SSE4a dependencies of ".arch .nosse*"Jan Beulich2-1/+6
Since ".arch .sse4a" enables SSE3 and earlier, disabling SSE3 should also disable SSE4a. And as per its name, ".arch .nosse4" should also do so.
2020-02-12x86: correct VFPCLASSP{S,D} operand size handlingJan Beulich6-5/+93
With AVX512VL disabled (e.g. when writing code for the Knights family of processors) these insns aren't ambiguous when used with a memory source, and hence should be accepted without suffix or operand size specifier. When AVX512VL is enabled, to be consistent with this as well as other ambiguous operand size handling it would seem better to just warn about the ambiguity in AT&T mode, and still default to 512-bit operands (on the assumption that the code may have been written without AVX512VL in mind yet), but it was requested to leave AT&T syntax mode alone here.
2020-02-12x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich11-3/+88
AMD and Intel differ in their handling of far indirect branches as well as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note how the latter three were hybrids so far, while far branches were fully AMD-like.)
2020-02-12x86: also disallow non-byte/-word registers with byte/word suffixJan Beulich7-71/+62
Along the lines of be4c5e58bd ("x86: Always disallow double word suffix with word general register") also adjust check_{byte,word}_reg(), to make overall behavior consistent again in this regard.
generated by cgit v1.1 at 2025-02-14 16:20:24 +0000