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2021-08-11Fix a typo in the RX asse,bler. The Double-precision floating-point ↵Darius Galis5-4/+11
exception handling control register name is DECNT not DCENT. * config/rx-parse.y (DECNT): Fixed typo. * testsuite/gas/rx/dpopm.sm (DECNT): Fixed typo. * testsuite/gas/rx/dpushm.sm (DECNT): Fixed typo. * testsuite/gas/rx/macros.inc (DECNT): Fixed typo.
2021-08-11Fix an internal error in the CSKY assembler when asked to resolve an ↵Nick Clifton2-1/+8
overlarge constant. PR 28215 * config/tc-csky.c (md_apply_fix): Correctly handle a fixup that involves an overlarge constant.
2021-08-11Deprecate a.out support for NetBSD targets.John Ericson5-1704/+1694
As discussed previously, a.out support is now quite deprecated, and in some cases removed, in both Binutils itself and NetBSD, so this legacy default makes little sense. `netbsdelf*` and `netbsdaout*` still work allowing the user to be explicit about there choice. Additionally, the configure script warns about the change as Nick Clifton requested. One possible concern was the status of NetBSD on NS32K, where only a.out was supported. But per [1] NetBSD has removed support, and if it were to come back, it would be with ELF. The binutils implementation is therefore marked obsolete, per the instructions in the last message. With that patch and this one applied, I have confirmed the following: --target=i686-unknown-netbsd --target=i686-unknown-netbsdelf builds completely --target=i686-unknown-netbsdaout properly fails because target is deprecated. --target=vax-unknown-netbsdaout builds completely except for gas, where the target is deprecated. [1]: https://mail-index.netbsd.org/tech-toolchain/2021/07/19/msg004025.html --- bfd/config.bfd | 43 +++++++++++++-------- bfd/configure.ac | 5 +-- binutils/testsuite/binutils-all/nm.exp | 2 +- binutils/testsuite/lib/binutils-common.exp | 7 +--- config/picflag.m4 | 4 +- gas/configure.tgt | 9 +++-- gas/testsuite/gas/arm/blx-bl-convert.d | 2 +- gas/testsuite/gas/arm/blx-local-thumb.d | 2 +- gas/testsuite/gas/sh/basic.exp | 2 +- gdb/configure.host | 34 +++++++---------- gdb/configure.tgt | 2 +- gdb/testsuite/gdb.asm/asm-source.exp | 6 +-- intl/configure | 2 +- ld/configure.tgt | 44 +++++++++++----------- ld/testsuite/ld-arm/arm-elf.exp | 4 +- ld/testsuite/ld-elf/elf.exp | 2 +- ld/testsuite/ld-elf/shared.exp | 4 +- libiberty/configure | 4 +-
2021-08-11Add a -mno-dollar-line-separator command line option to the AVR assembler.Matt Jacobson4-4/+33
Some frontends, like the gcc Objective-C frontend, emit symbols with $ characters in them. The AVR target code in gas treats $ as a line separator, so the code doesn?t assemble correctly. Provide a machine-specific option to disable treating $ as a line separator. * config/tc-avr.c (enum options): Add option flag. (struct option): Add option -mno-dollar-line-separator. (md_parse_option): Adjust treatment of $ when option is present. * config/tc-avr.h: Use avr_line_separator_chars.
2021-08-11Fix typo in previous deltaNick Clifton2-2/+6
2021-08-11gas: fold IEEE encoding of -Inf with that of +InfJan Beulich1-42/+3
The respective results differ only by the sign bits - there's no need to have basically identical (partially even arch-specific) logic twice. Simply set the sign bit at the end of encoding the various formats.
2021-08-11gas: support NaN flavorsJan Beulich9-18/+221
Like for infinity, there isn't just a single NaN. The sign bit may be of interest and, going beyond infinity, whether the value is quiet or signalling may be even more relevant to be able to encode. Note that an anomaly with x86'es double extended precision NaN values gets taken care of at the same time: For all other formats a positive value with all mantissa bits set was used, while here a negative value with all non-significant mantissa bits clear was chose for an unknown reason. For m68k, since I don't know their X_PRECISION floating point value layout, a warning gets issued if any of the new flavors was attempted to be encoded that way. However likely it may be that, given that the code lives in a source file supposedly implementing IEEE-compliant formats, the bit patterns of the individual words match x86'es, I didn't want to guess so. And my very, very old paper doc doesn't even mention floating point formats other than single and double.
2021-08-11Arm64: leave .bfloat16 processing to common codeJan Beulich1-49/+1
With x86 support having been implemented by extending atof-ieee.c, avoid unnecessary code duplication in md_atof(). This will then also allow to take advantage of adjustments made there without needing to mirror them here.
2021-08-11Arm32: leave more .bfloat16 processing to common codeJan Beulich1-46/+3
With x86 support having been implemented by extending atof-ieee.c, avoid unnecessary code duplication in md_atof(). This will then also allow to take advantage of adjustments made there without needing to mirror them here.
2021-08-11gas: make 2nd argument of .dcb.* consistently optionalJan Beulich2-55/+78
Unlike the forms consuming/producing integer data, the floating point ones so far required the 2nd argument to be present, contrary to documentation. To avoid code duplication, split float_length() out of hex_float() (taking the opportunity to adjust error message wording).
2021-08-11x86: introduce .bfloat16 directiveJan Beulich8-14/+32
This is to be able to generate data acted upon by AVX512-BF16 and AMX-BF16 insns. While not part of the IEEE standard, the format is sufficiently standardized to warrant handling in config/atof-ieee.c. Arm, where custom handling was implemented, may want to leverage this as well. To be able to also use the hex forms supported for other floating point formats, a small addition to the generic hex_float() is needed. Extend existing x86 testcases.
2021-08-11x86: introduce .hfloat directiveJan Beulich7-6/+21
This is to be able to generate data passed to {,V}CVTPH2PS and acted upon by AVX512-FP16 insns. To be able to also use the hex forms supported for other floating point formats, a small addition to the generic hex_float() is needed. Extend existing x86 testcases.
2021-08-11x86/ELF: fix .tfloat output with hex inputJan Beulich5-4/+29
The ELF psABI-s are quite clear here: On 32-bit the data type is 12 bytes long (with 2 bytes of trailing padding), while on 64-bit it is 16 bytes long (with 6 bytes of padding). Make hex_float() capable of handling such padding. Note that this brings the emitted data size of .dc.x / .dcb.x in line also for non-ELF targets; so far they were different depending on input format (dec vs hex). Extend the existing x86 testcases.
2021-08-11x86/ELF: fix .ds.x outputJan Beulich7-7/+38
The ELF psABI-s are quite clear here: On 32-bit the underlying data type is 12 bytes long (with 2 bytes of trailing padding), while on 64-bit it is 16 bytes long (with 6 bytes of padding). Make s_space() capable of handling 'x' (and 'p') type floating point being other than 12 bytes wide (also adjusting documentation). This requires duplicating the definition of X_PRECISION in the target speciifc header; the compiler would complain if this was out of sync with config/atof-ieee.c. Note that for now padding space doesn't get separated from actual storage, which means that things will work correctly only for little- endian cases, and which also means that by specifying large enough numbers padding space can be set to non-zero. Since the logic is needed for a single little-endian architecture only for now, I'm hoping that this might be acceptable for the time being; otherwise the change will become more intrusive. Note also that this brings the emitted data size of .ds.x vs .tfloat in line for non-ELF targets as well; the issue will be even more obvious when further taking into account a subsequent patch fixing .dc.x/.dcb.x (where output sizes currently differ depending on input format). Extend existing x86 testcases.
2021-08-11x86/ELF: fix .tfloat outputJan Beulich7-6/+60
The ELF psABI-s are quite clear here: On 32-bit the data type is 12 bytes long (with 2 bytes of trailing padding), while on 64-bit it is 16 bytes long (with 6 bytes of padding). Make ieee_md_atof() capable of handling such padding, and specify the needed padding for x86 (leaving non-ELF targets alone for now). Split the existing x86 testcase.
2021-08-10Updated Serbian and Russian translations for various sub-directoriesNick Clifton2-4241/+4330
2021-08-09GAS: DWARF-5: Ensure that the 0'th entry in the directory table contains the ↵Nick Clifton8-18/+91
current working directory. * dwarf2dbg.c (get_directory_table_entry): Ensure that dir[0] contains current working directory. (out_dir_and_file_list): Likewise. * testsuite/gas/elf/dwarf-5-dir0.s: New test source file. * testsuite/gas/elf/dwarf-5-dir0.d: New test driver. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/elf/dwarf-5-file0.d: Adjust expected output. * testsuite/gas/i386/dwarf5-line-1.d: Likewise. * testsuite/gas/i386/dwarf5-line-2.d: Likewise.
2021-08-06Re: Add tests for Intel AVX512_FP16 instructionsAlan Modra1-0/+1
* testsuite/gas/i386/x86-64-avx512_fp16_pseudo_ops.d: Pass with mingw section padding.
2021-08-05[PATCH 2/2] Add tests for Intel AVX512_FP16 instructionsCui,Lili30-0/+26033
Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * testsuite/gas/i386/i386.exp: Run FP16 tests. * testsuite/gas/i386/avx512_fp16-intel.d: New test. * testsuite/gas/i386/avx512_fp16-inval-bcast.l: Ditto. * testsuite/gas/i386/avx512_fp16-inval-bcast.s: Ditto. * testsuite/gas/i386/avx512_fp16.d: Ditto. * testsuite/gas/i386/avx512_fp16.s: Ditto. * testsuite/gas/i386/avx512_fp16_pseudo_ops.d: Ditto. * testsuite/gas/i386/avx512_fp16_pseudo_ops.s: Ditto. * testsuite/gas/i386/avx512_fp16_vl-intel.d: Ditto. * testsuite/gas/i386/avx512_fp16_vl.d: Ditto. * testsuite/gas/i386/avx512_fp16_vl.s: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16-inval-bcast.l: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16-inval-bcast.s: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16.d: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16.s: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16_pseudo_ops.d: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16_pseudo_ops.s: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16_vl-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16_vl.d: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16_vl.s: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16-inval-register.l: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16-inval-register.s: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16-bad.d: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16-bad.s: Ditto. * testsuite/gas/i386/x86-64-default-suffix-avx.d: Add new testcase. * testsuite/gas/i386/x86-64-default-suffix.d: Ditto. * testsuite/gas/i386/x86-64-default-suffix.s: Ditto. * testsuite/gas/i386/xmmword.l: Ditto. * testsuite/gas/i386/xmmword.s: Ditto.
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili3-4/+47
Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-08-04IBM Z: Remove lpswey parameterAndreas Krebbel2-2/+2
opcodes/ * s390-opc.c (INSTR_SIY_RD): New instruction format. (MASK_SIY_RD): New instruction mask. * s390-opc.txt: Change instruction format of lpswey to SIY_RD. gas/ * testsuite/gas/s390/zarch-arch14.d: Remove last operand of lpswey. * testsuite/gas/s390/zarch-arch14.s: Likewise.
2021-08-04gas: correctly output XCOFF tbss symbols with XTY_CM type.Clément Chigot1-1/+2
Global tbss symbols weren't correctly handled and were generating a symbol with XTY_SD instead of XTY_CM as expected. gas/ * config/tc-ppc.c (ppc_frog_symbol): Generate a XTY_CM when a symbol has a storage class of XMC_UL.
2021-08-04gas: always add dummy symbols when creating XCOFF sections.Clément Chigot1-17/+11
Most of the algorithms for XCOFF in tc-ppc.c assume that the csects field of a ppc_xcoff_section isn't NULL. This was already made for most of the sections with the creation of a dummy symbol. This patch simply mades it default when creating a xcoff_section. gas/ * config/tc-ppc.c (ppc_init_xcoff_section): Always create the dummy symbol. (md_begin): Adjust ppc_init_xcoff_section call. (ppc_comm): Likewise. (ppc_change_csect): Likewise.
2021-07-30gas: ensure XCOFF DWARF subsection are initialized to 0Clément Chigot1-1/+1
debug_abbrev doesn't use end_exp to compute its size. However, it must be NULL. Otherwise, ppc_xcoff_end might try to access uninitialized memory. gas/ * config/tc-ppc.c (ppc_dwsect): Use XCNEW instead of XNEW when creating a new subsection.
2021-07-29gas: improve C_BSTAT and C_STSYM symbols handling on XCOFFClément Chigot7-3/+81
A C_BSTAT debug symbol specifies the beginning of a static block. Its n_value is the index of the csect containing static symbols. A C_STSYM debug symbol represents the stabstring of a statically allocated symbol. Its n_value is the offset in the csect pointed by the containing C_BSTAT. These two special n_value were not correctly handled both when generating object files with gas or when reading them with objdump. This patch tries to improve that and, above all, to allow gas-generated object files with such symbols to be accepted by AIX ld. bfd/ * coff-bfd.c (bfd_coff_get_syment): Adjust n_value of symbols having fix_value = 1 in order to be an index and not a memory offset. * coffgen.c (coff_get_symbol_info): Likewize. (coff_print_symbol): Likewize. gas/ * config/tc-ppc.c (ppc_frob_label): Don't change within if already set. (ppc_stabx): Remove workaround changing exp.X_add_symbol's within. * config/tc-ppc.h (struct ppc_tc_sy): Update comments. * symbols.c (resolve_symbol_value): Remove symbol update when final_val is 0 and it's an AIX debug symbol. * testsuite/gas/ppc/aix.exp: Add new tests. * testsuite/gas/ppc/xcoff-stsym-32.d: New test. * testsuite/gas/ppc/xcoff-stsym-64.d: New test. * testsuite/gas/ppc/xcoff-stsym.s: New test.
2021-07-28x86: Simplify check for distinct TMM register operandsH.J. Lu1-15/+10
If any pair of operands in AMX instructions with 3 TMM register operands are the same, the instruction will UD. Don't call register_number to check for distinct TMM register operands since all TMM register operands have the same size. * config/tc-i386.c (check_VecOperands): Remove register_number call when checking for distinct TMM register operands.
2021-07-28PowerPC: ignore sticky options for .machineAlan Modra1-4/+16
PowerPC gas and objdump for a long time have allowed certain -m/-M options that extend a base cpu with extra functional units to be specified before the base cpu. For example, "-maltivec -mpower4" is the same as "-mpower4 -maltivec". See https://sourceware.org/pipermail/binutils/2008-January/054935.html It doesn't make as much sense that .machine keep any of these "sticky" flags when handling a new base cpu. See gcc PR101393. I think that instead .machine ought to override the command line. That's what this patch does. It is still possible to extend cpu functionality with .machine. For example the following can be assembled when selecting a basic -mppc on the command line: .machine power5 .machine altivec frin 1,2 lvsr 3,4,5 Here, ".machine altivec" extends the ".machine power5" so that both the power5 "frin" instruction and the altivec "lvsr" instruction are enabled. Swapping the two ".machine" directives would result in failure to assemble "lvsr". This change will expose some assembly errors, such as the one in glibc/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c, a file compiled with -maltivec but containing asm volatile (".machine push;\n" ".machine \"power5\";\n" "vspltisb %0,0;\n" "vspltisb %1,-1;\n" "vpkuwus %0,%0,%1;\n" "mfvscr %0;\n" "stvx %0,0,%2;\n" ".machine pop;" : "=v" (v0), "=v" (v1) : "r" (vscr_ptr) : "memory"); It's just wrong to choose power5 for a bunch of altivec instructions and in fact all of those .machine directives are unnecessary. * config/tc-ppc.c (ppc_machine): Don't use command line sticky options.
2021-07-26PATCH [10/10] arm: Alias 'ra_auth_code' to r12 for pacbti.Andrea Corallo1-0/+3
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (reg_names): Alias 'ra_auth_code' to r12.
2021-07-26PATCH [9/10] arm: add 'pacg' instruction for Armv8.1-M pacbti extensionAndrea Corallo3-0/+16
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (T16_32_TAB): Add '_pacg'. (do_t_pacbti_pacg): New function. (insns): Define 'pacg' insn. * testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacg' test. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'pacg'.
2021-07-26PATCH [8/10] arm: add 'autg' instruction for Armv8.1-M pacbti extensionAndrea Corallo3-0/+4
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (T16_32_TAB): Add '_autg'. (insns): Define 'autg' insn. * testsuite/gas/arm/armv8_1-m-pacbti.d: Add autg test. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'autg'.
2021-07-26PATCH [7/10] arm: add 'bxaut' instruction for Armv8.1-M pacbti extensionAndrea Corallo3-1/+17
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (T16_32_TAB): Add '_bxaut'. (do_t_pacbti_nonop): New function. (insns): Define 'bxaut' insn. * testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'bxaut' test. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'bxaut'.
2021-07-26PATCH [6/10] arm: Add -march=armv8.1-m.main+pacbti flagAndrea Corallo1-0/+4
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (pacbti_ext): Define. (BAD_PACBTI): New macro. (armv8_1m_main_ext_table): Add 'pacbti' extension. include/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * opcode/arm.h (ARM_EXT3_PACBTI, ARM_AEXT3_V8_1M_MAIN_PACBTI): New macro.
2021-07-26PATCH [4/10] arm: add 'pac' instruction for Armv8.1-M pacbti extensionAndrea Corallo5-0/+10
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (T16_32_TAB): Add '_pac'. (insns): Add 'pac' insn. * testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Add pac tests. * testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.d: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'pac'.
2021-07-26PATCH [3/10] arm: add 'aut' instruction for Armv8.1-M pacbti extensionAndrea Corallo5-0/+10
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (insns): Add 'aut.' (T16_32_TAB): Add '_aut'. * testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Add 'aut' tests. * testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.d: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'aut'.
2021-07-26PATCH [2/10] arm: add 'pacbti' instruction for Armv8.1-M pacbti extensionAndrea Corallo6-0/+41
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (enum operand_parse_code): Add OP_SP and OP_R12. (parse_operands): Add switch cases for OP_SP and OP_R12. (T16_32_TAB): Add '_pacbti'. (do_t_pacbti): New function. (insns): Add 'pacbti'. * testsuite/gas/arm/armv8_1-m-pacbti-bad.d: New file. * testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacbti' to testcase. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'pacbti' instruction.
2021-07-26PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extensionAndrea Corallo3-0/+16
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (insns): Add 'bti' insn. * testsuite/gas/arm/armv8_1-m-pacbti.d: New file. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add bti instruction.
2021-07-24Revert: PowerPC: Don't generate unused section symbolsAlan Modra3-0/+3
Blindly following x86 broke linux kernel builds. bfd/ * elf32-ppc.c (TARGET_KEEP_UNUSED_SECTION_SYMBOLS): Define as true. * elf64-ppc.c (TARGET_KEEP_UNUSED_SECTION_SYMBOLS): Likewise. gas/ * testsuite/gas/ppc/power4.d: Adjust for section sym change. * testsuite/gas/ppc/test1elf32.d: Likewise. * testsuite/gas/ppc/test1elf64.d: Likewise. ld/ * testsuite/ld-powerpc/tlsexe.r: Adjust for section sym change. * testsuite/ld-powerpc/tlsexe32.r: Likewise. * testsuite/ld-powerpc/tlsexe32no.r: Likewise. * testsuite/ld-powerpc/tlsexeno.r: Likewise. * testsuite/ld-powerpc/tlsexenors.r: Likewise. * testsuite/ld-powerpc/tlsexers.r: Likewise. * testsuite/ld-powerpc/tlsexetoc.r: Likewise. * testsuite/ld-powerpc/tlsexetocrs.r: Likewise. * testsuite/ld-powerpc/tlsget.d: Likewise. * testsuite/ld-powerpc/tlsget.wf: Likewise. * testsuite/ld-powerpc/tlsget2.d: Likewise. * testsuite/ld-powerpc/tlsget2.wf: Likewise. * testsuite/ld-powerpc/tlsso.r: Likewise. * testsuite/ld-powerpc/tlsso32.r: Likewise. * testsuite/ld-powerpc/tlstocso.r: Likewise.
2021-07-23x86: express unduly set rounding control bits in disassemblyJan Beulich6-26/+28
While EVEX.L'L are indeed ignored when EVEX.b stands for just SAE, EVEX.b itself is not ignored when an insn permits neither rounding control nor SAE. While changing this aspect of EVEX.b handling, also alter unduly set embedded broadcast: Don't call BadOp(), screwing up subsequent disassembly, but emit "{bad}" instead.
2021-07-22x86: drop dq{b,d}_modeJan Beulich5-84/+84
Their sole use is for {,V}EXTRACTPS / {,V}P{EXT,INS}RB respectively; for consistency also limit use of dqw_mode to Jdqw. 64-bit disassembly reflecting REX.W / VEX.W is not in line with the assembler's opcode table having NoRex64 / VexWIG in all respective templates, i.e. assembly input isn't being honored there either. Obviously the 0FC5 encodings of {,V}PEXTRW then also need adjustment for consistency reasons.
2021-07-22x86: correct EVEX.V' handling outside of 64-bit modeJan Beulich1-2/+2
Unlike the high bit of VEX.vvvv / EVEX.vvvv, EVEX.V' is not ignored outside of 64-bit mode. Oddly enough there already are tests for these cases, but their expectations were wrong. (This may have been based on an old SDM version, where the restriction wasn't properly spelled out.)
2021-07-22x86-64: properly bounds-check %bnd<N> in OP_G()Jan Beulich2-0/+16
The restriction to %bnd0-%bnd3 requires to also check REX.R is clear, just like OP_E_Register() also includes REX.B in its check.
2021-07-22x86-64: generalize OP_G()'s EVEX.R' handlingJan Beulich3-0/+6
EVEX.R' is invalid to be clear not only for mask registers, but also for GPRs - IOW everything handled in this function.
2021-07-22x86: correct VCVT{,U}SI2SD rounding mode handlingJan Beulich4-1/+28
With EVEX.W clear the instruction doesn't ignore the rounding mode, but (like for other insns without rounding semantics) EVEX.b set causes #UD. Hence the handling of EVEX.W needs to be done when processing evex_rounding_64_mode, not at the decode stages. Derive a new 64-bit testcase from the 32-bit one to cover the different EVEX.W treatment in both cases.
2021-07-21as_bad_subtractAlan Modra33-149/+121
Many places report errors of the nature "can't resolve a - b". This provides a utility function to report such errors consistently. I removed the section reporting and quotes around symbol names while I was at it. Compare ifunc-2.s:4: Error: can't resolve `bar1' {.text.1 section} - `foo1' {.text.1 section} with ifunc-2.s:4: Error: can't resolve bar1 - foo1 In many cases the section names don't help the user very much in figuring out what went wrong, and the quotes if present arguably ought to be placed around the entire expression: can't resolve `bar1 - foo1' The patch also tidies some tc_get_reloc functions that leak memory on error paths. * write.h (as_bad_subtract): Declare. * write.c (as_bad_subtract): New function. (fixup_segment): Use as_bad_subtract. * config/tc-arc.c (md_apply_fix): Likewise. * config/tc-avr.c (md_apply_fix, tc_gen_reloc): Likewise. * config/tc-cris.c (md_apply_fix): Likewise. * config/tc-d10v.c (md_apply_fix): Likewise. * config/tc-d30v.c (md_apply_fix): Likewise. * config/tc-ft32.c (md_apply_fix): Likewise. * config/tc-h8300.c (tc_gen_reloc): Likewise. * config/tc-m68hc11.c (md_apply_fix): Likewise. * config/tc-mmix.c (mmix_frob_file): Likewise. * config/tc-mn10200.c (tc_gen_reloc): Likewise. * config/tc-nds32.c (nds32_apply_fix): Likewise. * config/tc-pru.c (md_apply_fix): Likewise. * config/tc-riscv.c (md_apply_fix): Likewise. * config/tc-s12z.c (md_apply_fix): Likewise. * config/tc-s390.c (md_apply_fix): Likewise. * config/tc-tilegx.c (md_apply_fix): Likewise. * config/tc-tilepro.c (md_apply_fix): Likewise. * config/tc-v850.c (md_apply_fix): Likewise. * config/tc-vax.c (md_apply_fix): Likewise. * config/tc-xc16x.c (tc_gen_reloc): Likewise. * config/tc-xgate.c (md_apply_fix): Likewise. * config/tc-xstormy16.c (xstormy16_md_apply_fix): Likewise. * config/tc-xtensa.c (md_apply_fix): Likewise. * config/tc-z80.c (tc_gen_reloc): Likewise. * config/tc-spu.c (md_apply_fix): Likewise. (tc_gen_reloc): Delete dead code. Free memory on error. * config/tc-cr16.c (tc_gen_reloc): Use as_bad_subtract. Free on error. * config/tc-crx.c (tc_gen_reloc): Likewise. * config/tc-ppc.c (tc_gen_reloc): Likewise. * testsuite/gas/i386/ifunc-2.l: Adjust to suit changed error message. * testsuite/gas/mips/lui-2.l: Likewise. * testsuite/gas/tic6x/reloc-bad-1.l: Likewise.
2021-07-21Remove `netbsdpe` supportJohn Ericson1-1/+0
netbsdpe was deprecated in c2ce831330e10dab4703094491f80b6b9a5c2289. Since then, a release has passed (2.37), and it was marked obselete in 5c9cbf07f3f972ecffe13d858010b3179df17b32. Unless I am mistaken, that means we can now remove support altogether. All branches in the "active" code are remove, and the target is additionally marked as obsolete next to the other removed ones for libbfd and gdb. Per [1] from the NetBSD toolchain list, PE/COFF support was removed a decade ago. Furthermore, the sole mention of this target in the binutils commit history was in 2002. Together, I'm led to believe this target hasn't seen much attention in quite a while. [1]: https://mail-index.netbsd.org/tech-toolchain/2021/06/16/msg003996.html bfd/ * config.bfd: Remove netbsdpe entry. binutils/ * configure.ac: Remove netbsdpe entry. * testsuite/lib/binutils-common.exp (is_pecoff_format): Likewise. * configure: Regenerate. gas/ * configure.tgt: Remove netbsdpe entry. gdb/ * configure.tgt: Add netbsdpe to removed targets. ld/ * configure.tgt: Remove netbsdpe entry. * testsuite/ld-bootstrap/bootstrap.exp: Likewise.
2021-07-20RISC-V: Minor updates for architecture parser.Nelson Chu2-2/+2
* Two add subset functions is redundant. Keep the riscv_add_implicit_subset, and renamed it to riscv_add_subset. Besides, if the subset is added in order, then we just add it at the tail of the subset list. * Removed the "-march:" prefix from the error messages. Since not only the -march= option will use the parser, but also the architecture elf attributes, the default architecture setting and linker will use the same parser. * Use a function, riscv_parse_check_conflicts, to check the conflicts of extensions, including the rv64e and rv32q. The rv32emc-elf/rv32i-elf/rv32gc-linux/rv64gc-elf/rv64gc-linux regressions are tested and passed. bfd/ * elfxx-riscv.c (riscv_lookup_subset): Check the subset tail list first. If the subset is added in order, then we can just add it to the tail without searching the whole list. (riscv_add_subset): Replaced by riscv_add_implicit_subset. (riscv_add_implicit_subset): Renamed to riscv_add_subset. (riscv_parse_add_subset): Updated. (riscv_parsing_subset_version): Removed the "-march:" prefix from the error message. (riscv_parse_prefixed_ext): Likewise. (riscv_parse_std_ext): Likewise. And move the rv<xlen>e check to riscv_parse_check_conflicts. (riscv_parse_check_conflicts): New function used to check conflicts. (riscv_parse_subset): Updated. gas/ * testsuite/gas/riscv/march-fail-base-02.l: Updated. * testsuite/gas/riscv/march-fail-unknown-std.l: Likewise.
2021-07-14x86: Add int1 as one byte opcode 0xf1H.J. Lu6-0/+12
Also change the x86 disassembler to disassemble 0xf1 as int1, instead of icebp. gas/ PR gas/28088 * testsuite/gas/i386/opcode.s: Add int1. * testsuite/gas/i386/x86-64-opcode.s: Add int1, int3 and int. * testsuite/gas/i386/opcode-intel.d: Updated. * testsuite/gas/i386/opcode-suffix.d: Likewise. * testsuite/gas/i386/opcode.d: Likewise. * testsuite/gas/i386/x86-64-opcode.d: Likewise. opcodes/ PR gas/28088 * i386-dis.c (dis386): Replace icebp with int1. * i386-opc.tbl: Add int1. * i386-tbl.h: Regenerate.
2021-07-14gas: default TC_VALIDATE_FIX_SUB to 0Alan Modra6-13/+27
gas/write.c provides a fallback TC_VALIDATE_FIX_SUB define that can be a problem for some targets, the problem being that a non-zero definition of TC_VALIDATE_FIX_SUB says that some uses of fx_subsy are OK, in effect that the target will handle fx_subsy in md_apply_fix and/or tc_gen_reloc. A lot of targets don't have the necessary md_apply_fix and tc_gen_reloc support. So a safer default is to disallow fx_subsy by default. I've had a good look over target usage of fx_subsy, and think I've caught all the cases where targets need TC_VALIDATE_FIX_SUB. Possible failures would be limited to alpha, microblaze, ppc and s390 (the targets that define UNDEFINED_DIFFERENCE_OK), or targets that generate fixups with BFD_RELOC_GPREL32/16 and use a syntax explicitly showing a difference expression. * write.c (TC_VALIDATE_FIX_SUB): Default to 0. * config/tc-hppa.h (TC_VALIDATE_FIX_SUB): Define. * config/tc-microblaze.h (TC_VALIDATE_FIX_SUB): Define. * config/tc-alpha.h (TC_VALIDATE_FIX_SUB): Define for ECOFF. * config/tc-ppc.h (TC_VALIDATE_FIX_SUB): Don't define for ELF. Do define for XCOFF.
2021-07-14objdump: add DWARF support for AIXClément Chigot2-1/+6
DWARF sections have special names on AIX which need be handled by objdump in order to correctly print them. This patch also adds the correlation in bfd for future uses. bfd/ * libxcoff.h (struct xcoff_dwsect_name): Add DWARF name. * coff-rs6000.c (xcoff_dwsect_names): Update. * coffcode.h (sec_to_styp_flags): Likewise. (coff_new_section_hook): Likewise. binutils/ * dwarf.h (struct dwarf_section): Add XCOFF name. * dwarf.c (struct dwarf_section_display): Update. * objdump.c (load_debug_section): Add XCOFF name handler. (dump_dwarf_section): Likewise. gas/ * config/tc-ppc.c (ppc_change_debug_section): Update to match new name's field.
2021-07-13RISC-V: Enable elf attributes when default configure option isn't set.Nelson Chu2-16/+2
Since gcc commit, 3c70b3ca1ef58f302bf8c16d9e7c7bb8626408bf, we now enable elf attributes for all riscv targets by default in gcc. Therefore, I think binutils should have the same behavior, in case users are writing assembly files. If --enable-default-riscv-attribute isn't set, then we enable the elf attributes for all riscv targets by default. ChangLog: binutils/ * testsuite/binutils-all/readelf.s: Add comments for riscv. * testsuite/binutils-all/readelf.s-64: Likewise. * testsuite/binutils-all/readelf.s-64-unused: Likewise. * testsuite/binutils-all/readelf.ss: Likewise. * testsuite/binutils-all/readelf.ss-64: Likewise. * testsuite/binutils-all/readelf.ss-64-unused: Likewise. gas/ * configure.ac: If --enable-default-riscv-attribute isn't set, then we enable the elf attributes for all riscv targets by default. * configure: Regenerated.
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