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2022-09-07LoongArch: fix gas BFD_RELOC_8/16/24 bugmengqinggang3-18/+58
If fixP->fx_subsy is NULL, BFD_RELOC_8/16/24 can't convert to BFD_RELOC_LARCH_xxx. gas/config/tc-loongarch.c
2022-09-02RISC-V: Print highest address (-1) on the disassemblerTsukasa OI6-0/+71
This patch makes possible to print the highest address (-1) and the addresses related to gp which value is -1. This is particularly useful if the highest address space is used for I/O registers and corresponding symbols are defined. Besides, despite that it is very rare to have GP the highest address, it would be nice because we enabled highest address printing on regular cases. gas/ChangeLog: * testsuite/gas/riscv/dis-addr-topaddr.s: New test for the top address (-1) printing. * testsuite/gas/riscv/dis-addr-topaddr-32.d: Likewise. * testsuite/gas/riscv/dis-addr-topaddr-64.d: Likewise. * testsuite/gas/riscv/dis-addr-topaddr-gp.s: New test for GP-relative addressing when GP is the highest address (-1). * testsuite/gas/riscv/dis-addr-topaddr-gp-32.d: Likewise. * testsuite/gas/riscv/dis-addr-topaddr-gp-64.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (struct riscv_private_data): Add `to_print_addr' to enable printing the highest address. (maybe_print_address): Utilize `to_print_addr'. (riscv_disassemble_insn): Likewise.
2022-09-02RISC-V: PR29342, Fix RV32 disassembler address computationTsukasa OI4-1/+135
If either the base register is `zero', `tp' or `gp' and XLEN is 32, an incorrectly sign-extended address is produced when printing. This commit fixes this by fitting an address into a 32-bit value on RV32. Besides, H. Peter Anvin discovered that we have wrong address computation for JALR instruction (the initial bug is back in 2018). This commit also fixes that based on the idea of Palmer Dabbelt. gas/ pr29342 * testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix. * testsuite/gas/riscv/dis-addr-overflow.s: New testcase. * testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise. * testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise. opcodes/ pr29342 * riscv-dis.c (maybe_print_address): Fit address into 32-bit on RV32. (print_insn_args): Fix JALR address by adding EXTRACT_ITYPE_IMM.
2022-09-02RISC-V: Add address printer tests with ADDIWTsukasa OI3-0/+64
Address sequences involving ADDIW/C.ADDIW instructions require special handling to sign-extend lower 32-bits of the original result. This commit tests whether this sign-extension works. gas/ChangeLog: * testsuite/gas/riscv/dis-addr-addiw.s: New to test the address computation with sign extension as used in ADDIW/C.ADDIW. * testsuite/gas/riscv/dis-addr-addiw-a.d: Test PC sign bit 0. * testsuite/gas/riscv/dis-addr-addiw-b.d: Test PC sign bit 1. gas/ChangeLog: * testsuite/gas/riscv/dis-addr-addiw-a.d: New test. * testsuite/gas/riscv/dis-addr-addiw-b.d: New test. * testsuite/gas/riscv/dis-addr-addiw.s: New test.
2022-08-31Add OpenBSD AArch64 GAS support.Frederic Cambus2-0/+5
* configure.tgt (aarch64*-*-openbsd*): Add target.
2022-08-30Add a testcase for PR 29494.Nick Clifton3-0/+10001
PR 29494 * testsuite/gas/arm/pr29494.s: New test source file. * testsuite/gas/arm/pr29494.d: New test driver.
2022-08-30LoongArch: Fix redefinition of "PACKAGE".liuzhensong1-1/+1
Running configure and make in binutils-gdb. $ ./configure $ make In file included from ./as.h:37, from ./config/loongarch-lex.l:21, from config/loongarch-lex-wrapper.c:20: ./config.h:206: error: “PACKAGE” redefined [-Werror] #define PACKAGE "gas" ... gas/config * loongarch-lex-wrapper.c
2022-08-30RISC-V: Add 'Zmmul' extension in assembler.Tsukasa OI15-2/+143
Three-part patch set from Tsukasa OI to support zmmul in assembler. The 'Zmmul' is a RISC-V extension consisting of only multiply instructions (a subset of 'M' which has multiply and divide instructions). bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' implied by 'M'. (riscv_supported_std_z_ext): Add 'Zmmul' extension. (riscv_multi_subset_supports): Add handling for new instruction class. gas/ * testsuite/gas/riscv/attribute-09.d: Updated implicit 'Zmmul' by 'M'. * testsuite/gas/riscv/option-arch-02.d: Likewise. * testsuite/gas/riscv/m-ext.s: New test. * testsuite/gas/riscv/m-ext-32.d: New test (RV32). * testsuite/gas/riscv/m-ext-64.d: New test (RV64). * testsuite/gas/riscv/zmmul-32.d: New expected output. * testsuite/gas/riscv/zmmul-64.d: Likewise. * testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure by using RV64-only instructions in RV32). * testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise. * testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test (RV32 + Zmmul but with no M). * testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise. * testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test (RV64 + Zmmul but with no M). * testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise. * testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test (no Zmmul or M). * testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise. include/ * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZMMUL. ld/ * testsuite/ld-riscv-elf/attr-merge-arch-01.d: We don't care zmmul in these testcases, so just replaced m by a. * testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s: Renamed. * testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s: Renamed. opcodes/ * riscv-opc.c (riscv_opcodes): Updated multiply instructions to zmmul.
2022-08-28PR29494 Trailing jump table on ARMAlan Modra1-6/+6
out_inc_line_addr and relax_inc_line_addr are passed INT_MAX as line_delta to flag end of section. This filters its way down to size_inc_line_addr and emit_inc_line_addr. Pass line_delta on to scale_addr_delta where it can be used to omit an unaligned opcode error. PR 29494 * dwarf2dbg.c (scale_addr_delta): Delete unnecessary forward decl. Add line_delta param. Don't print error at end of section, just round the address down. (size_inc_line_addr, emit_inc_line_addr): Adjust calls.
2022-08-25GAS: Add a return type tag to DWARF DIEs generated for function symbols.Nick Clifton6-4/+82
PR 29517 * dwarf2dbg.c (GAS_ABBREV_COMP_UNIT): New defined constant. (GAS_ABBREV_SUBPROG): New defined constant. (GAS_ABBREV_NO_TYPE): New defined constant. (out_debug_abbrev): Use the new defined constants when emitting abbreviation numbers. Generate an abbreviation for an unspecified type. (out_debug_info): Use the new defined constants when referring to abbreviations. Generate a use of the no_type abbreviation. Reference the use when generating DIEs for functions. * testsuite/gas/elf/dwarf-3-func.d: Update to allow for newly extended output from the assembler. * testsuite/gas/elf/dwarf-5-func-global.d: Likewise. * testsuite/gas/elf/dwarf-5-func-local.d: Likewise. * testsuite/gas/elf/dwarf-5-func.d: Likewise.
2022-08-25GAS: Allow AArch64 pseudo-ops to accept the command line separator character.Nick Clifton4-12/+30
PR 29519 * config/tc-aarch64.c (s_unreq): Use find_end_of_line(). (s_aarch64_cpu): Likewise. (s_aarch64_arch): Likewise. (s_aarch64_arch_extension): Likewise. * testsuite/gas/aarch64/pr29519.d: New test driver file. * testsuite/gas/aarch64/pr29519.s: New test source file.
2022-08-25gas: NEWS: Add the RISC-V features for 2.39Palmer Dabbelt1-0/+12
2022-08-25gas: NEWS: Add the RISC-V features for 2.38Palmer Dabbelt1-0/+11
2022-08-25gas: NEWS: Add the RISC-V features for 2.37Palmer Dabbelt1-0/+3
2022-08-25gas: NEWS: Add the RISC-V features for 2.36Palmer Dabbelt1-0/+2
2022-08-25gas: NEWS: Add the RISC-V features for 2.35Palmer Dabbelt1-0/+5
2022-08-25gas: NEWS: Add the RISC-V features for 2.31Palmer Dabbelt1-0/+2
2022-08-24gas: arm: handle multiple .directives on a single line (PR29519)Richard Earnshaw3-20/+73
There's been a long-standing bug in the arm backend where target-specific directives did not correctly handle lines with multiple statements. This patch fixes the issue for all the cases I've been able to find. It does result in a slight change in behaviour when errors are encountered: where, previously, .cpu arm6 bar would result in the error "junk at end of line, first unrecognized character is `b'", we now get "unknown cpu `arm6 bar'", which I think is slightly more helpful anyway. Similar errors are generated for other directives.
2022-08-22LoongArch: gas: add support using constant variable in instructions.tangxiaolin11-18/+352
Instructions that can load immediate support using constant variable like ".equ var, 123 li.w/d resgister, var". gas/ * config/loongarch-parse.y * config/tc-loongarch.c Add four testcases.One is a program using constant variable, one test using label is unsupported, and another two test almost instructions that can load immediate. gas/ * testsuite/gas/loongarch/li.d * testsuite/gas/loongarch/li.s * testsuite/gas/loongarch/imm_ins_label-fail.d * testsuite/gas/loongarch/imm_ins_label-fail.l * testsuite/gas/loongarch/imm_ins_label-fail.s * testsuite/gas/loongarch/imm_ins.d * testsuite/gas/loongarch/imm_ins.s * testsuite/gas/loongarch/imm_ins_32.d * testsuite/gas/loongarch/imm_ins_32.s
2022-08-18x86: move / quiesce pre-386 non-16-bit warningJan Beulich1-6/+12
Emitting this warning for every insn, including ones having actual errors, is annoying. Introduce a boolean variable to emit the warning just once on the first insn after .arch may have changed the things, and move the warning to output_insn(). (I didn't want to go as far as checking whether the .arch actually turned off the i386 bit, but doing so would be an option.)
2022-08-18x86: insert "no error" enumerator in i386_error enumerationJan Beulich1-0/+1
The value of zero would better not indicate any error, but rather hit the abort() at the top of the consuming switch().
2022-08-16i386: Add MAX_OPERAND_BUFFER_SIZEH.J. Lu3-0/+14
When displaying operands, invalid opcodes may overflow operand buffer due to additional styling characters. Each style is encoded with 3 bytes. Define MAX_OPERAND_BUFFER_SIZE for operand buffer size and increase it from 100 bytes to 128 bytes to accommodate 9 sets of styles in an operand. gas/ PR binutils/29483 * testsuite/gas/i386/i386.exp: Run pr29483. * testsuite/gas/i386/pr29483.d: New file. * testsuite/gas/i386/pr29483.s: Likewise. opcodes/ PR binutils/29483 * i386-dis.c (MAX_OPERAND_BUFFER_SIZE): New. (obuf): Replace 100 with MAX_OPERAND_BUFFER_SIZE. (staging_area): Likewise. (op_out): Likewise.
2022-08-13readelf: print 0x0 as 0, and remove trailing spacesAlan Modra54-154/+153
This changes readelf output a little, removing the 0x prefix on hex output when the value is 0, except in cases where a fixed field width is shown. %#010x is not a good replacement for 0x%08x.
2022-08-11ppc/svp64: support svindex instructionDmitry Selyutin3-0/+25
https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/remap/#svindex https://libre-soc.org/openpower/isa/simplev/
2022-08-11ppc/svp64: support svremap instructionDmitry Selyutin3-0/+25
https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/remap/#svremap https://libre-soc.org/openpower/isa/simplev/
2022-08-11ppc/svp64: support svshape instructionDmitry Selyutin3-0/+19
https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/remap/#svshape https://libre-soc.org/openpower/isa/simplev/
2022-08-11ppc/svp64: support svstep instructionsDmitry Selyutin3-0/+19
https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/svstep/ https://libre-soc.org/openpower/isa/simplev/
2022-08-11ppc/svp64: support setvl instructionsDmitry Selyutin3-0/+24
https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/setvl/ https://libre-soc.org/openpower/isa/simplev/
2022-08-11ppc/svp64: introduce non-zero operand flagDmitry Selyutin1-3/+18
svstep and svshape instructions subtract 1 before encoding some of the operands. Obviously zero is not supported for these operands. Whilst PPC_OPERAND_PLUS1 fits perfectly to mark that maximal value should be incremented, there is no flag which marks the fact that zero values are not allowed. This patch adds a new flag, PPC_OPERAND_NONZERO, for this purpose.
2022-08-11ppc/svp64: support LibreSOC architectureDmitry Selyutin1-0/+2
This patch adds support for LibreSOC machine and SVP64 extension flag for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit Prefixed instruction format implementing SV. Funded by NLnet through EU Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly submitted via the OpenPOWER Foundation ISA Working Group via the newly-created External RFC Process. For more details, visit https://libre-soc.org.
2022-08-11PR29466, APP/NO_APP with .linefileAlan Modra9-4/+43
Commit 53f2b36a54b9 exposed a bug in sb_scrub_and_add_sb that could result in losing input. If scrubbing results in expansion past the holding capacity of do_scrub_chars output buffer, then do_scrub_chars stashes the extra input for the next call. That call never came because sb_scrub_and_add_sb wrongly decided it was done. Fix that by allowing sb_scrub_and_add_sb to see whether there is pending input. Also allow a little extra space so that in most cases we won't need to resize the output buffer. sb_scrub_and_add_sb also limited output to the size of the input, rather than the actual output buffer size. Fixing that resulted in a fail of gas/testsuite/macros/dot with an extra warning: "end of file not at end of a line; newline inserted". OK, so the macro in dot.s really does finish without end-of-line. Apparently the macro expansion code relied on do_scrub_chars returning early. So fix that too by adding a newline if needed in macro_expand_body. PR 29466 * app.c (do_scrub_pending): New function. * as.h: Declare it. * input-scrub.c (input_scrub_include_sb): Add extra space for two .linefile directives. * sb.c (sb_scrub_and_add_sb): Take into account pending input. Allow output to max. * macro.c (macro_expand_body): Add terminating newline. * testsuite/config/default.exp (SIZE, SIZEFLAGS): Define. * testsuite/gas/macros/app5.d, * testsuite/gas/macros/app5.s: New test. * testsuite/gas/macros/macros.exp: Run it.
2022-08-10gas/Dwarf: properly skip zero-size functionsJan Beulich1-19/+20
PR gas/29451 While out_debug_abbrev() properly skips such functions, out_debug_info() mistakenly didn't. It needs to calculate the high_pc expression ahead of time, in order to skip emitting any data for the function if the value is zero. The one case which would still leave a zero-size entry is when symbol_get_obj(symp)->size ends up evaluating to zero. I hope we can expect that to not be the case, otherwise we'd need to have a way to post-process .debug_info contents between resolving expressions and actually writing the data out to the file. Even then it wouldn't be entirely obvious in which way to alter the data.
2022-08-09Another gas manual typo correction.Stepan Nemec1-1/+1
2022-08-09Fix typos in assembler documentation.Stepan Nemec1-10/+11
2022-08-09x86-64: adjust MOVQ to/from SReg attributesJan Beulich2-6/+20
It is unclear to me why the corresponding MOV (no Q suffix) can be issued without REX.W, but MOVQ has to have that prefix (bit). Add NoRex64 and in exchange drop Size64.
2022-08-09x86: allow use of broadcast with X/Y/Z-suffixed AVX512-FP16 insnsJan Beulich6-0/+9
While the x/y/z suffix isn't necessary to use in this case, it is still odd that these forms don't support broadcast (unlike their AVX512F / AVX512DQ counterparts). The lack thereof can e.g. make macro-ized programming more difficult.
2022-08-08Mach-O: i18n enablement on some error messages.Tsukasa OI2-2/+7
* config/obj-macho.c (obj_mach_o_get_section_names): Wrap two string literals within with gettext macro.
2022-08-05gas: fix a testcase broken by new ZSTD supportTsukasa OI2-3/+2
The commit 1369522f36eece1b37139a81f7f2139ba3915172 ("Recognize the new ELF compression type for ZSTD.") added the new ELF compression type but it accidentally broke a GAS testcase. Since testing for the section type "2048" (SHF_COMPRESSED) is not going to be portable in the long term, it now tests SHF_LINK_ORDER ("128") instead. Using SHF_LINK_ORDER (with possibly sh_link == 0) is an idea by Jan Beulich. gas/ChangeLog: * testsuite/gas/elf/section10.s: Use SHF_LINK_ORDER to test mixed numeric and alpha values. * testsuite/gas/elf/section10.d: Reflect the change above.
2022-08-05When gas/read.c calls mbstowcs with a NULL destination, it should set size to 0Nick Clifton2-1/+10
PR 29447 * read.c (read_symbol_name): Pass 0 as the length parameter when invoking mbstowc in order to check the validity of a wide string.
2022-08-04Don't use BFD_VMA_FMT in binutilsAlan Modra4-14/+14
BFD_VMA_FMT can't be used in format strings that need to be translated, because the translation won't work when the type of bfd_vma differs from the machine used to compile .pot files. We've known about this for a long time, but patches slip through review. So just get rid of BFD_VMA_FMT, instead using the appropriate PRId64, PRIu64, PRIx64 or PRIo64 and SCN variants for scanf. The patch is mostly mechanical, the only thing requiring any thought is casts needed to preserve PRId64 output from bfd_vma values, or to preserve one of the unsigned output formats from bfd_signed_vma values.
2022-08-03x86: improve/shorten vector zeroing-idiom optimization conditionalJan Beulich1-12/+7
- Drop the rounding type check: We're past template matching, and none of the involved insns support embedded rounding. - Drop the extension opcode check: None of the involved opcodes have variants with it being other than None. - Instead check opcode space, even if just to be on the safe side going forward. - Reduce the number of comparisons by folding two groups.
2022-08-03x86: also use D for MOVBEJan Beulich1-7/+7
First of all rename the meanwhile misleading Opcode_SIMD_FloatD, as it has also been used for KMOV* and BNDMOV. Then simplify the condition selecting which form if "reversing" to use - except for the MOV to/from control/debug/test registers all extended opcode space insns use bit 0 (rather than bit 1) to indicate the direction (from/to memory) of an operation. With that, D can simply be set on the first of the two templates, while the other can be dropped.
2022-08-02arm: Add cfi expression support for ra_auth_codeVictor Do Nascimento3-0/+57
This patch extends assembler support for the use of register names to allow for pseudo-registers, e.g. ra_auth_code register. This is done particularly with CFI directives in mind, allowing for expressions of the type: .cfi_register ra_auth_code, 12 gas/Changelog: * config/tc-arm.c (tc_arm_regname_to_dw2regnum): Add REG_TYPE_PSEUDO handling. * testsuite/gas/arm/cfi-pacbti-m-readelf.d: New. * testsuite/gas/arm/cfi-pacbti-m.s: New.
2022-08-02arm: Use DWARF numbering convention for pseudo-register representationVictor Do Nascimento3-70/+95
This patch modifies the internal `struct reg_entry' numbering of DWARF pseudo-registers to match values assigned in DWARF standards (see "4.1 DWARF register names" in [1])so ra_auth_code goes from 12 to 143 and amends the unwinder .save directive-processing code to correctly handle mixed register-type save directives. The mechanism for splitting the register list is also re-written to comply with register ordering on push statements, being that registers are stored on the stack in numerical order, with the lowest numbered register at the lowest address [2]. Consequently, the parsing of the hypothetical directive .save{r4-r7, r10, ra_auth_core, lr} has been changed such as rather than producing .save{r4-r7, r10} .save{ra_auth_code} .save{lr} as was the case with previous implementation, now produces: .save{lr} .save{ra_auth_code} .save{r4-r7, r10} [1] <https://github.com/ARM-software/abi-aa/blob/main/aadwarf32/aadwarf32.rst> [2] <https://developer.arm.com/documentation/dui0473/j/arm-and-thumb-instructions/push> gas/Changelog: * config/tc-arm.c (REG_RA_AUTH_CODE): New. (parse_dot_save): Likewise. (parse_reg_list): Remove obsolete code. (reg_names): Set ra_auth_code to 143. (s_arm_unwind_save): Handle core and pseudo-register lists via parse_dot_save. (s_arm_unwind_save_mixed): Deleted. (s_arm_unwind_save_pseudo): Handle one register at a time. * testsuite/gas/arm/unwind-pacbti-m-readelf.d: Fix test. * testsuite/gas/arm/unwind-pacbti-m.d: Likewise.
2022-08-01x86: SKINIT with operand needs IgnoreSizeJan Beulich3-0/+45
Without it in 16-bit mode a pointless operand size prefix would be emitted.
2022-08-01opcodes: LoongArch: add "ret" instruction to reduce typingWANG Xuerui2-0/+2
This syntactic sugar is present in both classical and emerging architectures, like Alpha, SPARC and RISC-V, and assembler macros doing the same thing can already be found in the wild e.g. [1], proving the feature's popularity. It's better to provide support directly in the assembler so downstream users wouldn't have to re-invent this over and over again. [1]: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/unix/sysv/linux/loongarch/sysdep.h;h=c586df819cd90;hb=HEAD#l28
2022-08-01opcodes: LoongArch: make all non-native jumps desugar to canonical ↵WANG Xuerui1-3/+3
b{lt/ge}[u] forms Also re-order the jump/branch opcodes while at it, so that insns are sorted in ascending order according to opcodes, and the label form preceding the real definition.
2022-08-01Get rid of fprintf_vma and sprintf_vmaAlan Modra12-350/+279
These two macros print either a 16 digit hex number or an 8 digit hex number. Unfortunately they depend on both target and host, which means that the output for 32-bit targets may be either 8 or 16 hex digits. Replace them in most cases with code that prints a bfd_vma using PRIx64. In some cases, deliberately lose the leading zeros. This change some output, notably in base/offset fields of m68k disassembly which I think looks better that way, and in error messages. I've kept leading zeros in symbol dumps (objdump -t) and in PE header dumps. bfd/ * bfd-in.h (fprintf_vma, sprintf_vma, printf_vma): Delete. * bfd-in2.h: Regenerate. * bfd.c (bfd_sprintf_vma): Don't use sprintf_vma. (bfd_fprintf_vma): Don't use fprintf_vma. * coff-rs6000.c (xcoff_reloc_type_tls): Don't use sprintf_vma. Instead use PRIx64 to print bfd_vma values. (xcoff_ppc_relocate_section): Likewise. * cofflink.c (_bfd_coff_write_global_sym): Likewise. * mmo.c (mmo_write_symbols_and_terminator): Likewise. * srec.c (srec_write_symbols): Likewise. * elf32-xtensa.c (print_r_reloc): Similarly for fprintf_vma. * pei-x86_64.c (pex64_dump_xdata): Likewise. (pex64_bfd_print_pdata_section): Likewise. * som.c (som_print_symbol): Likewise. * ecoff.c (_bfd_ecoff_print_symbol): Use bfd_fprintf_vma. opcodes/ * dis-buf.c (perror_memory, generic_print_address): Don't use sprintf_vma. Instead use PRIx64 to print bfd_vma values. * i386-dis.c (print_operand_value, print_displacement): Likewise. * m68k-dis.c (print_base, print_indexed): Likewise. * ns32k-dis.c (print_insn_arg): Likewise. * ia64-gen.c (_opcode_int64_low, _opcode_int64_high): Delete. (opcode_fprintf_vma): Delete. (print_main_table): Use PRIx64 to print opcode. binutils/ * od-macho.c: Replace all uses of printf_vma with bfd_printf_vma. * objcopy.c (copy_object): Don't use sprintf_vma. Instead use PRIx64 to print bfd_vma values. (copy_main): Likewise. * readelf.c (CHECK_ENTSIZE_VALUES): Likewise. (dynamic_section_mips_val): Likewise. (print_vma): Don't use printf_vma. Instead use PRIx64 to print bfd_vma values. (dump_ia64_vms_dynamic_fixups): Likewise. (process_version_sections): Likewise. * rddbg.c (stab_context): Likewise. gas/ * config/tc-i386.c (offset_in_range): Don't use sprintf_vma. Instead use PRIx64 to print bfd_vma values. (md_assemble): Likewise. * config/tc-mips.c (load_register, macro): Likewise. * messages.c (as_internal_value_out_of_range): Likewise. * read.c (emit_expr_with_reloc): Likewise. * config/tc-ia64.c (note_register_values): Don't use fprintf_vma. Instead use PRIx64 to print bfd_vma values. (print_dependency): Likewise. * listing.c (list_symbol_table): Use bfd_sprintf_vma. * symbols.c (print_symbol_value_1): Use %p to print pointers. (print_binary): Likewise. (print_expr_1): Use PRIx64 to print bfd_vma values. * write.c (print_fixup): Use %p to print pointers. Don't use fprintf_vma. * testsuite/gas/all/overflow.l: Update expected output. * testsuite/gas/m68k/mcf-mov3q.d: Likewise. * testsuite/gas/m68k/operands.d: Likewise. * testsuite/gas/s12z/truncated.d: Likewise. ld/ * deffilep.y (def_file_print): Don't use fprintf_vma. Instead use PRIx64 to print bfd_vma values. * emultempl/armelf.em (gld${EMULATION_NAME}_finish): Don't use sprintf_vma. Instead use PRIx64 to print bfd_vma values. * emultempl/pe.em (gld${EMULATION_NAME}_finish): Likewise. * ldlang.c (lang_map): Use %V to print region origin. (lang_one_common): Don't use sprintf_vma. * ldmisc.c (vfinfo): Don't use fprintf_vma or sprintf_vma. * pe-dll.c (pe_dll_generate_def_file): Likewise. gdb/ * remote.c (remote_target::trace_set_readonly_regions): Replace uses of sprintf_vma with bfd_sprintf_vma.
2022-07-29libopcodes/aarch64: add support for disassembler stylingAndrew Burgess1-1/+44
This commit enables disassembler styling for AArch64. After this commit it is possible to have objdump style AArch64 disassembler output (using --disassembler-color option). Once the required GDB patches are merged, GDB will also style the disassembler output. The changes to support styling are mostly split between two files opcodes/aarch64-dis.c and opcodes/aarch64-opc.c. The entry point for the AArch64 disassembler can be found in aarch64-dis.c, this file handles printing the instruction mnemonics, and assembler directives (e.g. '.byte', '.word', etc). Some operands, mostly relating to assembler directives are also printed from this file. This commit changes all of this to pass through suitable styling information. However, for most "normal" instructions, the instruction operands are printed using a two step process. From aarch64-dis.c, in the print_operands function, the function aarch64_print_operand is called, this function is in aarch64-opc.c, and converts an instruction operand into a string. Then, back in print_operands (aarch64-dis.c), the operand string is printed. Unfortunately, the string returned by aarch64_print_operand can be quite complex, it will include syntax elements, like '[' and ']', in addition to register names and immediate values. In some cases, a single operand will expand into what will appear (to the user) as multiple operands separated with a ','. This makes the task of styling more complex, all these different components need to by styled differently, so we need to get the styling information out of aarch64_print_operand in some way. The solution that I propose here is similar to the solution that I used for the i386 disassembler. Currently, aarch64_print_operand uses snprintf to write the operand text into a buffer provided by the caller. What I propose is that we pass an extra argument to the aarch64_print_operand function, this argument will be a structure, the structure contains a callback function and some state. When aarch64_print_operand needs to format part of its output this can be done by using the callback function within the new structure, this callback returns a string with special embedded markers that indicate which mode should be used for each piece of text. Back in aarch64-dis.c we can spot these special style markers and use this to split the disassembler output up and apply the correct style to each piece. To make aarch64-opc.c clearer a series of new static functions have been added, e.g. 'style_reg', 'style_imm', etc. Each of these functions formats a piece of text in a different style, 'register' and 'immediate' in this case. Here's an example taken from aarch64-opc.c of the new functions in use: snprintf (buf, size, "[%s, %s]!", style_reg (styler, base), style_imm (styler, "#%d", opnd->addr.offset.imm)); The aarch64_print_operand function is also called from the assembler to aid in printing diagnostic messages. Right now I have no plans to add styling to the assembler output, and so, the callback function used in the assembler ignores the styling information and just returns an plain string. I've used the source files in gas/testsuite/gas/aarch64/ for testing, and have manually gone through and checked that the styling looks reasonable, however, I'm not an AArch64 expert, so it is possible that the odd piece is styled incorrectly. Please point out any mistakes I've made. With objdump disassembler color turned off, there should be no change in the output after this commit.
2022-07-29Arm64: re-work PR gas/27217 fixJan Beulich2-46/+23
The original approach has resulted in anomalies when . is involved in an operand of one of the affected insns. We cannot leave . unresolved, or else it'll be resolved at the end of assembly, then pointing to the address of a section rather than at the insn of interest. Undo part of the original change and instead check whether a relocation cannot be omitted in md_apply_fix(). By resolving the expressions again, equates (see the adjustment of the respective testcase) will now be evaluated, and hence relocations against absolute addresses be emitted. This ought to be okay as long as the equates aren't global (and hence can't be overridden). If a need for such arises, quite likely the only way to address this would be to invent yet another expression evaluation mode, leaving everything _except_ . un-evaluated. There's a further anomaly in how transitive equates are handled. In .set x, 0x12345678 .eqv bar, x foo: adrp x0, x add x0, x0, :lo12:x adrp x0, bar add x0, x0, :lo12:bar the first two relocations are now against *ABS*:0x12345678 (as said above), whereas the latter two relocations would be against x. (Before the change here, the first two relocations are against x and the latter two against bar.) But this is an issue seen elsewhere as well, and would likely require adjustments in the target-independent parts of the assembler instead of trying to hack around this for every target.
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