Age | Commit message (Collapse) | Author | Files | Lines |
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* config/tc-rx.c (rx_op): Correct handling of integer bignums.
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This commit adds a new extended menmonic for "sync 0" (same as "sync").
The ISA documentation doesn't explicitly mention hwsync as an extended
mnemonic (yet), but it does mention "heavyweight sync" and "hwsync" as
the operation that gets performed when the sync's L field is 0.
This is only enabled for POWER4 and later.
opcodes/
* ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
gas/testsuite/
* gas/ppc/a2.d: Fixup test case due to new extended mnemonic.
* gas/ppc/power4.s <hwsync, lwsync, ptesync, sync>: Add tests.
* gas/ppc/power4.d: Likewise.
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* config/tc-h8300.c (md_section_align): Fix compile time warning
about left shifting a negative value.
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2015-06-04 Renlin Li <renlin.li@arm.com>
* config/tc-arm.c (arm_init_frag): Use frag's thumb_mode information
when available.
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2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
* gas/arm/armv8-a+rdma.d: New.
* gas/arm/armv8-a+rdma.s: New.
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2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
gas/
* config/tc-arm.c (arm_archs): Add "armv8.1-a".
* doc/c-arm.texi (ARM Options, -march): Add "armv8.1-a".
* NEWS: Mention ARMv8.1 support.
include/opcode/
* arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
(ARM_ARCH_V8_1A): New.
(ARM_ARCH_V8_1A_FP): New.
(ARM_ARCH_V8_1A_SIMD): New.
(ARM_ARCH_V8_1A_CRYPTOV1): New.
(ARM_FEATURE_CORE): New.
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2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
gas/
* config/tc-aarch64.c (aarch64_features): Add "rdma".
* doc/c-aarch64.texi (AArch64 Extensions): Add "rdma".
gas/testsuite/
* rdma-directive.d: New.
* rdma.d: New.
* rdma.s: New.
include/opcode/
* aarch64.h (AARCH64_FEATURE_RDMA): New.
opcode/
* aarch64-tbl.h (aarch64_feature_rdma): New.
(RDMA): New.
(aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
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2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
include/
* aarch64.h (AARCH64_FEATURE_LOR): New.
opcodes/
* aarch64-tbl.h (aarch64_feature_lor): New.
(LOR): New.
(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
"stllrb", "stllrh".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas/
* config/tc-aarch64.c (aarch64_features): Add "lor".
* doc/c-aarch64.c (Aarch64 Extensions): Add "lor" to list of
architecture extensions.
gas/testsuite/
* lor-directive.d: New.
* lor.d: New.
* lor.s: New.
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2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
gas/
* config/tc-aarch64.c (parse_sys_reg): New parameter. Check
target support. Fix whitespace.
(parse_operands): Update for parse_sys_reg changes.
(aarch64_features): Add "pan".
* doc/c-aarch64.texi (Aarch64 Extensions): Add "pan".
gas/testsuite/
* pan-directive.d: New.
* pan.d: New.
* pan.s: New
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This patch add BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14 support in Gas.
The relocation modifier
===
:gotpage_lo14:symbol
2015-06-01 Jiong.Wang <jiong.wang@arm.com>
bfd/
* reloc.c (BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14): New entry.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for
BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14.
gas/
* config/tc-aarch64.c (reloc_table): New relocation modifiers.
(md_apply_fix): Support BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14.
(aarch64_force_relocation): Ditto.
gas/testsuite/
* gas/aarch64/ilp32-basic.s: New testcase.
* gas/aarch64/ilp32-basic.d: Ditto.
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2015-06-01 Jiong.Wang <jiong.wang@arm.com>
bfd/
* reloc.c (BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15): New entry.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for
BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15.
gas/
* config/tc-aarch64.c (reloc_table): New relocation modifiers.
(md_apply_fix): Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15.
(aarch64_force_relocation): Ditto.
gas/testsuite/
* gas/aarch64/reloc-insn.s: New testcase.
* gas/aarch64/reloc-insn.d: Ditto.
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As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so disassembler should produce output accordingly.
gas/testsuite/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512f.s: Adjust operand order for Intel syntax
vcvt{,u}si2ss.
* gas/i386/x86-64-avx512f.s: Adjust operand order for Intel
syntax vcvt{,u}si2s{d,s}.
opcodes/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (print_insn): Swap rounding mode specifier and
general purpose register in Intel mode.
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As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so gas should accept such input. As the brojen code got
released already we sadly will need to continue to also accept the
badly ordered operands.
gas/testsuite/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512f-intel.d: Adjust expectations on operand order.
* gas/i386/evex-lig256-intel.d: Likewise.
* gas/i386/evex-lig512-intel.d: Likewise.
* gas/i386/x86-64-avx512f-intel.d: Likewise.
* gas/i386/x86-64-evex-lig256-intel.d: Likewise.
* gas/i386/x86-64-evex-lig512-intel.d: Likewise.
opcodes/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
* i386-tbl.h: Regenerate.
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The specification for the Compact EH format is available at:
https://github.com/MentorEmbedded/cxx-abi/blob/master/MIPSCompactEH.pdf
2015-05-28 Catherine Moore <clm@codesourcery.com>
Bernd Schmidt <bernds@codesourcery.com>
Paul Brook <paul@codesourcery.com>
bfd/
* bfd-in2.h: Regenerated.
* elf-bfd.h (DWARF2_EH_HDR, COMPACT_EH_HDR): Define.
(COMPACT_EH_CANT_UNWIND_OPCODE): Define.
(dwarf_eh_frame_hdr_info): Move dwarf-specific fields from
eh_frame_hdr_info.
(compact_eh_frame_hdr_info): Declare.
(eh_frame_hdr_info): Redeclare with union for dwarf-specific
fields and compact-eh fields.
(elf_backend_data): Add cant_unwind_opcode and compact_eh_encoding.
(bfd_elf_section_data): Add eh_frame_entry_field.
(elf_section_eh_frame_entry): Define.
(bfd_elf_parse_eh_frame_entries): Declare.
(_bfd_elf_parse_eh_frame_entry): Declare.
(_bfd_elf_end_eh_frame_parsing): Declare.
(_bfd_elf_write_section_eh_frame_entry): Declare.
(_bfd_elf_eh_frame_entry_present): Declare.
(_bfd_elf_section_for_symbol): Declare.
* elf-eh-frame.c (bfd_elf_discard_eh_frame_entry): New function.
(bfd_elf_record_eh_frame_entry): New function.
(_bfd_elf_parse_eh_frame_entry): New function.
(_bfd_elf_parse_eh_frame): Update hdr_info field references.
(cmp_eh_frame_hdr): New function.
(add_eh_frame_hdr_terminator): New function.
(_bfd_elf_end_eh_frame_parsing): New function.
(find_merged_cie): Update hdr_info field references.
(_bfd_elf_discard_section_eh_frame): Likewise.
(_bfd_elf_discard_section_eh_frame_hdr): Add Compact EH support.
(_bfd_elf_eh_frame_entry_present): New function.
(_bfd_elf_maybe_strip_eh_frame_hdr): Add Compact EH support.
(_bfd_elf_write_section_eh_frame_entry): New function.
(_bfd_elf_write_section_eh_frame): Update hdr_info field references.
(_bfd_elf_fixup_eh_frame_hdr): New function.
(write_compact_eh_frame_hdr): New function.
(write_dwarf_eh_frame_hdr): New function.
(_bfd_elf_write_section_eh_frame_hdr): Add Compact EH support.
* elflink.c (_bfd_elf_section_for_symbol): New function.
(elf_section_ignore_discarded_relocs): Add Compact EH support.
(elf_link_input_bfd): Likewise.
(bfd_elf_final_link): Likewise.
(_bfd_elf_gc_mark): Likewise.
(bfd_elf_parse_eh_frame_entries): New function.
(bfd_elf_gc_sections): Add Compact EH support.
(bfd_elf_discard_info): Likewise.
* elfxx-mips.c: Include dwarf2.h.
(_bfd_mips_elf_compact_eh_encoding): New function.
(_bfd_mips_elf_cant_unwind_opcode): New function.
* elfxx-mips.h (_bfd_mips_elf_compact_eh_encoding): Declare.
(_bfd_mips_elf_cant_unwind_opcode): Declare.
(elf_backend_compact_eh_encoding): Define.
(elf_backend_cant_unwind_opcode): Define.
* elfxx-target.h (elf_backend_compact_eh_encoding): Provide default.
(elf_backend_cant_unwind_opcode): Provide default.
(elf_backend_data elfNN_bed): Add elf_backend_compact_eh_encoding and
elf_backend_cant_unwind_opcode.
* section.c (SEC_INFO_TYPE_EH_FRAME_ENTRY): Add definition.
gas/
* config/tc-alpha.c (all_cfi_sections): Declare.
(s_alpha_ent): Initialize all_cfi_sections.
(alpha_elf_md_end): Invoke cfi_set_sections.
* config/tc-mips.c (md_apply_fix): Handle BFD_RELOC_NONE.
(s_ehword): Use BFD_RELOC_32_PCREL.
(mips_fix_adjustable): Handle BFD_RELOC_32_PCREL.
(mips_cfi_reloc_for_encoding): New function.
* tc-mips.h (DWARF2_FDE_RELOC_SIZE): Redefine.
(DWARF2_FDE_RELOC_ENCODING): Define.
(tc_cfi_reloc_for_encoding): Define.
(mips_cfi_reloc_for_encoding): Define.
(tc_compact_eh_opcode_stop): Define.
(tc_compact_eh_opcode_pad): Define.
* doc/as.texinfo: Document Compact EH extensions.
* doc/internals.texi: Likewise.
* dw2gencfi.c (EH_FRAME_LINKONCE): Redefine.
(tc_cfi_reloc_for_encoding): Provide default.
(compact_eh): Declare.
(emit_expr_encoded): New function.
(get_debugseg_name): Add Compact EH support.
(alloc_debugseg_item): Likewise.
(cfi_set_sections): New function.
(dot_cfi_fde_data): New function.
(dot_cfi_personality_id): New function.
(dot_cfi_inline_lsda): New function.
(cfi_pseudo_table): Add cfi_fde_data, cfi_personality_id,
and cfi_inline_lsda.
(dot_cfi_personality): Add Compact EH support.
(dot_cfi_lsda): Likewise.
(dot_cfi_sections): Likewise.
(dot_cfi_startproc): Likewise.
(get_cfi_seg): Likewise.
(output_compact_unwind_data): New function.
(output_cfi_insn): Add Compact EH support.
(output_cie): Likewise.
(output_fde): Likewise.
(cfi_finish): Likewise.
(cfi_emit_eh_header): New function.
(output_eh_header): New function.
* dw2gencfi.h (cfi_set_sections): Declare.
(SUPPORT_COMPACT_EH): Define.
(MULTIPLE_FRAME_SECTIONS): Define.
New enumeration to describe the Compact EH header format.
(fde_entry): Add new fields personality_id, eh_header_type, eh_data_size,
eh_data, eh_loc and sections.
(CFI_EMIT_eh_frame, CFI_EMIT_debug_frame, CFI_EMIT_target,
CFI_EMIT_eh_frame_compact): Define.
2015-05-22 Catherine Moore <clm@codesourcery.com>
Bernd Schmidt <bernds@codesourcery.com>
gas/testsuite/
* gas/mips/mips.exp: Run new tests.
* gas/mips/compact-eh-1.s: New file.
* gas/mips/compact-eh-2.s: New file.
* gas/mips/compact-eh-3.s: New file.
* gas/mips/compact-eh-4.s: New file.
* gas/mips/compact-eh-5.s: New file.
* gas/mips/compact-eh-6.s: New file.
* gas/mips/compact-eh-7.s: New file.
* gas/mips/compact-eh-eb-1.d: New file.
* gas/mips/compact-eh-eb-2.d: New file.
* gas/mips/compact-eh-eb-3.d: New file.
* gas/mips/compact-eh-eb-4.d: New file.
* gas/mips/compact-eh-eb-5.d: New file.
* gas/mips/compact-eh-eb-6.d: New file.
* gas/mips/compact-eh-eb-7.d: New file.
* gas/mips/compact-eh-el-1.d: New file.
* gas/mips/compact-eh-el-2.d: New file.
* gas/mips/compact-eh-el-3.d: New file.
* gas/mips/compact-eh-el-4.d: New file.
* gas/mips/compact-eh-el-5.d: New file.
* gas/mips/compact-eh-el-6.d: New file.
* gas/mips/compact-eh-el-7.d: New file.
* gas/mips/compact-eh-err1.l: New file.
* gas/mips/compact-eh-err1.s: New file.
* gas/mips/compact-eh-err2.l: New file.
* gas/mips/compact-eh-err2.s: New file.
2015-05-22 Catherine Moore <clm@codesourcery.com>
include/
* bfdlink.h: Rename eh_frame_hdr to eh_frame_hdr_type.
2015-05-22 Catherine Moore <clm@codesourcery.com>
Paul Brook <paul@codesourcery.com>
ld/
* emultempl/elf32.em (gld${EMULATION_NAME}_after_open):
Add Compact EH support.
* scripttempl/elf.sc: Handle .eh_frame_entry and .gnu_extab
sections.
2015-05-22 Catherine Moore <clm@codesourcery.com>
ld/testsuite/
* ld-mips-elf/compact-eh.ld: New linker script.
* ld-mips-elf/compact-eh1.d: New.
* ld-mips-elf/compact-eh1.s: New.
* ld-mips-elf/compact-eh1a.s: New.
* ld-mips-elf/compact-eh1b.s: New.
* ld-mips-elf/compact-eh2.d: New.
* ld-mips-elf/compact-eh2.s: New.
* ld-mips-elf/compact-eh3.d: New.
* ld-mips-elf/compact-eh3.s: New.
* ld-mips-elf/compact-eh3a.s: New.
* ld-mips-elf/compact-eh4.d: New.
* ld-mips-elf/compact-eh5.d: New.
* ld-mips-elf/compact-eh6.d: New.
* ld-mips-elf/mips-elf.exp: Run new tests.
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When --text-section-literals is used and code in the .init or .fini
emits literal in the absence of .literal_position, xtensa_move_literals
segfaults.
Check that search_frag is non-NULL in the xtensa_move_literals and
report error otherwise.
2015-05-26 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (xtensa_move_literals): Check that
search_frag is non-NULL. Report error if literal frag is not
found.
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PR gas/18446
* read.c (output_big_sleb128): Use U suffix to prevent compile
time warning.
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2015-05-19 Jiong. Wang <jiong.wang@arm.com>
gas/
* config/tc-aarch64.c (process_movw_reloc_info): Sort relocation case labels
alphabetically.
(md_apply_fix): Ditto.
(aarch64_force_relocation): Ditto.
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AMD64 spec and Intel64 spec differ in direct unconditional branches in
64-bit mode. AMD64 supports direct unconditional branches with 16-bit
offset via the data size prefix, which truncates RIP to 16 bits, while
the data size prefix is ignored by Intel64.
This patch adds -mamd64/-mintel64 option to x86-64 assembler and
-Mamd64/-Mintel64 option to x86-64 disassembler. The most permissive
ISA, which is AMD64, is the default.
GDB can add an option, similar to
(gdb) help set disassembly-flavor
Set the disassembly flavor.
The valid values are "att" and "intel", and the default value is "att".
to select which ISA to disassemble.
binutils/
PR binutis/18386
* doc/binutils.texi: Document -Mamd64 and -Mintel64.
gas/
PR binutis/18386
* config/tc-i386.c (OPTION_MAMD64): New.
(OPTION_MINTEL64): Likewise.
(md_longopts): Add -mamd64 and -mintel64.
(md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64.
(md_show_usage): Add -mamd64 and -mintel64.
* doc/c-i386.texi: Document -mamd64 and -mintel64.
gas/testsuite/
PR binutis/18386
* gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3.
* gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump.
* gas/i386/ilp32/x86-64-branch.d: Likewise.
* gas/i386/x86-64-branch-2.d: New file.
* gas/i386/x86-64-branch-2.s: Likewise.
* gas/i386/x86-64-branch-3.l: Likewise.
* gas/i386/x86-64-branch-3.s: Likewise.
ld/testsuite/
PR binutis/18386
* ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump.
* ld-x86-64/tlspic.dd: Likewise.
* ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to
objdump for tlspic.dd and tlsgdesc.dd.
opcodes/
PR binutis/18386
* i386-dis.c: Add comments for '@'.
(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
(enum x86_64_isa): New.
(isa64): Likewise.
(print_i386_disassembler_options): Add amd64 and intel64.
(print_insn): Handle amd64 and intel64.
(putop): Handle '@'.
(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
* i386-opc.h (AMD64): New.
(CpuIntel64): Likewise.
(i386_cpu_flags): Add cpuamd64 and cpuintel64.
* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
Mark direct call/jmp without Disp16|Disp32 as Intel64.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
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This patch adds -mshared option to x86 ELF assembler. By default,
assembler will optimize out non-PLT relocations against defined non-weak
global branch targets with default visibility. The -mshared option tells
the assembler to generate code which may go into a shared library
where all non-weak global branch targets with default visibility can
be preempted. The resulting code is slightly bigger. This option
only affects the handling of branch instructions.
This Linux kernel patch is needed to create a working x86 Linux kernel if
it hasn't been applied:
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index ae6588b..b91a00c 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -339,8 +339,8 @@ early_idt_handlers:
i = i + 1
.endr
-/* This is global to keep gas from relaxing the jumps */
-ENTRY(early_idt_handler)
+/* This is weak to keep gas from relaxing the jumps */
+WEAK(early_idt_handler)
cld
cmpl $2,(%rsp) # X86_TRAP_NMI
--
gas/
* config/tc-i386.c (shared): New.
(OPTION_MSHARED): Likewise.
(elf_symbol_resolved_in_segment_p): Add relocation argument.
Check PLT relocations and shared.
(md_estimate_size_before_relax): Pass fragP->fr_var to
elf_symbol_resolved_in_segment_p.
(md_longopts): Add -mshared.
(md_show_usage): Likewise.
(md_parse_option): Handle OPTION_MSHARED.
* doc/c-i386.texi: Document -mshared.
gas/testsuite/
* gas/i386/i386.exp: Don't run pcrel for ELF targets. Run
pcrel-elf, relax-4 and x86-64-relax-3 for ELF targets.
* gas/i386/pcrel-elf.d: New file.
* gas/i386/relax-4.d: Likewise.
* gas/i386/x86-64-relax-3.d: Likewise.
* gas/i386/relax-3.d: Pass -mshared to assembler. Updated.
* gas/i386/x86-64-relax-2.d: Likewise.
* gas/i386/relax-3.s: Add test for PLT relocation.
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Remove the wait instructions for server processors, since they were never
implemented. Also add the extra operands added to the tlbie and slbia
instructions with ISA 2.06 and ISA 2.05 respectively.
binutils/
* MAINTAINERS: Add myself as PPC maintainer.
opcodes/
* ppc-opc.c (IH) New define.
(powerpc_opcodes) <wait>: Do not enable for POWER7.
<tlbie>: Add RS operand for POWER7.
<slbia>: Add IH operand for POWER6.
gas/testsuite/
* gas/ppc/power4.d: Add a slbia test.
* gas/ppc/power4.s: Likewise.
* gas/ppc/power6.d: Add slbia and tlbie tests.
* gas/ppc/power6.s: Likewise.
* gas/ppc/power7.d: Remove wait tests. Add a tlbie test.
* gas/ppc/power7.s: Likewise.
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In a SHF_COMPRESSED compressed section, the raw compressed data should
begin immediately after the compression header. This patch removes the
extra zlib header from the SHF_COMPRESSED section.
bfd/
* bfd.c (bfd_update_compression_header): Also write the zlib
header if the SHF_COMPRESSED bit cleared..
(bfd_check_compression_header): Return the uncompressed size.
* compress.c (decompress_contents): Don't skip the zlib header.
(bfd_compress_section_contents): Properly handle ELFCOMPRESS_ZLIB,
which doesn't have the zlib header.
(bfd_init_section_decompress_status): Likewise.
(bfd_get_full_section_contents): Updated.
(bfd_is_section_compressed): Likewise.
(bfd_is_section_compressed_with_header): Return the uncompressed
size.
* elf.c (_bfd_elf_make_section_from_shdr): Updated.
* bfd-in2.h: Regenerated.
binutils/
* readelf.c (uncompress_section_contents): Add a parameter for
uncompressed size. Don't check the zlib header.
(load_specific_debug_section): Updated.
binutils/testsuite/
* binutils-all/compress.exp: Replace "$OBJDUMP -s -j .debug_info"
with "$OBJDUMP -W".
* binutils-all/libdw2-compressedgabi.out: Updated.
gas/
2015-05-14 H.J. Lu <hongjiu.lu@intel.com>
* write.c (compress_debug): Don't write the zlib header, which
is handled by bfd_update_compression_header.
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Extra condition 'abs (addr - trampaddr) < J_RANGE / 2' for trampoline
selection results in regressions: when relaxable jump is little longer
than J_RANGE so that single trampoline makes two new jumps, one longer
than J_RANGE / 2 and one shorter, correct trampoline cannot be found.
Drop that condition.
2015-05-13 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (xtensa_relax_frag): Allow trampoline to be
closer than J_RANGE / 2 to jump frag.
gas/testsuite/
* gas/xtensa/trampoline.s: Add regression testcase.
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This reverts commit 573cc2e57db66165b390044338d3a4ad51f36bf8.
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This patch sets the default ELF output format of assembler and linker to
EM_IAMCU when binutils is configured to i?86-*-elfiamcu target.
gas/
* configure.tgt (arch): Set to iamcu for i386-*-elfiamcu target.
* config/tc-i386.c (i386_mach): Support iamcu.
(i386_target_format): Likewise.
ld/
* configure.tgt: Support i[3-7]86-*-elfiamcu target.
ld/testsuite/
* ld-i386/i386.exp (iamcu_tests): Run iamcu-4.
* ld-i386/iamcu-4.d: New file.
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-march=iamcu must be passed to i386 assembler to generate Intel MCU object
file.
gas/
* config/tc-i386.c (cpu_arch): Add iamcu.
(i386_align_code): Handle PROCESSOR_IAMCU.
(i386_arch): Likewise.
(i386_mach): Likewise.
(i386_target_format): Likewise.
(valid_iamcu_cpu_flags): New function.
(check_cpu_arch_compatible): Only allow Intel MCU instructions
when targeting Intel MCU.
(set_cpu_arch): Call valid_iamcu_cpu_flags to check if CPU flags
are valid for Intel MCU.
(md_parse_option): Likewise.
* tc-i386.h (ELF_TARGET_IAMCU_FORMAT): New.
(processor_type): Add PROCESSOR_IAMCU.
* doc/c-i386.texi: Document iamcu.
gas/testsuite/
* gas/i386/i386.exp: Run iamcu-1, iamcu-2, iamcu-3, iamcu-inval-1,
iamcu-inval-2 and iamcu-inval-3.
* gas/i386/iamcu-1.d: New file.
* gas/i386/iamcu-1.s: Likewise.
* gas/i386/iamcu-2.d: Likewise.
* gas/i386/iamcu-2.s: Likewise.
* gas/i386/iamcu-3.d: Likewise.
* gas/i386/iamcu-3.s: Likewise.
* gas/i386/iamcu-inval-1.l: Likewise.
* gas/i386/iamcu-inval-1.s: Likewise.
* gas/i386/iamcu-inval-2.l: Likewise.
* gas/i386/iamcu-inval-2.s: Likewise.
* gas/i386/iamcu-inval-3.l: Likewise.
* gas/i386/iamcu-inval-3.s: Likewise.
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The operand size prefix (0x66) is ignored for 32-bit PC-relative call,
jmp and jcc in 64-bit mode.
gas/testsuite/
PR binutis/18386
* gas/i386/i386.exp: Run x86-64-jump.
* gas/i386/x86-64-branch.d: Updated.
* gas/i386/ilp32/x86-64-branch.d: Likewise.
* gas/i386/x86-64-branch.s: Add tests for the operand size prefix
with call, jmp and jb.
* gas/i386/x86-64-jump.d: New file.
* gas/i386/x86-64-jump.s: Likewise.
ld/testsuite/
PR binutis/18386
* ld-x86-64/tlsgdesc.dd: Updated.
* ld-x86-64/tlspic.dd: Likewise.
opcodes/
PR binutis/18386
* i386-dis.c (X86_64_E8): New.
(X86_64_E9): Likewise.
Update comments on 'T', 'U', 'V'. Add comments for '^'.
(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
(x86_64_table): Add X86_64_E8 and X86_64_E9.
(mod_table): Replace {T|} with ^ on Jcall/Jmp.
(putop): Handle '^'.
(OP_J): Ignore the operand size prefix in 64-bit. Don't check
REX_W.
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form "name = val" is used.
PR gas/18347
* config/tc-arm.h (TC_EQUAL_IN_INSN): Define.
* config/tc-arm.c (arm_tc_equal_in_insn): New function. Move
the symbol name checking code to here from...
(md_undefined_symbo): ... here.
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On ELF target, the assembler normally generates code which can go into a
shared library where non-weak symbols can be preempted. The -mno-shared
option tells the assembler to generate code not for a shared library,
where non-weak symbols won't be preempted. The resulting code is slightly
smaller. This option mainly affects the handling of branch instructions.
gas/
* config/tc-i386.c (no_shared): New.
(OPTION_MNO_SHARED): Likewise.
(elf_symbol_resolved_in_segment_p): Check no_shared.
(md_longopts): Add mno-shared.
(md_parse_option): Handle OPTION_MNO_SHARED.
(md_show_usage): Add -mno-shared.
* doc/c-i386.texi: Document -mno-shared.
gas/testsuite/
* gas/i386/i386.exp: Run relax-4 and x86-64-relax-3.
* gas/i386/relax-4.d: New file.
* gas/i386/x86-64-relax-3.d: Likewise.
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Branches to global non-weak symbols defined in the same segment with
non-default visibility can be optimized the same way as branches to
local symbols.
gas/
* config/tc-i386.c (elf_symbol_resolved_in_segment_p): New.
(md_estimate_size_before_relax): Use it.
gas/testsuite/
* gas/i386/i386.exp: Run relax-3 and x86-64-relax-2.
* gas/i386/relax-3.d: New file.
* gas/i386/relax-3.s: Likewise.
* gas/i386/x86-64-relax-2.d: Likewise.
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gas/ChangeLog:
2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Typo in comment fixed.
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gas/ChangeLog:
2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com>
* gas/sparc/natural-32.d: Test ldn, ldna, stn, stna, slln, srln,
sran, casn, casna and clrn.
* gas/sparc/natural-32.s: Likewise.
* gas/sparc/natural.s: Likewise.
* gas/sparc/natural.d: Likewise.
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gas/ChangeLog:
2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Support the %ncc "natural"
condition codes
* doc/c-sparc.texi (Sparc-Regs): Document %ncc.
gas/testsuite/ChangeLog:
2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com>
* gas/sparc/natural.s: New file.
* gas/sparc/natural-32.s: Likewise.
* gas/sparc/natural.d: Likewise.
* gas/sparc/natural-32.d: Likewise.
* gas/sparc/sparc.exp (sparc_elf_setup): Run the tests natural and
natural-32.
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on some targets.
* doc/as.texinfo (Dollar Local Labels): Note that these are only
supported on some targets.
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2015-05-06 Renlin Li <renlin.li@arm.com>
gas/
* config/tc-aarch64.c (mapping_state): Recording alignment before exit.
gas/testsuite/
* gas/aarch64/codealign_1.s: New.
* gas/aarch64/codealign_1.d: New.
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2015-05-05 Renlin Li <renlin.li@arm.com>
gas/
* config/tc-aarch64.c (aarch64_init_frag): Always generate mapping symbols.
gas/testsuite/
* gas/aarch64/mapping_5.d: New.
* gas/aarch64/mapping_5.s: New.
* gas/aarch64/mapping_6.d: New.
* gas/aarch64/mapping_6.s: New.
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data into either low or high memory regions.
gas * config/tc-msp430.c (MAX_OP_LEN): Increase to 4096.
(msp430_make_init_symbols): New function.
(msp430_section): Call it.
(msp430_frob_section): Likewise.
ld * emulparams/msp430elf.sh (TEMPLATE_NAME): Change to msp430.
* scripttempl/msp430.sc (.text): Add .lower.text and .either.text.
(.data): Add .lower.data and .either.data.
(.bss): Add .lower.bss and .either.bss.
(.rodata): Add .lower.rodata and .either.rodata.
* emultempl/msp430.em: New file. Implements a new orphan
placement algorithm that divides sections between lower and upper
memory regions.
* Makefile.am (emsp430elf.c): Depend upon msp430.em.
*emsp430X.c): Likewise.
* Makefine.in: Regenerate.
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Currently every fixup in the current segment is checked when relaxing
trampoline frag. This is very expensive. Make a searchable array of
fixups pointing at potentially oversized jumps at the beginning of every
relaxation pass and only check subset of this cache in the reach of
single jump from the trampoline frag currently being relaxed.
Original profile:
% time self children called name
-----------------------------------------
370.16 593.38 12283048/12283048 relax_segment
98.4 370.16 593.38 12283048 xtensa_relax_frag
58.91 269.26 2691463834/2699602236 xtensa_insnbuf_from_chars
68.35 68.17 811266668/813338977 S_GET_VALUE
36.85 29.51 2684369246/2685538060 xtensa_opcode_decode
28.34 8.84 2684369246/2685538060 xtensa_format_get_slot
12.39 5.94 2691463834/2699775044 xtensa_format_decode
0.03 4.60 4101109/4101109 relax_frag_for_align
0.18 1.76 994617/994617 relax_frag_immed
0.07 0.09 24556277/24851220 new_logical_line
0.06 0.00 12283048/14067410 as_where
0.04 0.00 7094588/15460506 xtensa_format_num_slots
0.00 0.00 1/712477 xtensa_insnbuf_alloc
-----------------------------------------
Same data, after optimization:
% time self children called name
-----------------------------------------
0.51 7.47 12283048/12283048 relax_segment
58.0 0.51 7.47 12283048 xtensa_relax_frag
0.02 4.08 4101109/4101109 relax_frag_for_align
0.18 1.39 994617/994617 relax_frag_immed
0.01 0.98 555/555 xtensa_cache_relaxable_fixups
0.21 0.25 7094588/16693271 xtensa_insnbuf_from_chars
0.06 0.12 24556277/24851220 new_logical_line
0.06 0.00 7094588/15460506 xtensa_format_num_slots
0.02 0.04 7094588/16866079 xtensa_format_decode
0.05 0.00 12283048/14067410 as_where
0.00 0.00 1/712477 xtensa_insnbuf_alloc
0.00 0.00 93808/93808 xtensa_find_first_cached_fixup
-----------------------------------------
2015-05-02 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (cached_fixupS, fixup_cacheS): New typedefs.
(struct cached_fixup, struct fixup_cache): New structures.
(fixup_order, xtensa_make_cached_fixup),
(xtensa_realloc_fixup_cache, xtensa_cache_relaxable_fixups),
(xtensa_find_first_cached_fixup, xtensa_delete_cached_fixup),
(xtensa_add_cached_fixup): New functions.
(xtensa_relax_frag): Cache fixups pointing at potentially
oversized jumps at the beginning of every relaxation pass. Only
check subset of this cache in the reach of single jump from the
trampoline frag currently being relaxed.
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* config/rl78-parse.y (MULU): Remove ISA_G14.
(MULH, DIVHU, DIVWU, MACHI, MACH): Update error strings.
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This x86 assembler patch:
https://sourceware.org/ml/binutils/2001-11/msg00344.html
generates a .note section for .arch directive so that GDB can tell which
architecture an i386 binary belongs:
https://sourceware.org/ml/binutils/2001-11/msg00271.html
However, x86 assembly code can have any instructions. A .note section
doesn't help. This patch removes it.
gas/
* config/tc-i386.c (i386_elf_emit_arch_note): Removed.
* config/tc-i386.h (md_end): Likewise.
(i386_elf_emit_arch_note): Likewise.
gas/testsuite/
* gas/i386/i386.exp: Run note.
* gas/i386/note.d: New file.
* gas/i386/note.s: Likewise.
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bfd/
* config.bfd: Support i[3-7]86-*-elf*.
gas/
* configure.tgt: Support i386-*-elf*.
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[gas]
* config/rl78-defs.h (rl78_isa_g10): New.
(rl78_isa_g13): New.
(rl78_isa_g14): New.
* config/rl78-parse.y (ISA_G10): New.
(ISA_G13): New.
(ISA_G14): New.
(MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them.
* config/tc-rl78.c (rl78_isa_g10): New.
(rl78_isa_g13): New.
(rl78_isa_g14): New.
[gdb]
* rl78-tdep.c (rl78_analyze_prologue): Pass RL78_ISA_DEFAULT to
rl78_decode_opcode
[include]
* dis-asm.h (print_insn_rl78_g10): New.
(print_insn_rl78_g13): New.
(print_insn_rl78_g14): New.
(rl78_get_disassembler): New.
* opcode/rl78.h (RL78_Dis_Isa): New.
(rl78_decode_opcode): Add ISA parameter.
[opcodes]
* disassemble.c (disassembler): Choose suitable disassembler based
on E_ABI.
* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
it to decode mul/div insns.
* rl78-decode.c: Regenerate.
* rl78-dis.c (print_insn_rl78): Rename to...
(print_insn_rl78_common): ...this, take ISA parameter.
(print_insn_rl78): New.
(print_insn_rl78_g10): New.
(print_insn_rl78_g13): New.
(print_insn_rl78_g14): New.
(rl78_get_disassembler): New.
[sim]
* rl78/cpu.c (g14_multiply): New.
* rl78/cpu.h (g14_multiply): New.
* rl78/load.c (rl78_load): Decode ISA completely.
* rl78/main.c (main): Expand -M to include other ISAs.
* rl78/rl78.c (decode_opcode): Decode based on ISA.
* rl78/trace.c (rl78_disasm_fn): New.
(sim_disasm_init): Reset it.
(sim_disasm_one): Get correct disassembler for ISA.
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* config/tc-i386.c (i386_target_format): Use "else if" on
cpu_arch_isa.
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PR gas/18347
gas * config/tc-arm.c (md_undefined_symbol): Issue a warning message
(if enabled) when the user creates a symbol with the same name as
an ARM instruction.
(flag_warn_syms): New static variable.
(arm_opts): Add mwarn-syms and mno-warn-syms.
* doc/c-arm.texi (ARM Options): Document the -m[no-]warn-syms
options.
tests * gas/arm/pr18347.s: New file: Test case.
* gas/arm/pr18347.l: New file: Expected assembler output.
* gas/arm/pr18347.d: New file: Test driver.
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PR gas/18353
* doc/as.texinfo (Zero): Add documentation of the .zero pseudo-op.
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gas PR 18256
* config/tc-arm.c (encode_arm_cp_address): Issue an error message
if the operand is neither a register nor a vector.
tests * gas/arm/pr18256.s: New file: Test case.
* gas/arm/pr18256.l: New file: Expected assembler output.
* gas/arm/pr18256.d: New file: Test driver.
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