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2006-05-31Configury changes: update src repository (binutils, gdb, and rda) to useDaniel Jacobowitz7-2708/+534
config/gettext-sister.m4 instead of the old gettext.m4. Regenerate all affected autotools files. Include intl in gdb releases again.
2006-05-30Update Spanish translationNick Clifton2-3949/+4290
2006-05-29 * doc/c-avr.texi: New file.Denis Chertykov1-0/+7
* doc/Makefile.am (CPU_DOCS): Add c-avr.texi * doc/all.texi: Set AVR * doc/as.texinfo: Include c-avr.texi
2006-05-28 * config/bfin-parse.y (check_macfunc): Loose the condition ofJie Zhang2-2/+8
calling check_multiply_halfregs ().
2006-05-26Remove ">>>>>>> 1.2917".H.J. Lu1-1/+0
2006-05-25include/opcodes/Richard Sandiford3-0/+21
* m68k.h (mcf_mask): Define. opcodes/ * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd and fmovem entries. Put register list entries before immediate mask entries. Use "l" rather than "L" in the fmovem entries. * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it out from INFO. (m68k_scan_mask): New function, split out from... (print_insn_m68k): ...here. If no architecture has been set, first try printing an m680x0 instruction, then try a Coldfire one. gas/testsuite/ * gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions. * gas/m68k/mcf-fpu.d: Adjust accordingly.
2006-05-25 * gas/bfin/vector2.s, gas/bfin/vector2.d: Test to ensure (m) is notJie Zhang3-0/+13
thrown away.
2006-05-25 * config/bfin-parse.y (asm_1): Better check and deal withJie Zhang2-38/+44
vector and scalar Multiply 16-Bit Operands instructions.
2006-05-24Add TLS support for hppa-linuxNick Clifton3-2549/+2532
2006-05-24Add support for AVR6 familyNick Clifton4-104/+145
2006-05-23 [ gas/ChangeLog ]Thiemo Seufer11-94/+321
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename. (ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS, ISA_HAS_MXHC1): New macros. (HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments. (mips_cpu_info): Change to use combined ASE/IS_ISA flag. (MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines. (mips_after_parse_args): Change default handling of float register size to account for 32bit code with 64bit FP. Better sanity checking of ISA/ASE/ABI option combinations. (s_mipsset): Support switching of GPR and FPR sizes via .set {g,f}p={32,64,default}. Better sanity checking for .set ASE options. (mips_elf_final_processing): We should record the use of 64bit FP registers in 32bit code but we don't, because ELF header flags are a scarce ressource. (mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef, 24kex, 34kc, 34kf, 34kx, 25kf CPU definitions. (mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA. * doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document missing -march options. Document .set arch=CPU. Move .set smartmips to ASE page. Use @code for .set FOO examples. [ gas/testsuite/Changelog ] * gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d, gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l, gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler output. * gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files, catch assembler warnings.
2006-05-23 * config/tc-bfin.c (bfin_start_line_hook): Bump line countersJie Zhang2-1/+17
if needed.
2006-05-23Commit the missing bits of my last patch.Jie Zhang1-3/+3
2006-05-23 * config/bfin-defs.h (bfin_equals): Remove declaration.Jie Zhang4-47/+9
* config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr". * config/tc-bfin.c (bfin_name_is_register): Remove. (bfin_equals): Remove. * config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1. (bfin_name_is_register): Remove declaration.
2006-05-22* gas/mips/mips32-dsp.l: Fix expected unsigned decoding of -1 in warning ↵Nick Clifton3-145/+151
messages. * gas/mips/mips32-mt.l: Likewise.
2006-05-22Remove ChangeLog entries, since the template files were already up to date.Nick Clifton1-4/+0
2006-05-22Update translation templatesNick Clifton1-0/+4
2006-05-19 * gas/mips/vxworks1-el.d, gas/mips/vxworks1-xgot-el.d: Add littleThiemo Seufer6-2/+187
endian testcases. * gas/mips/vxworks1.d, gas/mips/vxworks1-xgot.d: Build as big endian. * gas/mips/mips.exp: Run new testcases.
2006-05-19 * config/tc-mipc.c (ISA_HAS_ODD_SINGLE_FPR): New define.Thiemo Seufer2-12/+54
(mips_oddfpreg_ok): New function. (mips_ip): Use it. -------------------------------------------------------------------
2006-05-19 * config/tc-mips.h (tc_mips_regname_to_dw2regnum): Declare.Thiemo Seufer3-372/+432
* config/tc-mipc.c (ABI_NEEDS_64BIT_REGS, ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Reformat. (regname, RTYPE_MASK, RTYPE_NUM, RTYPE_FPU, RTYPE_FCC, RTYPE_VEC, RTYPE_GP, RTYPE_CP0, RTYPE_PC, RTYPE_ACC, RTYPE_CCC, RNUM_MASK, RWARN, GENERIC_REGISTER_NUMBERS, FPU_REGISTER_NAMES, FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES, N32N64_SYMBOLIC_REGISTER_NAMES, O32_SYMBOLIC_REGISTER_NAMES, SYMBOLIC_REGISTER_NAMES, MIPS16_SPECIAL_REGISTER_NAMES, MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, reg_names, reg_names_o32, reg_names_n32n64): Define register classes. (reg_lookup): New function, use register classes. (md_begin): Reserve register names in the symbol table. Simplify OBJ_ELF defines. (mips_ip): Fix comment formatting. Handle symbolic COP0 registers. Use reg_lookup. (mips16_ip): Use reg_lookup. (tc_get_register): Likewise. (tc_mips_regname_to_dw2regnum): New function. -------------------------------------------------------------------
2006-05-19 * config/tc-arm.c, config/tc-arm.h (tc_arm_regname_to_dw2regnum):Thiemo Seufer15-15/+32
Un-constify string argument. * config/tc-i386.c, config/tc-i386.h (tc_x86_regname_to_dw2regnum): Likewise. * config/tc-m68k.c, config/tc-m68k.h (tc_m68k_regname_to_dw2regnum): Likewise. * config/tc-ppc.c, config/tc-ppc.h (tc_ppc_regname_to_dw2regnum): Likewise. * config/tc-s390.c, config/tc-s390.h (tc_s390_regname_to_dw2regnum): Likewise. * config/tc-sh.c, config/tc-sh.h (sh_regname_to_dw2regnum): Likewise. * config/tc-sparc.c, config/tc-sparc.h (sparc_regname_to_dw2regnum): Likewise. -------------------------------------------------------------------
2006-05-19 * gas/config/tc-m68k.c (m68k_init_arch): Move checking ofNathan Sidwell2-9/+14
cfloat/m68881 to correct architecture before using it.
2006-05-16* config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate constant values.Nick Clifton2-10/+16
2006-05-152006-05-15 Paul Brook <paul@codesourcery.com>Paul Brook2-1/+7
bfd/ * cpu-arm.c (bfd_is_arm_mapping_symbol_name): Rename ... (bfd_is_arm_special_symbol_name): ... to this. Add type argument. Check symbol name is of specified type. * elf32-arm.c (elf32_arm_is_target_special_symbol, arm_elf_find_function, elf32_arm_output_symbol_hook): Use bfd_is_arm_special_symbol_name. * bfd-in.h (BFD_ARM_SPECIAL_SYM_TYPE_MAP, BFD_ARM_SPECIAL_SYM_TYPE_TAG, BFD_ARM_SPECIAL_SYM_TYPE_OTHER, BFD_ARM_SPECIAL_SYM_TYPE_ANY): Define. (bfd_is_arm_mapping_symbol_name): Remove prototype. (bfd_is_arm_special_symbol_name): Add prototype. * bfd-in2.h: Regenerate. gas/ * config/tc-arm.c (arm_adjust_symtab): Use bfd_is_arm_special_symbol_name. ld/testsuite/ * ld-arm/arm-be8.d: New test. * ld-arm/arm-be8.s: New test. * ld-arm/arm-elf.exp: Add arm-be8.
2006-05-15bfd:Bob Wilson2-8/+15
* elf32-xtensa.c (check_loop_aligned): Fix reversed check for undefined opcode. Clean up assertions. (narrow_instruction, widen_instruction): Remove "do_it" parameters. Factor most of the code into separate functions.... (can_narrow_instruction, can_widen_instruction): New. (prev_instr_is_a_loop): New. (compute_ebb_proposed_actions): Combine error handling code for decode errors. Replace call to insn_decode_len with inline code. Use can_narrow_instruction and can_widen_instruction. Handle errors from call to xtensa_opcode_is_loop. (relax_section): Adjust calls to narrow_instruction and widen_instruction. gas: * config/tc-xtensa.c (is_direct_call_opcode, is_branch_jmp_to_next, xg_assemble_vliw_tokens, xtensa_mark_narrow_branches, xtensa_fix_short_loop_frags, is_local_forward_loop, relax_frag_immed): Handle errors from calls to xtensa_opcode_is_* functions.
2006-05-14 [ gas/ChangeLog ]Thiemo Seufer9-1/+190
* config/tc-mips.c (macro_build): Test for currently active mips16 option. (mips16_ip): Reject invalid opcodes. [ opcodes/ChangeLog ] * mips16-opc.c (I1, I32, I64): New shortcut defines. (mips16_opcodes): Change membership of instructions to their lowest baseline ISA. [ gas/testsuite/ChangeLog ] * gas/mips/mips.exp: Run new tests. * gas/mips/mips16e.s, gas/mips/mips16e.d, gas/mips/mips16e-64.s, gas/mips/mips16e-64.d, gas/mips/mips16e-64.l: New tests.
2006-05-11bfd/doc/Carlos O'Donell2-6/+11
2006-05-11 Carlos O'Donell <carlos@codesourcery.com> * bfd.texinfo: Rename "Index" to "BFD Index" gas/ 2006-05-11 Carlos O'Donell <carlos@codesourcery.com> * doc/as.texinfo: Rename "Index" to "AS Index", and "ABORT" to "ABORT (COFF)". ld/ 2006-05-11 Carlos O'Donell <carlos@codesourcery.com> * ld.texinfo: Rename "Index" to "LD Index"
2006-05-112006-05-11 Paul Brook <paul@codesourcery.com>Paul Brook3-11/+207
bfd/ * elf32-arm.c (elf32_arm_reloc_map): Add MOVW and MOVT relocs. (elf32_arm_final_link_relocate): Handle MOVW and MOVT relocs. (elf32_arm_gc_sweep_hook, elf32_arm_check_relocs): Ditto. * reloc.c: Ditto. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * libcoff.h: Regenerate. gas/ * config/tc-arm.c (parse_half): New function. (operand_parse_code): Remove OP_Iffff. Add OP_HALF. (parse_operands): Ditto. (do_mov16): Reject invalid relocations. (do_t_mov16): Ditto. Use Thumb reloc numbers. (insns): Replace Iffff with HALF. (md_apply_fix): Add MOVW and MOVT relocs. (tc_gen_reloc): Ditto. * doc/c-arm.texi: Document relocation operators ld/testsuite/ * ld-arm/arm-elf.exp: Add arm-movwt. * ld-arm/arm-movwt.d: New test. * ld-arm/arm-movwt.s: New test. * ld-arm/arm.ld: Add .far.
2006-05-112006-05-11 Paul Brook <paul@codesourcery.com>Paul Brook5-3/+36
gas/ * config/tc-arm.c (arm_fix_adjustable): Return 0 for function symbols. gas/testsuite/ * gas/arm/local_function.d: New test. * gas/arm/local_function.s: New test.
2006-05-11 [ gas/ChangeLog ]Thiemo Seufer5-8/+13
* config/tc-mips.c (append_insn): Don't check the range of j or jal addresses. [ gas/testsuite/ChangeLog ] * gas/mips/jal-range.l: Don't check the range of j or jal addresses.
2006-05-11Apply fixes to allow arm WinCE toolchain to produce working executables.Nick Clifton2-3/+30
2006-05-092006-05-09 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-8/+12
* gas/i386/x86-64-gidt.d: Adjusted.
2006-05-09gas/testsuite/H.J. Lu4-0/+39
2006-05-09 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run x86-64-gidt. * gas/i386/x86-64-gidt.d: New file. * gas/i386/x86-64-gidt.s: Likewise. opcodes/ 2006-05-09 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (grps): Update sgdt/sidt for 64bit.
2006-05-09Revised test (that is not O(n2)) for checking for orphaned cloned symbolsNick Clifton1-11/+6
2006-05-09 [ gas/ChangeLog ]Thiemo Seufer4-5/+15
* config/tc-mips.c (append_insn): Only warn about an out-of-range j or jal address. [ gas/testsuite/ChangeLog ] * gas/mips/jal-range.l: Only warn about an out-of-range j or jal address.
2006-05-09* config/tc-arm.c (arm_fix_adjustable): For COFF, convert fixups againstNick Clifton2-6/+30
symbols which are not going to be placed into the symbol table. * coffcode.h (coff_write_relocs): Produce an error message if a an out-of-range symbol index is detected in a reloc.
2006-05-09 * expr.c (operand): Remove `if (0 && ..)' statement andBen Elliston3-14/+9
subsequently unused target_op label. Collapse `if (1 || ..)' statement. * app.c (do_scrub_chars): Remove unused case 0, as it is handled separately above the switch.
2006-05-08 * gas/mips/mips32.s, gas/mips/mips32.d: Extend testcase to checkThiemo Seufer3-16/+37
larger offset arguments for cache instructions.
2006-05-08 PR gas/2623bNick Clifton2-1/+6
* config/tc-msp430.c (line_separator_character): Define as |.
2006-05-08 [ gas/ChangeLog ]Thiemo Seufer8-4/+145
* config/tc-mips.c (mips_set_options): Add ase_smartmips flag. (mips_opts): Likewise. (file_ase_smartmips): New variable. (ISA_HAS_ROR): SmartMIPS implements rotate instructions. (macro_build): Handle SmartMIPS instructions. (mips_ip): Likewise. (md_longopts): Add argument handling for smartmips. (md_parse_options, mips_after_parse_args): Likewise. (s_mipsset): Add .set smartmips support. (md_show_usage): Document -msmartmips/-mno-smartmips. * doc/as.texinfo: Document -msmartmips/-mno-smartmips and .set smartmips. * doc/c-mips.texi: Likewise. [ gas/testsuite/ChangeLog ] * gas/mips/smartmips.s, gas/mips/smartmips.d: New smartmips test. * gas/mips/mips.exp: Run smartmips test.
2006-05-07 * write.c (relax_segment): Add pass count arg. Don't error onAlan Modra3-17/+56
negative org/space on first two passes. (relax_seg_info): New struct. (relax_seg, write_object_file): Adjust. * write.h (relax_segment): Update prototype.
2006-05-05 * config/tc-arm.c (parse_vfp_reg_list): Improve register boundsJulian Brown2-8/+60
checking. (do_neon_mov): Enable several VMOV variants for VFP. Add suitable architecture version checks. (insns): Allow overlapping instructions to be used in VFP mode.
2006-05-05 * gas/arm/vfp-neon-overlap.s: New test. Overlapping VFP/NeonJulian Brown6-73/+158
instructions. * gas/arm/vfp-neon-overlap.d: Expected output of above. * gas/arm/vfp1xD.d: Test for fldmx/fstmx. * gas/arm/vfp1xD_t2.d: Likewise. * gas/arm/vfpv3-32drs.d: Likewise.
2006-05-052006-05-05 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-0/+11
PR gas/2598 * config/obj-elf.c (obj_elf_change_section): Allow user specified SHF_ALPHA_GPREL.
2006-05-05* gas/config/tc-avr.h (TC_VALIDATE_FIX): Define. Disable fixups for PMEMNick Clifton2-2/+24
related expressions. * bfd/elf32-avr.c (elf32_avr_relax_delete_bytes): Iterate over all of the bfd's sections for the reloc-addend adjustments.
2006-05-05PR gas/2582Nick Clifton2-2/+35
* dwarf2dbg.c (INSERT_DIR_SEPARATOR): New macro. Handles the insertion of a directory separator character into a string at a given offset. Uses heuristics to decide when to use a backslash character rather than a forward-slash character. (dwarf2_directive_loc): Use the macro. (out_debug_info): Likewise.
2006-05-05 * gas/mips/noreorder.s, gas/mips/noreorder.d: New test forThiemo Seufer4-0/+56
reorder/noreorder corner case. * gas/mips/mips.exp: Run new test. -------------------------------------------------------------------
2006-05-05 [ gas/ChangeLog ]Thiemo Seufer2-0/+16
* config/tc-mips.c (macro_build): Add case 'k' to handle cache instruction. (macro): Add new case M_CACHE_AB. [ opcodes/ChangeLog ] * mips-opc.c: Add macro for cache instruction. [ include/opcode/ChangeLog ] * mips.h (enum): Add macro M_CACHE_AB.
2006-05-04gas/Kazu Hirata7-7/+66
* config/tc-arm.c (opcode_tag): Add OT_cinfix3_deprecated. (opcode_lookup): Issue a warning for opcode with OT_cinfix3_deprecated. Otherwise treat OT_cinfix3_deprecated identical to OT_cinfix3. (TxC3w, TC3w, tC3w): New. (insns): Use tC3w and TC3w for comparison instructions with 's' suffix. gas/testsuite * gas/arm/armv1.d (error-output): New. * gas/arm/armv1.l: New. * gas/arm/thumb32.d (error-output): New. * gas/arm/thumb32.l: New.
2006-05-04[ gas/testsuite/ChangeLog ]Thiemo Seufer3-5/+11
2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> * gas/mips/mips.exp: Run mips32-dsp tests only for mips32r2. * gas/mips/set-arch.d: Adjust according to opcode table changes. [ include/opcode/ChangeLog ] 2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> * mips.h: Add INSN_SMARTMIPS define. [ opcodes/ChangeLog ] 2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> * mips-dis.c (mips_arch_choices): Add smartmips instruction decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to MIPS64R2. * mips-opc.c: fix random typos in comments. (INSN_SMARTMIPS): New defines. (mips_builtin_opcodes): Add paired single support for MIPS32R2. Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd, flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the FP_S and FP_D flags to denote single and double register accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards. Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1 for MIPS32R2. Add SmartMIPS instructions. Add two-argument variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to release 2 ISAs. * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
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