aboutsummaryrefslogtreecommitdiff
path: root/gas
AgeCommit message (Collapse)AuthorFilesLines
2024-06-23aarch64: Enable +cssc for armv8.9-aAndrew Carlotti1-0/+1
FEAT_CSSC is mandatory in the architecture from Armv8.9.
2024-04-03x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4Cui, Lili4-138/+2
APX spec removed KEYLOCKER and SHA promotions from EVEX MAP4. https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html gas/ChangeLog: * NEWS: Mention that remove KEYLOCKER and SHA promotions from EVEX * MAP4. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: Removed KEYLOCKER * and SHA instructions. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Removed KEYLOCKER and SHA instructions. * i386-dis-evex.h: Ditto. * i386-opc.tbl: Ditto. * i386-tbl.h: Regenerated.
2024-03-14aarch64: Remove B16B16, SVE2p1 and SME2p1Andrew Carlotti6-16/+9
Support for these extensions is broken and incomplete in the 2.42 branch, with a number of syntax and opcode bugs. This patch removes the flags and documentation, to avoid any further suggestion that this extension is fully and correctly supported.
2024-02-29aarch64: Fix the 2nd operand in gcsstr and gcssttr instructions.Srinath Parvathaneni3-49/+49
The assembler wrongly expects plain register name instead of memory-form 2nd operand for gcsstr and gcssttr instructions. This patch fixes the issue.
2024-02-15x86: Display -msse-check= default as noneH.J. Lu1-1/+1
Display -msse-check= default as none for "as --help" since its default is none, not warning. PR gas/31389 * config/tc-i386.c (md_show_usage): Change -msse-check= default to none. (cherry picked from commit 7a6a03c499ad899c1d1dd93beccbb62795feb1db)
2024-02-13PowerPC: Add support for Power11 optionsPeter Bergner2-0/+5
binutils/ * doc/binutils.texi (PowerPC -M option): Mention power11 and pwr11. gas/ * config/tc-ppc.c: (md_show_usage): Mention -mpower11 and -mpwr11. * doc/c-ppc.texi: Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power11" and "pwr11" entries. (powerpc_init_dialect): Default to "power11". (cherry picked from commit 4199cf1e152daab0460f08cc7dbd1f727ac3e4cc)
2024-02-10x86-64: Add R_X86_64_CODE_6_GOTTPOFFH.J. Lu3-22/+94
For add %reg1, name@gottpoff(%rip), %reg2 and add name@gottpoff(%rip), %reg1, %reg2 add #define R_X86_64_CODE_6_GOTTPOFF 50 if the instruction starts at 6 bytes before the relocation offset. They are similar to R_X86_64_GOTTPOFF. Linker can covert GOTTPOFF to add $name@tpoff, %reg1, %reg2 Rewrite fx_tcbit, fx_tcbit2 and fx_tcbit3 usage to generate R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX, R_X86_64_CODE_4_GOTPCRELX, R_X86_64_CODE_4_GOTTPOFF, R_X86_64_CODE_4_GOTPC32_TLSDESC and R_X86_64_CODE_6_GOTTPOFF. NB: There is no need to check BFD_RELOC_X86_64_CODE_4_GOTTPOFF in md_assemble since there is only BFD_RELOC_X86_64_GOTTPOFF at this stage, which will be converted to BFD_RELOC_X86_64_CODE_4_GOTTPOFF or BFD_RELOC_X86_64_CODE_6_GOTTPOFF in i386_validate_fix. 5 relocations: #define R_X86_64_CODE_5_GOTPCRELX 46 #define R_X86_64_CODE_5_GOTTPOFF 47 #define R_X86_64_CODE_5_GOTPC32_TLSDESC 48 #define R_X86_64_CODE_6_GOTPCRELX 49 #define R_X86_64_CODE_6_GOTPC32_TLSDESC 51 are added for completeness and they are unused. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. (elf_x86_64_check_tls_transition): Handle R_X86_64_CODE_6_GOTTPOFF. (elf_x86_64_tls_transition): Likewise. (elf_x86_64_scan_relocs): Handle R_X86_64_CODE_6_GOTTPOFF. Issue an error for R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX and R_X86_64_CODE_6_GOTPC32_TLSDESC. (elf_x86_64_relocate_section): Handle R_X86_64_CODE_6_GOTTPOFF. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_5_GOTPCRELX, BFD_RELOC_X86_64_CODE_5_GOTTPOFF, BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC, BFD_RELOC_X86_64_CODE_6_GOTPCRELX, BFD_RELOC_X86_64_CODE_6_GOTTPOFF and BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. elfcpp/ * x86_64.h (R_X86_64_CODE_5_GOTPCRELX): New. (R_X86_64_CODE_5_GOTTPOFF): Likewise. (R_X86_64_CODE_5_GOTPC32_TLSDESC): Likewise. (R_X86_64_CODE_6_GOTPCRELX): Likewise. (R_X86_64_CODE_6_GOTTPOFF): Likewise. (R_X86_64_CODE_6_GOTPC32_TLSDESC): Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. (md_assemble): Don't check BFD_RELOC_X86_64_CODE_4_GOTTPOFF. Allow "add %reg1, foo@gottpoff(%rip), %reg2". (output_disp): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. Rewrite setting fx_tcbitX bits for BFD_RELOC_X86_64_GOTTPOFF, BFD_RELOC_X86_64_GOTPC32_TLSDESC and BFD_RELOC_32_PCREL. (md_apply_fix): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. (i386_validate_fix): Rewrite fx_tcbitX bit checking for BFD_RELOC_X86_64_GOTTPOFF, BFD_RELOC_X86_64_GOTPC32_TLSDESC and BFD_RELOC_32_PCREL. (tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. * testsuite/gas/i386/x86-64-gottpoff.d: Updated. * testsuite/gas/i386/x86-64-gottpoff.s: Add tests for "add %reg1, foo@gottpoff(%rip), %reg2" and "add foo@gottpoff(%rip), %reg, %reg2". gold/ * x86_64.cc (Target_x86_64::optimize_tls_reloc): Handle R_X86_64_CODE_6_GOTTPOFF. (Target_x86_64::Scan::get_reference_flags): Likewise. (Target_x86_64::Scan::local): Likewise. (Target_x86_64::Scan::global): Likewise. (Target_x86_64::Relocate::relocate): Likewise. (Target_x86_64::Relocate::relocate_tls): Likewise. (Target_x86_64::Relocate::tls_ie_to_le): Handle. R_X86_64_CODE_6_GOTTPOFF. * testsuite/x86_64_ie_to_le.s: Add tests for "add %reg1, foo@gottpoff(%rip), %reg2" and "add foo@gottpoff(%rip), %reg, %reg2". * testsuite/x86_64_ie_to_le.sh: Updated. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. ld/ * testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_6_GOTTPOFF tests. * testsuite/ld-x86-64/tlsbindesc.d: Updated. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise. (cherry picked from commit 5bc71c2a6b8efb27089baa1fecded82be4f550a7)
2024-02-04LoongArch: gas: Fix the types of symbols referred with %le_*_r in the symtabXi Ruoyao3-0/+12
When a symbol is referred with %le_{hi20,lo12,add}_r, it's definitely a TLS symbol and we should set its type to TLS in the symtab. Otherwise when building Perl with gcc-14 -flto, we get: /usr/bin/ld: PL_current_context: TLS definition in ./miniperl.ltrans0.ltrans.o section .tbss mismatches non-TLS reference in ./miniperl.ltrans1.ltrans.o A minimal reproducer: $ cat t1.s .section .tbss .globl x x: .word 0 $ cat t2.s f: lu12i.w $a0, %le_hi20_r(x) add.d $a0, $a0, $tp, %le_add_r(x) li.w $a1, 1 st.w $a1, $a0, %le_lo12_r(x) $ gas/as-new t1.s -o t1.o $ gas/as-new t2.s -o t2.o $ ld/ld-new t1.o t2.o ld/ld-new: x: TLS definition in t1.o section .tbss mismatches non-TLS reference in t2.o Unfortunately this was undetected before Binutils-2.42 release because GCC < 14 does not use %le_*_r, and without LTO it's very rare to have a TLS LE definition and its reference in two different translation units. So this fix should be backported to Binutils-2.42 branch too. Signed-off-by: Xi Ruoyao <xry111@xry111.site> (cherry picked from commit 029e52bac7f3a6dd8b39f7f3d298b73174da806b)
2024-02-02x86: Disallow instructions with length > 15 bytesH.J. Lu6-32/+40
It is a hard error when an instruction length exceeds the limit of 15 bytes: [hjl@gnu-cfl-3 tmp]$ cat x.s .text xacquire lock addq $0x11223344, %fs:(,%eax) [hjl@gnu-cfl-3 tmp]$ gcc -c x.s x.s: Assembler messages: x.s:2: Warning: instruction length of 16 bytes exceeds the limit of 15 [hjl@gnu-cfl-3 tmp]$ objdump -dw x.o x.o: file format elf64-x86-64 Disassembly of section .text: 0000000000000000 <.text>: 0: 64 67 f2 f0 48 81 04 05 00 00 00 00 44 33 22 xacquire lock (bad) f: 11 .byte 0x11 [hjl@gnu-cfl-3 tmp]$ and [hjl@gnu-cfl-3 tmp]$ cat z.s addq $0xe0, %fs:0, %rdx [hjl@gnu-cfl-3 tmp]$ as -o z.o z.s z.s: Assembler messages: z.s:1: Warning: instruction length of 16 bytes exceeds the limit of 15 [hjl@gnu-cfl-3 tmp]$ objdump -dw z.o z.o: file format elf64-x86-64 Disassembly of section .text: 0000000000000000 <.text>: 0: 64 62 f4 ec 18 81 04 25 00 00 00 00 e0 00 00 (bad) ... [hjl@gnu-cfl-3 pr31323]$ Instructions with length > 15 bytes are always invalid. It is quite easy to generate invalid instructions with APX now. We should issue an error when instruction length exceeds the limit of 15 bytes. PR gas/31323 * config/tc-i386.c (output_insn): Issue an error when instruction length exceeds the limit of 15 bytes. * testsuite/gas/i386/oversized16.l: Updated. * testsuite/gas/i386/oversized64.l: Likewise. * testsuite/gas/i386/x86-64-apx-inval.l: New file. * testsuite/gas/i386/x86-64-apx-inval.s: Likewise. (cherry picked from commit 46bd909328c3c8f3d6fc7a505b2fad1eea72d872)
2024-01-31Mention support for AMD/znver5 in GASNick Clifton1-0/+2
2024-01-30gas: scfi: add missing ginsn-cofi-1 testcase filesIndu Bhagat2-0/+58
Previous commit a58dc5427f0 intended to bring the following two commits from master branch: 91cdbed4d7b gas: scfi: untraceable control flow should be a hard error 16cbeae1b27 x86: testsuite: scfi: adjust COFI testcase But missed adding the testcase files. Fix the failure by adding the missing files. gas/testsuite/ * gas/scfi/x86_64/ginsn-cofi-1.l: New test. * gas/scfi/x86_64/ginsn-cofi-1.s: Likewise.
2024-01-29Set version number to 2.42.0 and re-enable developmentNick Clifton1-10/+10
2024-01-29Update version number to 2.42binutils-2_42Nick Clifton2-212/+212
2024-01-29x86: testsuite: scfi: adjust COFI testcase and gas: scfi: untraceable ↵Indu Bhagat6-37/+4
control flow should be a hard error
2024-01-29LoongArch: update test cases about TLSNick Clifton8-7/+26
2024-01-26Backport commits 969f5c0e1 (LoongArch: gas: Add support for s9 register) and ↵mengqinggang4-2/+9
a0aa6f4ab (LoongArch: ld: Add support for TLS LE symbol with addend) to 2.42 branch.
2024-01-25gas: Update NEWSAndrew Carlotti1-23/+37
Groups entries by architecture, and update AArch64 content.
2024-01-25aarch64: Update Architecture Extensions documentationAndrew Carlotti1-116/+142
Restructure the architecture extensions table, add a new table for architecture version dependencies, add missing architecture extensions, and improve some extension descriptions.
2024-01-25LoongArch: gas: Start a new frag after instructions that can be relaxedmengqinggang3-5/+93
For R_LARCH_TLS_{LE_HI20_R,LE_ADD_R,LD_PC_HI20,GD_PC_HI20, DESC_PC_HI20} relocations, start a new frag to get correct eh_frame Call Frame Information FDE DW_CFA_advance_loc info.
2024-01-25LoongArch: gas: Don't define LoongArch .alignmengqinggang4-13/+7
Gcc may generate "\t.align\t%d,54525952,4\n" before commit b20c7ee066cb7d952fa193972e8bc6362c6e4063. To write 54525952 (NOP) to object file, we call s_align_ptwo (-4). It result in alignment padding must be a multiple of 4 if .align has second parameter. Use default s_align_ptwo for .align.
2024-01-25LoongArch: Do not emit R_LARCH_RELAX for two register macrosmengqinggang3-122/+132
For two register macros (e.g. la.local $t0, $t1, symbol) used in extreme code model, do not emit R_LARCH_RELAX relocations.
2024-01-23[PATCH v2] gas/NEWS, ld/NEWS: Announce LoongArch changes in 2.42Xi Ruoyao1-0/+27
2024-01-23x86/APX: also amend the PUSH2/POP2 testcaseJan Beulich2-0/+2
Commit f530d5f1bab6 ("Update x86/APX: VROUND{P,S}{S,D} can generally be encoded") took care of only half of the remaining issue. Add #pass here as well.
2024-01-19Update x86/APX: VROUND{P,S}{S,D} can generally be encodedH.J. Lu2-0/+2
Append "#pass" to APX tests for targets which pad text sections with NOPs. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Append "#pass". * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Likewise. (cherry picked from commit f530d5f1bab6eb5adc65f422ef811fb278a21a4b)
2024-01-19x86/APX: VROUND{P,S}{S,D} can generally be encodedJan Beulich6-10/+24
VRNDSCALE{P,S}{S,D} is the AVX512 generalization of these AVX insns. As long as the immediate has the top 4 bits clear, they are equivalent to the earlier VEX-encoded insns, and hence can be used to permit use of eGPR-s in the memory operand. Since this is the normal way of using these insns, also alter the resulting diagnostic to complain about the immediate, not the eGPR use.
2024-01-19x86/APX: be consistent with insn suffixesJan Beulich1-43/+43
When there's a suitably disambiguating register operand, suffixes are generally omitted (unless in suffix-always mode). All NDD insns have a suitable register operand, so they shouldn't have suffixes by default.
2024-01-19x86: support APX forms of U{RD,WR}MSRJan Beulich4-3/+23
This was missed in 6177c84d5edc ("Support APX GPR32 with extend evex prefix").
2024-01-18Updated translations for various sub-directoriesNick Clifton2-5176/+5883
2024-01-15x86-64: Skip SCFI tests for x32 targetsH.J. Lu1-1/+1
Since SCFI isn't supported on x32: Fatal error: SCFI is not supported for this ABI skip SCFI tests for x32 targets. PR gas/31245 * testsuite/gas/scfi/x86_64/scfi-x86-64.exp: Skip for x32 targets. (cherry picked from commit 7bd344dd0e0469a93cbbf50f797155278cb76a0b)
2024-01-15Update version number and regenerate configure filesNick Clifton4-2154/+2368
2024-01-15Add markers for 2.42 branchNick Clifton2-0/+7
2024-01-15aarch64: rcpc3: Add FP load/store insnsVictor Do Nascimento5-0/+90
Along with the relevant unit-tests, this adds the following rcpc3 instructions: STL1 { <Vt>.D }[<index>], [<Xn|SP>] LDAP1 { <Vt>.D }[<index>], [<Xn|SP>] LDAPUR <Bt>, [<Xn|SP>{, #<simm>}] LDAPUR <Ht>, [<Xn|SP>{, #<simm>}] LDAPUR <St>, [<Xn|SP>{, #<simm>}] LDAPUR <Dt>, [<Xn|SP>{, #<simm>}] LDAPUR <Qt>, [<Xn|SP>{, #<simm>}] STLUR <Bt>, [<Xn|SP>{, #<simm>}] STLUR <Ht>, [<Xn|SP>{, #<simm>}] STLUR <St>, [<Xn|SP>{, #<simm>}] STLUR <Dt>, [<Xn|SP>{, #<simm>}] STLUR <Qt>, [<Xn|SP>{, #<simm>}] with `#<simm>' taking on a signed 8-bit integer value in the range [-256,255] and `index' the values 0 or 1. Co-authored-by: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2024-01-15aarch64: rcpc3: Add integer load/store insnsVictor Do Nascimento6-2/+65
Along with the relevant unit tests and updates to the existing regression tests, this adds support for the following novel rcpc3 insns: LDIAPP <Wt1>, <Wt2>, [<Xn|SP>] LDIAPP <Wt1>, <Wt2>, [<Xn|SP>], #8 LDIAPP <Xt1>, <Xt2>, [<Xn|SP>] LDIAPP <Xt1>, <Xt2>, [<Xn|SP>], #16 STILP <Wt1>, <Wt2>, [<Xn|SP>] STILP <Wt1>, <Wt2>, [<Xn|SP>, #-8]! STILP <Xt1>, <Xt2>, [<Xn|SP>] STILP <Xt1>, <Xt2>, [<Xn|SP>, #-16]! LDAPR <Wt>, [<Xn|SP>], #4 LDAPR <Xt>, [<Xn|SP>], #8 STLR <Wt>, [<Xn|SP>, #-4]! STLR <Xt>, [<Xn|SP>, #-8]!
2024-01-15aarch64: rcpc3: New RCPC3_ADDR operand typesVictor Do Nascimento1-0/+65
The particular choices of address indexing, along with their encoding for RCPC3 instructions lead to the requirement of a new set of operand descriptions, along with the relevant inserter/extractor set. That is, for the integer load/stores, there is only a single valid indexing offset quantity and offset mode is allowed - The value is always equivalent to the amount of data read/stored by the operation and the offset is post-indexed for Load-Acquire RCpc, and pre-indexed with writeback for Store-Release insns. This indexing quantity/mode pair is selected by the setting of a single bit in the instruction. To represent these insns, we add the following operand types: - AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND - AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB In the case of loads and stores involving SIMD/FP registers, the optional offset is encoded as an 8-bit signed immediate, but neither post-indexing or pre-indexing with writeback is available. This created the need for an operand type similar to AARCH64_OPND_ADDR_OFFSET, with the difference that FLD_index should not be checked. We thus introduce the AARCH64_OPND_RCPC3_ADDR_OFFSET operand, a variant of AARCH64_OPND_ADDR_OFFSET, w/o the FLD_index bitfield.
2024-01-15aarch64: rcpc3: Add +rcpc3 architectural feature support flagVictor Do Nascimento2-0/+4
Indicating the presence of the Armv8.2-a feature adding further support for the Release Consistency Model, the `+rcpc3' architectural extension flag is added to the list of possible `-march' options in Binutils, together with the necessary macro for encoding rcpc3 instructions.
2024-01-15aarch64: Fix tlbi and tlbip instructionsAndrew Carlotti9-149/+242
There are some tlbi operations that don't have a corresponding tlbip operation, but we were incorrectly using the same list for both. Add the missing tlbi *nxs operations, and use the F_REG_128 flag to filter tlbi operations that don't have a tlbip analogue. For increased clarity, I have also used a macro to reduce duplication between the 'nxs' and non-'nxs' variants, and added a test to verify that no invalid combinations are accepted. Additionally, fix two missing checks for AARCH64_OPND_SYSREG_TLBIP that were preventing disassembly of tlbip instructions.
2024-01-15aarch64: Refactor aarch64_sys_ins_reg_supported_pAndrew Carlotti1-3/+2
Add an aarch64_feature_set field to aarch64_sys_ins_reg, and use this for feature checks instead of testing against a list of operand codes.
2024-01-15aarch64: Add SVE2.1 Contiguous load/store instructions.Srinath Parvathaneni4-0/+46
Hi, This patch add support for SVE2.1 instructions ld1q, ld2q, ld3q and ld4q, st1q, st2q, st3q and st4q. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15PATCH 5/6][Binutils] aarch64: Add SVE2.1 fmin and fmax instructions.Srinath Parvathaneni3-0/+79
Hi, This patch add support for SVE2.1 instruction faddqv, fmaxnmqv, fmaxqv, fminnmqv and fminqv. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15aarch64: Add SVE2.1 dupq, eorqv and extq instructions.Srinath Parvathaneni4-0/+64
Hi, This patch add support for SVE2.1 instruction dupq, eorqv and extq. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15aarch64: Add support for FEAT_SVE2p1.Srinath Parvathaneni7-0/+134
Hi, This patch add support for FEAT_SVE2p1 (SVE2.1 Extension) feature along with +sve2p1 optional flag to enabe this feature. Also support for following SVE2p1 instructions is added addqv, andqv, smaxqv, sminqv, umaxqv, uminqv and uminqv. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15aarch64: Add support for FEAT_SME2p1 instructions.Srinath Parvathaneni5-0/+104
Hi, This patch add support for FEAT_SME2p1 and "movaz" instructions along with the optional flag +sme2p1. Following "movaz" instructions are add: Move and zero two ZA tile slices to vector registers. Move and zero four ZA tile slices to vector registers. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15aarch64: Add support for FEAT_B16B16 instructions.Srinath Parvathaneni5-0/+320
Hi, This patch add support for SVE2.1 and SME2.1 non-widening BFloat16 (FEAT_B16B16) instructions. Following instructions predicated, unpredicated and indexed variants are added in this patch. bfadd, bfclamp, bfmax bfmaxnm, bfmin,bfminnm, bfmla,bfmls,bfmul and bfsub. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15gas/NEWS: announce the new SCFI command line optionIndu Bhagat1-0/+3
2024-01-15gas: testsuite: add an x86 testsuite for SCFIIndu Bhagat129-0/+3074
The testsuite for SCFI contains target-specific tests. When a test is executed with --scfi=experimental command line option, the CFI annotations in the test .s files are skipped altogether by the GAS for processing. The CFI directives in the input assembly files are, however, validated by running the assembler one more time without --scfi=experimental. Some testcases are used to highlight those asm constructs that the SCFI machinery in GAS currently does not support: - Only System V AMD64 ABI is supported for now. Using either --32 or --x32 with SCFI results in hard error. See scfi-unsupported-1.s. - Untraceable stack-pointer manipulation in function epilougue and prologue. See scfi-unsupported-2.s. - Using Dynamically Realigned Arguement Pointer (DRAP) register to realign the stack. For SCFI, the CFA must be only REG_SP or REG_FP based. See scfi-unsupported-drap-1.s Some testcases are used to highlight some diagnostics that the SCFI machinery in GAS currently issues, with an intent to help user correct inadvertent errors in their hand-written asm. An error is issued when GAS finds that input asm is not amenable to correct CFI synthesis. - (#1) "Warning: SCFI: Asymetrical register restore" - (#2) "Error: SCFI: usage of REG_FP as scratch not supported" - (#3) "Error: SCFI: unsupported stack manipulation pattern" In case of (#2) and (#3), SCFI generation is skipped for the respective function. Above is a subset of the warnings/errors implemented in the code. gas/testsuite/: * gas/scfi/README: New test. * gas/scfi/x86_64/ginsn-add-1.l: New test. * gas/scfi/x86_64/ginsn-add-1.s: New test. * gas/scfi/x86_64/ginsn-dw2-regnum-1.l: New test. * gas/scfi/x86_64/ginsn-dw2-regnum-1.s: New test. * gas/scfi/x86_64/ginsn-pop-1.l: New test. * gas/scfi/x86_64/ginsn-pop-1.s: New test. * gas/scfi/x86_64/ginsn-push-1.l: New test. * gas/scfi/x86_64/ginsn-push-1.s: New test. * gas/scfi/x86_64/scfi-add-1.d: New test. * gas/scfi/x86_64/scfi-add-1.l: New test. * gas/scfi/x86_64/scfi-add-1.s: New test. * gas/scfi/x86_64/scfi-add-2.d: New test. * gas/scfi/x86_64/scfi-add-2.l: New test. * gas/scfi/x86_64/scfi-add-2.s: New test. * gas/scfi/x86_64/scfi-asm-marker-1.d: New test. * gas/scfi/x86_64/scfi-asm-marker-1.l: New test. * gas/scfi/x86_64/scfi-asm-marker-1.s: New test. * gas/scfi/x86_64/scfi-asm-marker-2.d: New test. * gas/scfi/x86_64/scfi-asm-marker-2.l: New test. * gas/scfi/x86_64/scfi-asm-marker-2.s: New test. * gas/scfi/x86_64/scfi-asm-marker-3.d: New test. * gas/scfi/x86_64/scfi-asm-marker-3.l: New test. * gas/scfi/x86_64/scfi-asm-marker-3.s: New test. * gas/scfi/x86_64/scfi-bp-sp-1.d: New test. * gas/scfi/x86_64/scfi-bp-sp-1.l: New test. * gas/scfi/x86_64/scfi-bp-sp-1.s: New test. * gas/scfi/x86_64/scfi-bp-sp-2.d: New test. * gas/scfi/x86_64/scfi-bp-sp-2.l: New test. * gas/scfi/x86_64/scfi-bp-sp-2.s: New test. * gas/scfi/x86_64/scfi-callee-saved-1.d: New test. * gas/scfi/x86_64/scfi-callee-saved-1.l: New test. * gas/scfi/x86_64/scfi-callee-saved-1.s: New test. * gas/scfi/x86_64/scfi-callee-saved-2.d: New test. * gas/scfi/x86_64/scfi-callee-saved-2.l: New test. * gas/scfi/x86_64/scfi-callee-saved-2.s: New test. * gas/scfi/x86_64/scfi-callee-saved-3.d: New test. * gas/scfi/x86_64/scfi-callee-saved-3.l: New test. * gas/scfi/x86_64/scfi-callee-saved-3.s: New test. * gas/scfi/x86_64/scfi-callee-saved-4.d: New test. * gas/scfi/x86_64/scfi-callee-saved-4.l: New test. * gas/scfi/x86_64/scfi-callee-saved-4.s: New test. * gas/scfi/x86_64/scfi-cfg-1.d: New test. * gas/scfi/x86_64/scfi-cfg-1.l: New test. * gas/scfi/x86_64/scfi-cfg-1.s: New test. * gas/scfi/x86_64/scfi-cfg-2.d: New test. * gas/scfi/x86_64/scfi-cfg-2.l: New test. * gas/scfi/x86_64/scfi-cfg-2.s: New test. * gas/scfi/x86_64/scfi-cfi-label-1.d: New test. * gas/scfi/x86_64/scfi-cfi-label-1.l: New test. * gas/scfi/x86_64/scfi-cfi-label-1.s: New test. * gas/scfi/x86_64/scfi-cfi-sections-1.d: New test. * gas/scfi/x86_64/scfi-cfi-sections-1.l: New test. * gas/scfi/x86_64/scfi-cfi-sections-1.s: New test. * gas/scfi/x86_64/scfi-cofi-1.d: New test. * gas/scfi/x86_64/scfi-cofi-1.l: New test. * gas/scfi/x86_64/scfi-cofi-1.s: New test. * gas/scfi/x86_64/scfi-diag-1.l: New test. * gas/scfi/x86_64/scfi-diag-1.s: New test. * gas/scfi/x86_64/scfi-diag-2.l: New test. * gas/scfi/x86_64/scfi-diag-2.s: New test. * gas/scfi/x86_64/scfi-dyn-stack-1.d: New test. * gas/scfi/x86_64/scfi-dyn-stack-1.l: New test. * gas/scfi/x86_64/scfi-dyn-stack-1.s: New test. * gas/scfi/x86_64/scfi-enter-1.d: New test. * gas/scfi/x86_64/scfi-enter-1.l: New test. * gas/scfi/x86_64/scfi-enter-1.s: New test. * gas/scfi/x86_64/scfi-fp-diag-2.l: New test. * gas/scfi/x86_64/scfi-fp-diag-2.s: New test. * gas/scfi/x86_64/scfi-indirect-mov-1.d: New test. * gas/scfi/x86_64/scfi-indirect-mov-1.l: New test. * gas/scfi/x86_64/scfi-indirect-mov-1.s: New test. * gas/scfi/x86_64/scfi-indirect-mov-2.d: New test. * gas/scfi/x86_64/scfi-indirect-mov-2.l: New test. * gas/scfi/x86_64/scfi-indirect-mov-2.s: New test. * gas/scfi/x86_64/scfi-indirect-mov-3.d: New test. * gas/scfi/x86_64/scfi-indirect-mov-3.l: New test. * gas/scfi/x86_64/scfi-indirect-mov-3.s: New test. * gas/scfi/x86_64/scfi-indirect-mov-4.d: New test. * gas/scfi/x86_64/scfi-indirect-mov-4.l: New test. * gas/scfi/x86_64/scfi-indirect-mov-4.s: New test. * gas/scfi/x86_64/scfi-indirect-mov-5.s: New test. * gas/scfi/x86_64/scfi-lea-1.d: New test. * gas/scfi/x86_64/scfi-lea-1.l: New test. * gas/scfi/x86_64/scfi-lea-1.s: New test. * gas/scfi/x86_64/scfi-leave-1.d: New test. * gas/scfi/x86_64/scfi-leave-1.l: New test. * gas/scfi/x86_64/scfi-leave-1.s: New test. * gas/scfi/x86_64/scfi-pushq-1.d: New test. * gas/scfi/x86_64/scfi-pushq-1.l: New test. * gas/scfi/x86_64/scfi-pushq-1.s: New test. * gas/scfi/x86_64/scfi-pushsection-1.d: New test. * gas/scfi/x86_64/scfi-pushsection-1.l: New test. * gas/scfi/x86_64/scfi-pushsection-1.s: New test. * gas/scfi/x86_64/scfi-pushsection-2.d: New test. * gas/scfi/x86_64/scfi-pushsection-2.l: New test. * gas/scfi/x86_64/scfi-pushsection-2.s: New test. * gas/scfi/x86_64/scfi-selfalign-func-1.d: New test. * gas/scfi/x86_64/scfi-selfalign-func-1.l: New test. * gas/scfi/x86_64/scfi-selfalign-func-1.s: New test. * gas/scfi/x86_64/scfi-simple-1.d: New test. * gas/scfi/x86_64/scfi-simple-1.l: New test. * gas/scfi/x86_64/scfi-simple-1.s: New test. * gas/scfi/x86_64/scfi-simple-2.d: New test. * gas/scfi/x86_64/scfi-simple-2.l: New test. * gas/scfi/x86_64/scfi-simple-2.s: New test. * gas/scfi/x86_64/scfi-sub-1.d: New test. * gas/scfi/x86_64/scfi-sub-1.l: New test. * gas/scfi/x86_64/scfi-sub-1.s: New test. * gas/scfi/x86_64/scfi-sub-2.d: New test. * gas/scfi/x86_64/scfi-sub-2.l: New test. * gas/scfi/x86_64/scfi-sub-2.s: New test. * gas/scfi/x86_64/scfi-unsupported-1.l: New test. * gas/scfi/x86_64/scfi-unsupported-1.s: New test. * gas/scfi/x86_64/scfi-unsupported-2.l: New test. * gas/scfi/x86_64/scfi-unsupported-2.s: New test. * gas/scfi/x86_64/scfi-unsupported-3.l: New test. * gas/scfi/x86_64/scfi-unsupported-3.s: New test. * gas/scfi/x86_64/scfi-unsupported-4.l: New test. * gas/scfi/x86_64/scfi-unsupported-4.s: New test. * gas/scfi/x86_64/scfi-unsupported-cfg-1.l: New test. * gas/scfi/x86_64/scfi-unsupported-cfg-1.s: New test. * gas/scfi/x86_64/scfi-unsupported-cfg-2.l: New test. * gas/scfi/x86_64/scfi-unsupported-cfg-2.s: New test. * gas/scfi/x86_64/scfi-unsupported-drap-1.l: New test. * gas/scfi/x86_64/scfi-unsupported-drap-1.s: New test. * gas/scfi/x86_64/scfi-unsupported-insn-1.l: New test. * gas/scfi/x86_64/scfi-unsupported-insn-1.s: New test. * gas/scfi/x86_64/scfi-x86-64.exp: New file.
2024-01-15gas: doc: update documentation for the new listing optionIndu Bhagat1-5/+11
Add a new listing option, -i, to emit ginsn in the listing output. We may also emit other SCFI information if necessary in the future. ginsn are most useful when seen alongside the assembly instructions. Hence, they are emitted when the user includes the assembly instructions in the listing output, i.e., "-ali=FILE". gas/doc/: * as.texi: Add documentation for the new listing option, -i.
2024-01-15gas: x86: synthesize CFI for hand-written asmIndu Bhagat16-10/+4128
This patch adds support in GAS to create generic GAS instructions (a.k.a., the ginsn) for the x86 backend (AMD64 ABI only at this time). Using this ginsn infrastructure, GAS can then synthesize CFI for hand-written asm for x86_64. A ginsn is a target-independent representation of the machine instructions. One machine instruction may need one or more ginsn. This patch also adds skeleton support for printing ginsn in the listing output for debugging purposes. Since the current use-case of ginsn is to synthesize CFI, the x86 target needs to generate ginsns necessary for the following machine instructions only: - All change of flow instructions, including all conditional and unconditional branches, call and return from functions. - All register saves and unsaves to the stack. - All instructions affecting the two registers that could potentially be used as the base register for CFA tracking. For SCFI, the base register for CFA tracking is limited to REG_SP and REG_FP only for now. The representation of ginsn is kept simple: - GAS instruction has GINSN_NUM_SRC_OPNDS (defined to be 2 at this time) number of source operands and one destination operand at this time. - GAS instruction uses DWARF register numbers in its representation and does not track register size. - GAS instructions carry location information (file name and line number). - GAS instructions are ID's with a natural number in order of their addtion to the list. This can be used as a proxy for the static program order of the corresponding machine instructions. Note that, GAS instruction (ginsn) format does not support GINSN_TYPE_PUSH and GINSN_TYPE_POP. Some architectures, like aarch64, do not have push and pop instructions, but rather STP/LDP/STR/LDR etc. instructions. Further these instructions have a variety of addressing modes, like offset, pre-indexing and post-indexing etc. Among other things, one of differences in these addressing modes is _when_ the addr register is updated with the result of the address calculation: before or after the memory operation. To best support such needs, the generic instructions like GINSN_TYPE_LOAD, GINSN_TYPE_STORE together with GINSN_TYPE_ADD, and GINSN_TYPE_SUB may be used. The functionality provided in ginsn.c and scfi.c is compiled in when a target defines TARGET_USE_SCFI and TARGET_USE_GINSN. This can be revisited later when there are other use-cases of creating ginsn's in GAS, apart from the current use-case of synthesizing CFI for hand-written asm. Support is added only for System V AMD64 ABI for ELF at this time. If the user enables SCFI with --32, GAS issues an error: "Fatal error: SCFI is not supported for this ABI" For synthesizing (DWARF) CFI, the SCFI machinery requires the programmer to adhere to some pre-requisites for their asm: - Hand-written asm block must begin with a .type foo, @function It is highly recommended to, additionally, also ensure that: - Hand-written asm block ends with a .size foo, .-foo The SCFI machinery encodes some rules which align with the standard calling convention specified by the ABI. Apart from the rules, the SCFI machinery employs some heuristics. For example: - The base register for CFA tracking may be either REG_SP or REG_FP. - If the base register for CFA tracking is REG_SP, the precise amount of stack usage (and hence, the value of REG_SP) must be known at all times. - If using dynamic stack allocation, the function must switch to FP-based CFA. This means using instructions like the following (in AMD64) in prologue: pushq %rbp movq %rsp, %rbp and analogous instructions in epilogue. - Save and Restore of callee-saved registers must be symmetrical. However, the SCFI machinery at this time only warns if any such asymmetry is seen. These heuristics/rules are architecture-independent and are meant to employed for all architectures/ABIs using SCFI in the future. gas/ * Makefile.am: Add new files. * Makefile.in: Regenerated. * as.c (defined): Handle documentation and listing option for ginsns and SCFI. * config/obj-elf.c (obj_elf_size): Invoke ginsn_data_end. (obj_elf_type): Invoke ginsn_data_begin. * config/tc-i386.c (x86_scfi_callee_saved_p): New function. (ginsn_prefix_66H_p): Likewise. (ginsn_dw2_regnum): Likewise. (x86_ginsn_addsub_reg_mem): Likewise. (x86_ginsn_addsub_mem_reg): Likewise. (x86_ginsn_alu_imm): Likewise. (x86_ginsn_move): Likewise. (x86_ginsn_lea): Likewise. (x86_ginsn_jump): Likewise. (x86_ginsn_jump_cond): Likewise. (x86_ginsn_enter): Likewise. (x86_ginsn_safe_to_skip): Likewise. (x86_ginsn_unhandled): Likewise. (x86_ginsn_new): New functionality to generate ginsns. (md_assemble): Invoke x86_ginsn_new. (s_insn): Likewise. (i386_target_format): Add hard error for usage of SCFI with non AMD64 ABIs. * config/tc-i386.h (TARGET_USE_GINSN): New definition. (TARGET_USE_SCFI): Likewise. (SCFI_MAX_REG_ID): Likewise. (REG_FP): Likewise. (REG_SP): Likewise. (SCFI_INIT_CFA_OFFSET): Likewise. (SCFI_CALLEE_SAVED_REG_P): Likewise. (x86_scfi_callee_saved_p): Likewise. * gas/listing.h (LISTING_GINSN_SCFI): New define for ginsn and SCFI. * gas/read.c (read_a_source_file): Close SCFI processing at end of file read. * gas/scfidw2gen.c (scfi_process_cfi_label): Add implementation. (scfi_process_cfi_signal_frame): Likewise. * subsegs.h (struct frch_ginsn_data): New forward declaration. (struct frchain): New member for ginsn data. * gas/subsegs.c (subseg_set_rest): Initialize the new member. * symbols.c (colon): Invoke ginsn_frob_label to convey user-defined labels to ginsn infrastructure. * ginsn.c: New file. * ginsn.h: New file. * scfi.c: New file. * scfi.h: New file.
2024-01-15opcodes: gas: x86: define and use Rex2 as attribute not constraintIndu Bhagat1-1/+1
Rex2 is currently an operand constraint. For the upcoming SCFI implementation in GAS, we need to identify operations which implicitly update the stack pointer. An operand constraint enumerator for implicit stack op seems more appropriate than an attribute. However, two opcodes currently necessitate both Rex2 and an implicit stack op marker; this prompts revisiting the current representations a bit. Make Rex2 a standalone attribute, so that later a new operand constraint may be added for IMPLICIT_STACK_OP. ChangeLog: * gas/config/tc-i386.c (is_apx_rex2_encoding): Update the check. * opcodes/i386-gen.c: Add a new BITFIELD for Rex2. * opcodes/i386-opc.h (REX2_REQUIRED): Remove. * opcodes/i386-opc.tbl: Remove Rex2 operand constraint. * opcodes/i386-tbl.h: Regenerated.
2024-01-15gas: scfidw2gen: new functionality to prepare for SCFIIndu Bhagat5-5/+312
Define a new set of handlers for CFI directives for the purpose of SCFI. The SCFI machinery ignores many of the user-specified CFI direcives when SCFI is in effect. A warning ("Warning: SCFI ignores most user-specified CFI directives") is issued once per file. The following CFI directives, however, are not ignored: - .cfi_sections - .cfi_label - .cfi_signal_frame gas/ * Makefile.am: Add new files to GAS_CFILES and HFILES. * Makefile.in: Likewise. * gas/read.c (scfi_pop_insert): New define. (pobegin): Use the SCFI handlers. * scfidw2gen.c: New file. * scfidw2gen.h: New file.
2024-01-15gas: add new command line option --scfi=experimentalIndu Bhagat3-2/+44
When the command line option --scfi=experimenta is passed to the GNU assembler, it will synthesize DWARF call frame information (CFI) for the input assembly. The option --scfi=experimental will also ignore most of the existing .cfi_* directives, if already contained in the provided input file. Only the following CFI directives will not be ignored: - .cfi_sections, - .cfi_label, - .cfi_signal_frame To use SCFI, a target will need to: - define TARGET_USE_SCFI and TARGET_USE_GINSN, and other necessary definitions, - provide means to help GAS understand the target specific instruction semantics by creating ginsns. The upcoming support for SCFI is inteded to be experimental, hence the option --scfi=experimental. The --scfi= may see more options like --scfi=[all,none] added in future, once the SCFI support in GAS is mature and robust. The offering may also see for example, an --scfi=inline option for dealing with inline asm may be added in the future. In --scfi=inline option, the GNU assembler may consume (and not ignore) the compiler generated CFI for the code surrounding the inline asm. Also document the option. gas/ * as.c (show_usage): Add support for --scfi=experimental. (parse_args): Likewise. * as.h (enum synth_cfi_type): Define new type. * doc/as.texi: Document the new option.
generated by cgit v1.1 at 2024-07-26 16:35:53 +0000