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2017-11-08Fix typo in changelogNick Clifton1-1/+1
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton2-1/+13
2017-11-08Adds command line support for Armv8.4-A, via the new command line option -mar...Jiong Wang12-3/+1552
2017-11-08xtensa message pluralizationAlan Modra2-4/+18
2017-11-07RISC-V: Fix riscv g++ testsuite EH failures.Jim Wilson5-0/+47
2017-11-07RISC-V: Add satp as an alias for sptbrPalmer Dabbelt5-0/+23
2017-11-07This patch similarly to the AArch64 one enables Dot Product support by defaul...Tamar Christina2-68/+87
2017-11-07bundle_lock message tidyAlan Modra3-13/+20
2017-11-07readelf ngettext fixesAlan Modra32-132/+167
2017-11-07gas and ld pluralization fixesAlan Modra15-42/+127
2017-11-07ngettext supportAlan Modra2-2/+13
2017-11-03Add option for Qualcomm Saphira partSiddhesh Poyarekar3-0/+10
2017-11-02[ARM] Help wince objdump on coproc testsThomas Preud'homme3-2/+8
2017-11-01FT32B is a new FT32 family member. It has a code compression scheme, which re...James Bowman21-375/+2909
2017-11-01[ARM] Fix Coprocessor instructions availabilityThomas Preud'homme26-35/+328
2017-10-26x86: Check invalid XMM register in AVX512 gathersH.J. Lu14-1/+41
2017-10-26testsuite/gas/all/fill-1.s: Use L2 rather than .L2.Hans-Peter Nilsson2-2/+6
2017-10-25PR22348, conflicting global vars in crx and cr16Alan Modra2-10/+18
2017-10-25Yet another fill-1 test fixAlan Modra3-11/+17
2017-10-24RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman8-0/+26
2017-10-24RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2Andrew Waterman5-0/+15
2017-10-24Fix my previous gas/ChangeLog entryPalmer Dabbelt1-2/+2
2017-10-24i386: Support .code64 directive only with 64-bit bfdH.J. Lu7-4/+54
2017-10-23RISC-V: Don't emit 2-byte NOPs if the C extension is disabledPalmer Dabbelt2-1/+6
2017-10-23Add missing ChangeLog entriesIgor Tsimbalist1-0/+162
2017-10-23MIPS: Preset EF_MIPS_ABI2 with n32 ELF objectsMaciej W. Rozycki2-3/+6
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist15-0/+1046
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist15-1/+977
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist33-1/+738
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist33-0/+1349
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist32-1/+1865
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist15-2/+3409
2017-10-22Fix spurious left-over quotes from last edit.Hans-Peter Nilsson2-3/+8
2017-10-20Improve handling of REPT pseudo op with a negative count.Nick Clifton8-9/+46
2017-10-19RISC-V: Relax RISCV_PCREL_* to RISCV_GPREL_*Palmer Dabbelt2-1/+10
2017-10-19Fix the AVR assembler so that it will correctly issue warnings about skipped ...Nick Clifton6-4/+49
2017-10-19Fix fill-1 testcaseAndreas Krebbel4-6/+23
2017-10-18RISC-V: Mark unsupported gas testcasesPalmer Dabbelt9-1/+38
2017-10-18Update Cris assembler tests for checks that now pass where they used to fail.Nick Clifton3-6/+9
2017-10-18Update the Swedish translation in the GAS subdirectory.Nick Clifton2-4238/+6054
2017-10-16Fix segfault processing nios2 pseudo-instructions with too few arguments.Sandra Loosemore5-30/+145
2017-10-12FT32: support for FT32B processor - part 1James Bowman2-3/+20
2017-10-11Disable the inclusion of logical input files in the assembler listing output ...Nick Clifton4-13/+38
2017-10-09S/390: Sync with latest POP - 3 new instructionsAndreas Krebbel4-1/+14
2017-10-09Add missing changelog entriesAndreas Krebbel1-0/+11
2017-10-09Replace nop in fill-1.s testcase.Andreas Krebbel1-1/+1
2017-10-09Enable .fill forward labelsAndreas Krebbel3-1/+8
2017-10-05Fix the MSP430 assembler so that it detects and reports extraneous text at th...Nick Clifton6-27/+114
2017-10-04Add an assembler test for PR gas/21167H.J. Lu4-0/+22
2017-10-05PR21167, relocation sections not included in groupsAlan Modra8-31/+62
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