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2022-01-01ubsan: next_char_of_string signed integer overflowAlan Modra1-2/+2
2022-01-01ubsan: signed integer multiply overflowAlan Modra1-1/+6
2021-12-28gas reloc sortingAlan Modra4-42/+30
2021-12-24RISC-V: Rewrite the csr testcases.Nelson Chu42-1521/+3567
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta5-5/+313
2021-12-24RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/testsVineet Gupta9-90/+0
2021-12-22RISC-V: Update Scalar Crypto testcases.jiawei18-144/+144
2021-12-21x86: -mfence-as-lock-add=yes doesn't work for 16-bit modeJan Beulich1-1/+6
2021-12-21gas/ELF: avoid below-base ref in obj_elf_parse_section_letters()Jan Beulich1-13/+11
2021-12-17x86: Terminate mnemonicendp in swap_operand()Vladimir Mezentsev8-420/+420
2021-12-16Fix AVR assembler so that it creates relocs that will work with linker relaxa...Nick Clifton7-6/+45
2021-12-16arm: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford11-3/+94
2021-12-16arm: Add support for Armv8.7-A and Armv8.8-ARichard Sandiford9-1/+65
2021-12-16aarch64: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford18-2/+95
2021-12-16RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu2-0/+20
2021-12-15loongarch64 build failure on 32-bit hostAlan Modra1-6/+6
2021-12-09RISC-V: Clarify the behavior of .option arch directive.Nelson Chu8-9/+13
2021-12-02aarch64: Update gas/NEWS for recent changesRichard Sandiford1-1/+4
2021-12-02aarch64: Add BC instructionRichard Sandiford7-0/+90
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford4-10/+202
2021-12-02aarch64: Add support for +mopsRichard Sandiford7-0/+1592
2021-12-02aarch64: Add Armv8.8-A system registersRichard Sandiford5-0/+46
2021-12-02aarch64: Add id_aa64isar2_el1Richard Sandiford5-0/+8
2021-12-02aarch64: Add support for Armv8.8-ARichard Sandiford4-2/+10
2021-12-02aarch64: Provide line info for unclosed sequencesRichard Sandiford5-15/+17
2021-12-02aarch64: Add maximum immediate value to aarch64_sys_regRichard Sandiford9-39/+66
2021-12-02gas: re-generate configureSimon Marchi1-2/+1
2021-12-01gas: merge doc subdir up a levelMike Frysinger6-1163/+671
2021-11-30aarch64: Add missing system registers [PR27145]Richard Sandiford10-6/+877
2021-11-30aarch64: Make LOR registers conditional on +lorRichard Sandiford4-1/+13
2021-11-30aarch64: Remove ZIDR_EL1Richard Sandiford3-7/+0
2021-11-30aarch64: Allow writes to MFAR_EL3Richard Sandiford5-20/+13
2021-11-30aarch64: Mark PMSIDR_EL1 as read-onlyRichard Sandiford5-3/+8
2021-11-30aarch64: Remove duplicate system register entriesRichard Sandiford2-4/+0
2021-11-30aarch64: Check for register aliases before mnemonicsRichard Sandiford6-34/+38
2021-11-30RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu2-0/+13
2021-11-30RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.Nelson Chu2-68/+28
2021-11-29PR28629 NIOS2 falloutAlan Modra1-1/+1
2021-11-26gas: Update commit 4780e5e4933H.J. Lu2-2/+2
2021-11-26[gas] Fix file 0 dir with -gdwarf-5Tom de Vries3-3/+16
2021-11-25gas: enable silent build rulesMike Frysinger2-2/+42
2021-11-23Update bug reporting addressAlan Modra2-6/+2
2021-11-22RISC-V: Replace .option rvc/norvc with .option arch, +c/-c.Nelson Chu16-18/+22
2021-11-19RISC-V: Support new .option arch directive.Nelson Chu12-18/+134
2021-11-19Re: Add multibyte character warning option to the assembler.Alan Modra1-10/+10
2021-11-19RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu6-0/+101
2021-11-18Add multibyte character warning option to the assembler.Nick Clifton14-10/+205
2021-11-18RISC-V: Add testcases for z[fdq]inxjiawei6-0/+222
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei1-1/+3
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus6-0/+348
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