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2019-05-06PowerPC reloc symbols that shouldn't be adjustedAlan Modra3-1/+27
2019-05-05[LVu] base subseg head view on prev subseg's tailAlexandre Oliva5-5/+107
2019-05-04m32c padding with nopsAlan Modra8-31/+23
2019-05-02i386: Issue a warning to IRET without suffix for .code16gccH.J. Lu5-7/+46
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das8-0/+111
2019-04-29S12Z: Opcodes: Fix crash when trying to decode a truncated operation.John Darrington4-0/+27
2019-04-26[MIPS] Add load-link, store-conditional paired instructionsAndrew Bennett14-10/+228
2019-04-26i386: Don't add 0x66 prefix to IRET for .code16gccH.J. Lu4-0/+22
2019-04-25Speed up locview resolution with relaxable fragsAlexandre Oliva4-1/+69
2019-04-24resolve_symbol_value vs. .loc view resolutionAlan Modra3-29/+35
2019-04-24S12Z: Opcodes: Handle bit map operations with non-canonical operands.John Darrington3-1/+15
2019-04-19RX Assembler: Ensure that the internal limit on the number of relaxation iter...Nick Clifton3-8/+31
2019-04-18Improve warning message for $0 constraint on MIPSR6 branchesMatthew Fortune3-11/+20
2019-04-18MSP430 Assembler: Define symbols for functions to run through.Jozef Lawrynowicz9-6/+141
2019-04-17MSP430 Assembler: Leave placement of .lower and .upper sections to generic li...Jozef Lawrynowicz1-0/+13
2019-04-17MSP420 assembler: Add -m{u,U} options to enable/disable NOP warnings for unk...Jozef Lawrynowicz13-10/+198
2019-04-16xfail gas weakref1 test for nds32Alan Modra2-0/+5
2019-04-16ns32k testsuite tidyAlan Modra3-3/+6
2019-04-16Move fixup fx_bit_fixP and fx_im_disp fields to TC_FIX_TYPEAlan Modra8-68/+66
2019-04-16Make fixup fx_where unsignedAlan Modra7-27/+36
2019-04-16Make frag fr_fix unsignedAlan Modra13-23/+40
2019-04-15[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registersAndre Vieira6-4/+225
2019-04-15[binutils, ARM, 15/16] Add support for VSCCLRMAndre Vieira6-14/+158
2019-04-15[binutils, ARM, 13/16] Add support for CLRMAndre Vieira7-29/+150
2019-04-15[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Ma...Andre Vieira7-0/+189
2019-04-15[binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M MainlineAndre Vieira4-0/+121
2019-04-15[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_...Andre Vieira2-0/+42
2019-04-15[binutils, ARM, 9/16] New BFL instruction for Armv8.1-M MainlineAndre Vieira9-0/+102
2019-04-15[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18Andre Vieira2-0/+42
2019-04-15[binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M MainlineAndre Vieira7-0/+69
2019-04-15[binutils, ARM, 6/16] New BF instruction for Armv8.1-M MainlineAndre Vieira9-0/+142
2019-04-15[binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM...Andre Vieira2-0/+42
2019-04-15[binutils, ARM, 4/16] BF insns infrastructure with array of relocs in struct ...Andre Vieira2-271/+310
2019-04-15[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real fo...Andre Vieira2-0/+64
2019-04-15[GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M MainlineAndre Vieira6-4/+585
2019-04-15[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLIAndre Vieira3-45/+68
2019-04-13[MIPS] Add i6500 CPU and fix i6400 default ASEsMatthew Fortune6-1/+63
2019-04-13[MIPS] Apply ASE information for the selected processorMatthew Fortune4-7/+51
2019-04-12GAS: S12Z: Remove definition of macro TC_M68K.John Darrington2-3/+4
2019-04-12GAS: tc-s12z.c: int -> bfd_booleanJohn Darrington2-206/+210
2019-04-11xtensa: gas: add relaxations testsMax Filippov13-0/+179
2019-04-11xtensa: gas: convert tests to run_dump_testsMax Filippov13-105/+63
2019-04-11xtensa: gas: clean up literal management codeMax Filippov2-60/+65
2019-04-11xtensa: gas: put .literal_position at section startMax Filippov5-25/+34
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das6-33/+45
2019-04-11[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instructionSudakshina Das5-0/+39
2019-04-10Disable R_X86_64_PLT32 generation as branch marker on Solaris/x86Rainer Orth21-0/+426
2019-04-10te-cloudabi.hAlan Modra5-6/+41
2019-04-09[MIPS] Add RDHWR with the SEL field for MIPS R6.Robert Suchanek4-0/+71
2019-04-08x86: Define GNU_PROPERTY_X86_ISA_1_AVX512_BF16H.J. Lu5-2/+13
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