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2021-08-06Re: Add tests for Intel AVX512_FP16 instructionsAlan Modra1-0/+1
2021-08-05[PATCH 2/2] Add tests for Intel AVX512_FP16 instructionsCui,Lili30-0/+26033
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili3-4/+47
2021-08-04IBM Z: Remove lpswey parameterAndreas Krebbel2-2/+2
2021-08-04gas: correctly output XCOFF tbss symbols with XTY_CM type.Clément Chigot1-1/+2
2021-08-04gas: always add dummy symbols when creating XCOFF sections.Clément Chigot1-17/+11
2021-07-30gas: ensure XCOFF DWARF subsection are initialized to 0Clément Chigot1-1/+1
2021-07-29gas: improve C_BSTAT and C_STSYM symbols handling on XCOFFClément Chigot7-3/+81
2021-07-28x86: Simplify check for distinct TMM register operandsH.J. Lu1-15/+10
2021-07-28PowerPC: ignore sticky options for .machineAlan Modra1-4/+16
2021-07-26PATCH [10/10] arm: Alias 'ra_auth_code' to r12 for pacbti.Andrea Corallo1-0/+3
2021-07-26PATCH [9/10] arm: add 'pacg' instruction for Armv8.1-M pacbti extensionAndrea Corallo3-0/+16
2021-07-26PATCH [8/10] arm: add 'autg' instruction for Armv8.1-M pacbti extensionAndrea Corallo3-0/+4
2021-07-26PATCH [7/10] arm: add 'bxaut' instruction for Armv8.1-M pacbti extensionAndrea Corallo3-1/+17
2021-07-26PATCH [6/10] arm: Add -march=armv8.1-m.main+pacbti flagAndrea Corallo1-0/+4
2021-07-26PATCH [4/10] arm: add 'pac' instruction for Armv8.1-M pacbti extensionAndrea Corallo5-0/+10
2021-07-26PATCH [3/10] arm: add 'aut' instruction for Armv8.1-M pacbti extensionAndrea Corallo5-0/+10
2021-07-26PATCH [2/10] arm: add 'pacbti' instruction for Armv8.1-M pacbti extensionAndrea Corallo6-0/+41
2021-07-26PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extensionAndrea Corallo3-0/+16
2021-07-24Revert: PowerPC: Don't generate unused section symbolsAlan Modra3-0/+3
2021-07-23x86: express unduly set rounding control bits in disassemblyJan Beulich6-26/+28
2021-07-22x86: drop dq{b,d}_modeJan Beulich5-84/+84
2021-07-22x86: correct EVEX.V' handling outside of 64-bit modeJan Beulich1-2/+2
2021-07-22x86-64: properly bounds-check %bnd<N> in OP_G()Jan Beulich2-0/+16
2021-07-22x86-64: generalize OP_G()'s EVEX.R' handlingJan Beulich3-0/+6
2021-07-22x86: correct VCVT{,U}SI2SD rounding mode handlingJan Beulich4-1/+28
2021-07-21as_bad_subtractAlan Modra33-149/+121
2021-07-21Remove `netbsdpe` supportJohn Ericson1-1/+0
2021-07-20RISC-V: Minor updates for architecture parser.Nelson Chu2-2/+2
2021-07-14x86: Add int1 as one byte opcode 0xf1H.J. Lu6-0/+12
2021-07-14gas: default TC_VALIDATE_FIX_SUB to 0Alan Modra6-13/+27
2021-07-14objdump: add DWARF support for AIXClément Chigot2-1/+6
2021-07-13RISC-V: Enable elf attributes when default configure option isn't set.Nelson Chu2-16/+2
2021-07-12Add the SEC_ELF_OCTETS flag to debug sections created by the assembler.Tucker2-0/+22
2021-07-07Add changelog entries for last commitAndreas Krebbel1-0/+5
2021-07-07IBM Z: Add another arch14 instructionAndreas Krebbel2-0/+2
2021-07-07Fix problems translating messages when a percentage sign appears at the end o...Nick Clifton6-333/+367
2021-07-06PR 28053: Fix spelling mistakes: usupported -> unsupported and relocatation -...Yuri Chornoivan1-1/+1
2021-07-05Updated translations (mainly Ukranian and French) triggered by creation of 2....Nick Clifton2-5658/+5824
2021-07-03Update version number and regenerate filesNick Clifton3-2800/+2856
2021-07-03Add markers for 2.37 branchNick Clifton2-0/+6
2021-07-02Re: Fix minor NDS32 renaming snafuAlan Modra2-2/+6
2021-07-02Fix minor NDS32 renaming snafu.Nick Clifton2-2/+7
2021-07-01opcodes: constify & scope microblaze opcodesMike Frysinger2-2/+7
2021-07-01opcodes: constify aarch64_opcode_tablesMike Frysinger2-3/+9
2021-06-24gas: update csect alignment for PPC prefixed instructions on XCOFFClément Chigot2-0/+10
2021-06-22picojava assembler and disassembler fixesAlan Modra4-173/+159
2021-06-19ubsan errors when 32-bit bfdAlan Modra2-3/+7
2021-06-19ppc raw test failure when 32-bit bfdAlan Modra3-2/+7
2021-06-18gas: fold symbol table entries generated for .startof.() / .sizeof.()Jan Beulich5-8/+71
generated by cgit v1.1 at 2024-11-08 10:43:45 +0000