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2020-03-06x86: fold (supposed to be) identical codeJan Beulich2-27/+20
2020-03-06x86: replace NoRex64 on VEX-encoded insnsJan Beulich8-50/+64
2020-03-06x86: drop Rex64 attributeJan Beulich2-3/+10
2020-03-06x86: correct MPX insn w/o base or index encoding in 16-bit modeJan Beulich5-0/+182
2020-03-06x86: add missing IgnoreSizeJan Beulich31-22/+274
2020-03-06x86: refine TPAUSE and UMWAITJan Beulich8-16/+70
2020-03-04RISC-V: Support assembler modifier %got_pcrel_hi.Nelson Chu7-7/+45
2020-03-04RISC-V: Add description for RISC-V Modifiers to as doc.Nelson Chu2-1/+117
2020-03-04Generate a warning in the ARM assembler if a PC-relative thumb load instructi...Alexandre Oliva7-6/+24
2020-03-04x86: support VMGEXITJan Beulich7-4/+21
2020-03-03x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu2-13/+21
2020-03-03The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble...Sergey Belyashov6-4/+54
2020-03-03x86: Allow integer conversion without suffix in AT&T syntaxH.J. Lu8-24/+61
2020-03-03x86: Improve -malign-branchHongtao Liu7-32/+378
2020-03-03Fix a potential illegal memory access in the Z80 assembler.Sergey Belyashov2-8/+30
2020-03-03Tidy obj-coff.hAlan Modra2-14/+5
2020-03-02miscellaneous SEC_SMALL_DATAAlan Modra6-56/+34
2020-02-28MIPS/fix_loongson3_llsc: fix when target has multi labelsYunQiang Su2-5/+51
2020-02-26[binutils][arm] Arm CDE CX*A instructions allow condition codeMatthew Malcomson5-46/+50
2020-02-26gas gettext warningAlan Modra2-1/+6
2020-02-26gas strncpy warningAlan Modra2-1/+7
2020-02-26Indent labelsAlan Modra22-63/+87
2020-02-20RISC-V: Support the read-only CSR checking.Nelson Chu8-0/+543
2020-02-20RISC-V: Disable the CSR checking by default.Nelson Chu5-3/+50
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu8-9/+198
2020-02-21pdp11 reloc processingAlan Modra2-13/+22
2020-02-21PR25569, PDP11 ld -s clobbers last data byteAlan Modra2-20/+35
2020-02-19RISC-V: Add description for -march-attr/-mno-arch-attr options in gas doc.Nelson Chu2-0/+19
2020-02-19RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.Jim Wilson3-0/+19
2020-02-19Various fixes for the Z80 support.Sergey Belyashov25-229/+209
2020-02-19x86: Mark cvtpi2ps and cvtpi2pd as MMXH.J. Lu6-1/+36
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu3-5/+14
2020-02-17x86: fold AddrPrefixOpReg templatesJan Beulich2-48/+72
2020-02-17x86/Intel: don't swap operands of MONITOR{,X} and MWAIT{,X}Jan Beulich9-4/+124
2020-02-17x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich10-45/+115
2020-02-16x86: Don't disable SSE4a when disabling SSE4H.J. Lu3-2/+13
2020-02-14Remove the old movsx and movzx documentation for AT&T syntaxH.J. Lu2-16/+5
2020-02-14x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich29-87/+1673
2020-02-14x86: adjust segment override prefix emissionJan Beulich4-6/+29
2020-02-14x86: optimize away pointless segment overridesJan Beulich4-3/+31
2020-02-14x86: extend LEA's segment override warningJan Beulich6-3/+33
2020-02-14x86: Document movsx/movsxd/movzx for AT&T syntaxH.J. Lu2-0/+59
2020-02-13x86: Resolve PLT32 reloc aganst local symbol to sectionH.J. Lu7-2/+62
2020-02-13x86: fix SSE4a dependencies of ".arch .nosse*"Jan Beulich2-1/+6
2020-02-12x86: correct VFPCLASSP{S,D} operand size handlingJan Beulich6-5/+93
2020-02-12x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich11-3/+88
2020-02-12x86: also disallow non-byte/-word registers with byte/word suffixJan Beulich7-71/+62
2020-02-12x86/Intel: improve diagnosticsJan Beulich2-4/+11
2020-02-11x86: drop ShortForm attributeJan Beulich2-3/+16
2020-02-11[binutils][gas] Fix build failure with -std=c89Matthew Malcomson2-2/+7
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