| Age | Commit message (Collapse) | Author | Files | Lines |
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BFIN has lots of instructions that contain "=", so "sym = expression"
is disabled for that target. This makes an exception for assignment
to dot, fixing the recent regression of ld-scripts/pr18963.
* config/tc-bfin.h (TC_EQUAL_IN_INSN): Allow assignment to dot.
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PR 25803
gas * config/obj-elf.c (obj_elf_type): Reject ifunc symbols on MIPS
targets.
* testsuite/gas/elf/elf.exp: Add MIPS targets to the list to skip
for the type-2 test.
* testsuite/gas/elf/type-noifunc.e: Update to allow for MIPS
targets running this test.
bfd * elfxx-mips.c (_bfd_mips_elf_adjust_dynamic_symbol): Replace an
abort with a more helpful error message.
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Add support for the JMP32 class of eBPF instructions.
cpu/ChangeLog
* bpf.cpu (define-cond-jump-insn): Renamed from djci.
(dcji) New version with support for JMP32
gas/ChangeLog
* testsuite/gas/bpf/bpf.exp: Run jump32 tests.
* testsuite/gas/bpf/jump32.s: New file.
* testsuite/gas/bpf/jump32.d: Likewise.
opcodes/ChangeLog
* bpf-desc.c: Regenerate.
* bpf-desc.h: Likewise.
* bpf-opc.c: Regenerate.
* bpf-opc.h: Likewise.
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Replace "after indirect near branch" with "before indirect near branch".
* doc/c-i386.texi: Correct -mlfence-before-indirect-branch=
documentation.
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The microblaze target header duplicates prototypes already provided by tc.h.
* config/tc-microblaze.h (md_begin, md_assemble, md_undefined_symbol,
md_show_usage, md_convert_frag, md_operand, md_number_to_chars,
md_estimate_size_before_relax, md_section_align, tc_gen_reloc,
md_apply_fix3): Delete prototypes.
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This patch removes the need for target headers to provide a custom prototype
for md_pcrel_from_section.
* tc.h (md_pcrel_from_section): Add prototype.
* config/tc-aarch64.h (md_pcrel_from_section): Remove prototype.
* config/tc-arc.h (md_pcrel_from_section): Likewise.
* config/tc-arm.h (md_pcrel_from_section): Likewise.
* config/tc-avr.h (md_pcrel_from_section): Likewise.
* config/tc-bfin.h (md_pcrel_from_section): Likewise.
* config/tc-bpf.h (md_pcrel_from_section): Likewise.
* config/tc-csky.h (md_pcrel_from_section): Likewise.
* config/tc-d10v.h (md_pcrel_from_section): Likewise.
* config/tc-d30v.h (md_pcrel_from_section): Likewise.
* config/tc-epiphany.h (md_pcrel_from_section): Likewise.
* config/tc-fr30.h (md_pcrel_from_section): Likewise.
* config/tc-frv.h (md_pcrel_from_section): Likewise.
* config/tc-iq2000.h (md_pcrel_from_section): Likewise.
* config/tc-lm32.h (md_pcrel_from_section): Likewise.
* config/tc-m32c.h (md_pcrel_from_section): Likewise.
* config/tc-m32r.h (md_pcrel_from_section): Likewise.
* config/tc-mcore.h (md_pcrel_from_section): Likewise.
* config/tc-mep.h (md_pcrel_from_section): Likewise.
* config/tc-metag.h (md_pcrel_from_section): Likewise.
* config/tc-microblaze.h (md_pcrel_from_section): Likewise.
* config/tc-mmix.h (md_pcrel_from_section): Likewise.
* config/tc-moxie.h (md_pcrel_from_section): Likewise.
* config/tc-msp430.h (md_pcrel_from_section): Likewise.
* config/tc-mt.h (md_pcrel_from_section): Likewise.
* config/tc-or1k.h (md_pcrel_from_section): Likewise.
* config/tc-ppc.h (md_pcrel_from_section): Likewise.
* config/tc-rl78.h (md_pcrel_from_section): Likewise.
* config/tc-rx.h (md_pcrel_from_section): Likewise.
* config/tc-s390.h (md_pcrel_from_section): Likewise.
* config/tc-sh.h (md_pcrel_from_section): Likewise.
* config/tc-xc16x.h (md_pcrel_from_section): Likewise.
* config/tc-xstormy16.h (md_pcrel_from_section): Likewise.
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The m32c target header has a duplicate entry for MD_PCREL_FROM_SECTION.
The duplication was present since the initial commit of the port.
* config/tc-m32c.h (MD_PCREL_FROM_SECTION): Delete duplicate define.
(md_pcrel_from_section): Remove duplicate prototype.
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The moxie target header uses md_pcrel_from, thus the local prototype and
the macro definition for MD_PCREL_FROM_SECTION are not needed.
* config/tc-moxie.h (MD_PCREL_FROM_SECTION): Delete define.
(md_pcrel_from): Remove prototytpe.
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* NEWS: Mention support for Intel SERIALIZE and TSXLDTRK
instructions.
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Fix
gas/doc/c-z80.texi:244: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:278: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:284: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:291: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:295: warning: `.' or `,' must follow @xref, not )
* doc/c-z80.texi: Fix @xref warnings.
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gas/
* config/tc-i386.c (cpu_arch): Add .TSXLDTRK.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document TSXLDTRK.
* testsuite/gas/i386/i386.exp: Run TSXLDTRK tests.
* testsuite/gas/i386/tsxldtrk.d: Likewise.
* testsuite/gas/i386/tsxldtrk.s: Likewise.
* testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
(prefix_table): New instructions (see prefixes above).
(rm_table): Likewise.
* i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
CPU_ANY_TSXLDTRK_FLAGS.
(cpu_flags): Add CpuTSXLDTRK.
* i386-opc.h (enum): Add CpuTSXLDTRK.
(i386_cpu_flags): Add cputsxldtrk.
* i386-opc.tbl: Add XSUSPLDTRK insns.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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gas/
* config/tc-i386.c (cpu_arch): Add .serialize.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document serialize.
* testsuite/gas/i386/i386.exp: Run serialize tests
* testsuite/gas/i386/serialize.d: Likewise.
* testsuite/gas/i386/x86-64-serialize.d: Likewise.
* testsuite/gas/i386/serialize.s: Likewise.
opcodes/
* i386-dis.c (prefix_table): New instructions serialize.
* i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
CPU_ANY_SERIALIZE_FLAGS.
(cpu_flags): Add CpuSERIALIZE.
* i386-opc.h (enum): Add CpuSERIALIZE.
(i386_cpu_flags): Add cpuserialize.
* i386-opc.tbl: Add SERIALIZE insns.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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A couple of ld ifunc tests currently FAIL on 64-bit Solaris/x86:
FAIL: ld-ifunc/ifunc-10-x86-64
FAIL: ld-ifunc/ifunc-11-x86-64
FAIL: ld-ifunc/ifunc-12-x86-64
FAIL: ld-ifunc/ifunc-13-x86-64
FAIL: ld-ifunc/ifunc-14a-x86-64
FAIL: ld-ifunc/ifunc-14b-x86-64
FAIL: ld-ifunc/ifunc-14c-x86-64
FAIL: ld-ifunc/ifunc-14d-x86-64
FAIL: ld-ifunc/ifunc-14e-x86-64
FAIL: ld-ifunc/ifunc-14f-x86-64
FAIL: ld-ifunc/ifunc-15-x86-64
FAIL: ld-ifunc/ifunc-17a-x86-64
FAIL: ld-ifunc/ifunc-17b-x86-64
FAIL: ld-ifunc/ifunc-2-local-x86-64-now
FAIL: ld-ifunc/ifunc-2-local-x86-64
FAIL: ld-ifunc/ifunc-2-x86-64-now
FAIL: ld-ifunc/ifunc-2-x86-64
FAIL: ld-ifunc/ifunc-20-x86-64
FAIL: ld-ifunc/pr17154-x86-64-now
FAIL: ld-ifunc/pr17154-x86-64
For one, the actual error is weird:
./ld-new: target elf64-x86-64 not found
failed with: <./ld-new: target elf64-x86-64 not found>, no expected output
FAIL: ld-ifunc/ifunc-10-x86-64
although ld -V does report the elf_x86_64 emulation as supported:
$ ./ld/ld-new -V
GNU ld (GNU Binutils) 2.34.50.20200328
Supported emulations:
elf_x86_64_sol2
elf_x86_64
[...]
When using ld -m elf_x86_64_sol2 instead, one of the testcases links
successfully.
However, there's no point in pursuing this: Solaris does not support
ifunc, as can be seen in <sys/elf.h>:
/*
* GNU/Linux specific symbol type not used by Solaris
*/
#define STT_GNU_IFUNC 10
and never will, given that it has symbol capabilities as solution to
effectively the same problem:
http://www.linker-aliens.org/blogs/rie/entry/symbol_capabilitie/
Therefore this patch disables ifunc testing on Solaris completely by
removing Solaris from binutils/testsuite/lib/binutils-common.exp
(supports_gnu_osabi). The ifunc part is justified above. SHF_GNU_MBIND is
in the OS-specific range and conflicts with
#define SHF_SUNW_REALLOC 0x01000000 /* internal: krtld realloc */
While the comment suggests this might be relocatable without too much
problems, the description of mbind (no formal spec AFAICS, just the
comment in the binutils patch submission) strongly suggests that this
isn't relevant to Solaris at all.
Indirectly, clearing supports_gnu_osabi on Solaris disables
supports_gnu_unique. Again, Solaris <sys/elf.h> has
/*
* GNU/Linux specific binding not used by Solaris
*/
#define STB_GNU_UNIQUE 10
so this seems the right thing to do.
Afterwards, one can remove the explicit mentions of *-*-solaris2* in
quite a number of (but not all) the ld-ifunc dump file notarget lists.
There's one fallout, though: two gas tests now XPASS because they are
xfail'ed for !supports_gnu_osabi:
XPASS: mbind sections 12
XPASS: mbind section contents 16
XPASS: mbind sections 16
XPASS: mbind section contents 16
To fix that, I've changed
#xfail: ![supports_gnu_osabi]
to notarget.
Tested on x86_64-pc-solaris2.11, i386-pc-solaris2.11,
x86_64-pc-linux-gnu, and i686-pc-linux-gnu.
ld:
* testsuite/ld-ifunc/ifunc-10-i386.d: Remove *-*-solaris2* from
notarget.
* ifunc-11-i386.d: Likewise.
* ifunc-12-i386.d: Likewise.
* ifunc-13-i386.d: Likewise.
* ifunc-14a-i386.d: Likewise.
* ifunc-14b-i386.d: Likewise.
* ifunc-14c-i386.d: Likewise.
* ifunc-14d-i386.d: Likewise.
* ifunc-14e-i386.d: Likewise.
* ifunc-14f-i386.d: Likewise.
* ifunc-15-i386.d: Likewise.
* ifunc-16-i386-now.d: Likewise.
* ifunc-16-i386.d: Likewise.
* ifunc-17a-i386.d: Likewise.
* ifunc-17b-i386.d: Likewise.
* ifunc-18a-i386.d: Likewise.
* ifunc-18b-i386.d: Likewise.
* ifunc-19a-i386.d: Likewise.
* ifunc-19b-i386.d: Likewise.
* ifunc-2-i386-now.d: Likewise.
* ifunc-2-i386.d: Likewise.
* ifunc-2-local-i386-now.d: Likewise.
* ifunc-2-local-i386.d: Likewise.
* ifunc-20-i386.d: Likewise.
* ifunc-21-i386.d: Likewise.
* ifunc-22-i386.d: Likewise.
* ifunc-5a-i386.d: Likewise.
* ifunc-5a-local-i386.d: Likewise.
* ifunc-5b-i386.d: Likewise.
* ifunc-5b-local-i386.d: Likewise.
* ifunc-5r-local-i386.d: Likewise.
* ifunc-6a-i386.d: Likewise.
* ifunc-6b-i386.d: Likewise.
* ifunc-7a-i386.d: Likewise.
* ifunc-7b-i386.d: Likewise.
* ifunc-8-i386.d: Likewise.
* ifunc-9-i386.d: Likewise.
* pr17154-i386-now.d: Likewise.
* pr17154-i386.d: Likewise.
* ifunc-23a-x86.d: Remove notarget.
* ifunc-24a-x86.d: Likewise.
* ifunc-25a-x86.d: Likewise.
gas:
* testsuite/gas/elf/section12a.d: Use notarget instead of xfail.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section16a.d: Likewise.
* testsuite/gas/elf/section16b.d: Likewise.
binutils:
* testsuite/lib/binutils-common.exp (supports_gnu_osabi): Don't
enable on *-*-solaris*.
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* config/tc-m68k.c (m68k_ip): Fix range check for index register
with a suppressed address register.
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Define TC_FORCE_RELOCATION_ABS to force relocation against local
absolute symbol.
PR gas/25756
* config/tc-i386.h (TC_FORCE_RELOCATION_ABS): New.
* testsuite/gas/i386/localpic.s: Add a test for relocation
against local absolute symbol.
* testsuite/gas/i386/x86-64-localpic.s: Likewise.
* testsuite/gas/i386/localpic.d: Updated.
* testsuite/gas/i386/x86-64-localpic.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
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As reported in PR gas/25732, some testcases currently FAIL on
Solaris/x86:
FAIL: x86-64 branch 2
FAIL: x86-64 branch 3
FAIL: x86-64 MPX branch
FAIL: x86-64 branch with BND prefix
FAIL: x86-64 jump
Since https://sourceware.org/ml/binutils/2019-03/msg00163.html, gas
doesn't emit R_X86_64_PLT32 as branch marker on Solaris. Since the
testsuite lacks a way to preprocess dump files, adjusted copies of the
affected dumps are now used on Solaris. Unfortunately, those dumps
weren't adapted when the original testcases were changed or other
testcases started to differ between non-Solaris and Solaris targets.
The following patch fixes that, re-syncing the affected dump files or
creating new Solaris-specific ones.
Tested on i386-pc-solaris2.11, x86_64-pc-solaris2.11,
x86_64-pc-linux-gnu, and i686-pc-linux-gnu.
PR gas/25732
* testsuite/gas/i386/solaris/x86-64-branch-2.d: New file.
* testsuite/gas/i386/solaris/x86-64-branch-3.d: New file.
* testsuite/gas/i386/solaris/x86-64-jump.d: Incorporate changes to
testsuite/gas/i386/x86-64-jump.d.
* gas/testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d:
Incorporate changes to
gas/testsuite/gas/i386/x86-64-mpx-branch-1.d.
* testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d : Incorporate
changes to testsuite/gas/i386/x86-64-mpx-branch-2.d.
* testsuite/gas/i386/x86-64-branch-2.d: Skip on *-*-solaris*.
* testsuite/gas/i386/x86-64-branch-3.d: Likewise.
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Correct an issue with commit 5496f3c635dc ("Add support for generating
DWARF-5 format directory and file name tables from the assembler.") and
remove a duplicate direct inclusion of "bignum.h" from dwarf2dbg.c that
causes a GAS compilation error:
In file included from .../gas/dwarf2dbg.c:33:
.../gas/bignum.h:42: error: redefinition of typedef 'LITTLENUM_TYPE'
.../gas/bignum.h:42: error: previous declaration of 'LITTLENUM_TYPE' was here
make[4]: *** [dwarf2dbg.o] Error 1
with some GCC versions, as this header has been already included via
"as.h" and then "flonum.h".
gas/
PR 25611
PR 25614
* dwarf2dbg.c: Do not include "bignum.h".
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gas/
* testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo.
* testsuite/gas/riscv/alias-csr.s: Likewise.
* testsuite/gas/riscv/no-aliases-csr.d: Move this
to priv-reg-pseudo-noalias.
* testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent.
* testsuite/gas/riscv/bad-csr.l: Likewise.
* testsuite/gas/riscv/bad-csr.s: Likewise.
* testsuite/gas/riscv/satp.d: Removed. Already included in priv-reg.
* testsuite/gas/riscv/satp.s: Likewise.
* testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo
csr instruction, including alias-csr testcase.
* testsuite/gas/riscv/priv-reg-pseudo.s: Likewise.
* testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all
pseudo instruction with objdump -Mno-aliases.
* testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase.
* testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise.
* testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11.
* testsuite/gas/riscv/priv-reg.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
include/
* opcode/riscv-opc.h: Update CSR to 1.11.
gdb/
* features/riscv/32bit-csr.xml: Regenerated.
* features/riscv/64bit-csr.xml: Regenerated.
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also clear the CONTENTS attribute so that named bss sections don't take up space in an object file. This can be achieved by setting the 'bss' flag in seg_info.
* config/obj-coff.c (obj_coff_section): Set the bss flag on
sections with the "b" attribute.
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Don't ignore buffer memory read failure, or malloc failure. Lots of
functions get a return status to pass these failures up the chain in
this patch.
opcodes/
* s12z-dis.c (abstract_read_memory): Don't print error on EOI.
* s12z-opc.c: Formatting.
(operands_f): Return an int.
(opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
(opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
(shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
(exg_sex_discrim): Likewise.
(create_immediate_operand, create_bitfield_operand),
(create_register_operand_with_size, create_register_all_operand),
(create_register_all16_operand, create_simple_memory_operand),
(create_memory_operand, create_memory_auto_operand): Don't
segfault on malloc failure.
(z_ext24_decode): Return an int status, negative on fail, zero
on success.
(x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
(imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
(z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
(decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
(ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
(mov_imm_opr, ld_18bit_decode, exg_sex_decode),
(loop_primitive_decode, shift_decode, psh_pul_decode),
(bit_field_decode): Similarly.
(z_decode_signed_value, decode_signed_value): Similarly. Add arg
to return value, update callers.
(x_opr_decode_with_size): Check all reads, returning NULL on fail.
Don't segfault on NULL operand.
(decode_operation): Return OP_INVALID on first fail.
(decode_s12z): Check all reads, returning -1 on fail.
gas/
* testsuite/gas/s12z/truncated.d: Update expected output.
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PR 25690
* config/tc-z80.c (md_pseudo_table): Add xdef anf xref pseudo ops.
* doc/c-z80.texi: Update documentation.
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attempts to parse corrupt input files.
PR 25633
* elf.c (_bfd_elf_copy_special_section_fields): Replace assertions
with error messages.
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PR 25641
PR 25668
PR 25633
gas Fix disassembling ED+A4/AC/B4/BC opcodes.
Fix assembling lines containing colonless label and instruction
with first operand inside parentheses.
Fix registration of unsupported by target CPU registers.
* config/tc-z80.c: See above.
* config/tc-z80.h: See above.
* testsuite/gas/z80/colonless.d: Update test.
* testsuite/gas/z80/colonless.s: Likewise.
* testsuite/gas/z80/ez80_adl_all.d: Likewise.
* testsuite/gas/z80/ez80_unsup_regs.d: Likewise.
* testsuite/gas/z80/ez80_z80_all.d: Likewise.
* testsuite/gas/z80/gbz80_unsup_regs.d: Likewise.
* testsuite/gas/z80/r800_unsup_regs.d: Likewise.
* testsuite/gas/z80/unsup_regs.s: Likewise.
* testsuite/gas/z80/z180_unsup_regs.d: Likewise.
* testsuite/gas/z80/z80.exp: Likewise.
* testsuite/gas/z80/z80_strict_unsup_regs.d: Likewise.
* testsuite/gas/z80/z80_unsup_regs.d: Likewise.
* testsuite/gas/z80/z80n_unsup_regs.d: Likewise.
opcodes * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
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As explained in the PR, the addition of MVE makes the parser strip 't' and 'e'
as suffixes when MVE is enabled. This leads to vadd and vsub in it blocks with
lt and le conditions to be initially parsed as vaddl and vsubl. This means the
operand parsing for these must allow for the same operands as the scalar vadd
and vsub. I had forgotten to do this and this patch remedies that oversight.
gas/ChangeLog:
2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25660
* config/tc-arm.c (operand_parse_code): Add OP_RNSDMQR and OP_oRNSDMQ.
(parse_operands): Handle new operand codes.
(do_neon_dyadic_long): Make shape check accept the scalar variants.
(asm_opcode_insns): Fix operand codes for vaddl and vsubl.
* testsuite/gas/arm/mve-vaddsub-it.s: New test.
* testsuite/gas/arm/mve-vaddsub-it.d: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.s: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.l: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.d: New test.
* testsuite/gas/arm/nomve-vaddsub-it.d: New test.
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* NEWS: Mention x86 assembler options for CVE-2020-0551.
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Add tests for -mlfence-after-load=, -mlfence-before-indirect-branch=
and -mlfence-before-ret=.
* testsuite/gas/i386/i386.exp: Run new tests.
* testsuite/gas/i386/lfence-byte.d: New file.
* testsuite/gas/i386/lfence-byte.e: Likewise.
* testsuite/gas/i386/lfence-byte.s: Likewise.
* testsuite/gas/i386/lfence-indbr-a.d: Likewise.
* testsuite/gas/i386/lfence-indbr-b.d: Likewise.
* testsuite/gas/i386/lfence-indbr-c.d: Likewise.
* testsuite/gas/i386/lfence-indbr.e: Likewise.
* testsuite/gas/i386/lfence-indbr.s: Likewise.
* testsuite/gas/i386/lfence-load.d: Likewise.
* testsuite/gas/i386/lfence-load.s: Likewise.
* testsuite/gas/i386/lfence-ret-a.d: Likewise.
* testsuite/gas/i386/lfence-ret-b.d: Likewise.
* testsuite/gas/i386/lfence-ret.s: Likewise.
* testsuite/gas/i386/x86-64-lfence-byte.d: Likewise.
* testsuite/gas/i386/x86-64-lfence-byte.e: Likewise.
* testsuite/gas/i386/x86-64-lfence-byte.s: Likewise.
* testsuite/gas/i386/x86-64-lfence-indbr-a.d: Likewise.
* testsuite/gas/i386/x86-64-lfence-indbr-b.d: Likewise.
* testsuite/gas/i386/x86-64-lfence-indbr-c.d: Likewise.
* testsuite/gas/i386/x86-64-lfence-indbr.e: Likewise.
* testsuite/gas/i386/x86-64-lfence-indbr.s: Likewise.
* testsuite/gas/i386/x86-64-lfence-load.d: Likewise.
* testsuite/gas/i386/x86-64-lfence-load.s: Likewise.
* testsuite/gas/i386/x86-64-lfence-ret-a.d: Likewise.
* testsuite/gas/i386/x86-64-lfence-ret-b.d: Likewise.
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Add 3 command-line options to generate lfence for load, indirect near
branch and ret to help mitigate:
https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00334.html
http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2020-0551
1. -mlfence-after-load=[no|yes]:
-mlfence-after-load=yes generates lfence after load instructions.
2. -mlfence-before-indirect-branch=[none|all|memory|register]:
a. -mlfence-before-indirect-branch=all generates lfence before indirect
near branches via register and a warning before indirect near branches
via memory.
b. -mlfence-before-indirect-branch=memory issue a warning before
indirect near branches via memory.
c. -mlfence-before-indirect-branch=register generates lfence before
indirect near branches via register.
Note that lfence won't be generated before indirect near branches via
register with -mlfence-after-load=yes since lfence will be generated
after loading branch target register.
3. -mlfence-before-ret=[none|or|not]
a. -mlfence-before-ret=or generates or with lfence before ret.
b. -mlfence-before-ret=not generates not with lfence before ret.
A warning will be issued and lfence won't be generated before indirect
near branch and ret if the previous item is a prefix or a constant
directive, which may be used to hardcode an instruction, since there
is no clear instruction boundary.
* config/tc-i386.c (lfence_after_load): New.
(lfence_before_indirect_branch_kind): New.
(lfence_before_indirect_branch): New.
(lfence_before_ret_kind): New.
(lfence_before_ret): New.
(last_insn): New.
(load_insn_p): New.
(insert_lfence_after): New.
(insert_lfence_before): New.
(md_assemble): Call insert_lfence_before and insert_lfence_after.
Set last_insn.
(OPTION_MLFENCE_AFTER_LOAD): New.
(OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH): New.
(OPTION_MLFENCE_BEFORE_RET): New.
(md_longopts): Add -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
(md_parse_option): Handle -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
(md_show_usage): Display -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
(i386_cons_align): New.
* config/tc-i386.h (i386_cons_align): New.
(md_cons_align): New.
* doc/c-i386.texi: Document -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
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from the assembler.
PR 25611
PR 25614
* dwarf.h (DWARF2_Internal_LineInfo): Add li_address_size and
li_segment_size fields.
* dwarf.c (read_debug_line_header): Record the address size and
segment selector size values (if present) in the lineinfo
structure.
(display_formatted_table): Warn if the format count is empty but
the table itself is not empty.
Display the format count and entry count at the start of the table
dump.
(display_debug_lines_raw): Display the address size and segement
selector size fields, if present.
* testsuite/binutils-all/dw5.W: Update expected output.
gas * dwarf2dbg.c (DWARF2_FILE_TIME_NAME): Default to -1.
(DWARF2_FILE_SIZE_NAME): Default to -1.
(DWARF2_LINE_VERSION): Default to the current dwarf level or 3,
whichever is higher.
(DWARF2_LINE_MAX_OPS_PER_INSN): Provide a default value of 1.
(NUM_MD5_BYTES): Define.
(struct file entry): Add md5 field.
(get_filenum): Delete and replace with...
(get_basename): New function.
(get_directory_table_entry): New function.
(allocate_filenum): New function.
(allocate_filename_to_slot): New function.
(dwarf2_where): Use new functions.
(dwarf2_directive_filename): Add support for extended .file
pseudo-op.
(dwarf2_directive_loc): Allow the use of file number zero with
DWARF 5 or higher.
(out_file_list): Rename to...
(out_dir_and_file_list): Add DWARF 5 support.
(out_debug_line): Emit extra values into the section header for
DWARF 5.
(out_debug_str): Allow for file 0 to be used with DWARF 5.
* doc/as.texi (.file): Update the description of this pseudo-op.
* testsuite/gas/elf-dwarf-5-file0.s: Add more lines.
* testsuite/gas/elf-dwarf-5-file0.d: Update expected dump output.
* testsuite/gas/lns/lns-diag-1.l: Update expected error message.
* NEWS: Mention the new feature.
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* config/tc-csky.c (get_operand_value): Rewrite 1 << 31 expressions
to avoid signed overflow.
* config/tc-mcore.c (md_assemble): Likewise.
* config/tc-mips.c (gpr_read_mask, gpr_write_mask): Likewise.
* config/tc-nds32.c (SET_ADDEND): Likewise.
* config/tc-nios2.c (nios2_assemble_arg_R): Likewise.
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These all follow an almost common pattern, again with the exception of
being commutative, which can be easily taken care of.
Note that, as an intended side effect (and in fact one of the reason to
introduce templates), AVX long-form pseudo-ops get introduced alongside
the already existing AVX512 ones.
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Fixes a fail on hppa64-hp-hpux, where anything in the first column is
a label.
* testsuite/gas/elf/dwarf-5-file0.s: Don't start directives in
first column.
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PR 25614
* dwarf2dbg.c (dwarf2_directive_filename): Allow a file number of
0 if the dwarf_level is 5 or more. Complain if a filename follows
a file 0.
* testsuite/gas/elf/dwarf-5-file0.s: New test.
* testsuite/gas/elf/dwarf-5-file0.d: New test driver.
* testsuite/gas/elf/elf.exp: Run the new test.
PR 25612
* config/tc-ia64.h (DWARF2_VERISION): Fix typo.
* doc/as.texi: Fix another typo.
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PR 25612
* as.c (dwarf_level): Define.
(show_usage): Add --gdwarf-3, --gdwarf-4 and --gdwarf-5.
(parse_args): Add support for the new options.
as.h (dwarf_level): Prototype.
* dwarf2dbg.c (DWARF2_VERSION): Use dwarf_level as default version
value.
* config/tc-ia64.h (DWARF2_VERISION): Update definition.
(DWARF2_LINE_VERSION): Remove definition.
* doc/as.texi: Document the new options.
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same, if neither of them are regular files.
PR 25572
* as.c (main): Allow matching input and outputs when they are
not regular files.
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Presumably as a result of various changes over the last several months,
and - for some of them - with a generalization of logic in
match_mem_size() plus mirroring of this generalization into the
broadcast handling logic of check_VecOperands(), various register-only
templates can be foled into their respective memory forms. This in
particular then also allows dropping a few more instances of IgnoreSize.
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Even after commit dc2be329b950 ("i386: Only check suffix in instruction
mnemonic"), by which many of its uses have become unnecessary (some were
unnecessary even before), IgnoreSize is still used for various slightly
different purposes:
- to suppress emission of an operand size prefix,
- in Intel syntax mode to zap "derived" suffixes in certain cases and to
skip certain checks of remaining "derived" suffixes,
- to suppress ambiguous operand size / missing suffix diagnostics,
- for prefixes to suppress the "stand-alone ... prefix" warning.
Drop entirely unnecessary ones and where possible also replace instances
by the more focused (because of having just a single purpose) NoRex64.
To further restrict when IgnoreSize is needed, also generalize the logic
when to skip a template because of a present or derived L or Q suffix,
by skipping immediate operands. Additionally consider mask registers and
VecSIB there.
Note that for the time being the attribute needs to be kept in place on
MMX/SSE/etc insns (but not on VEX/EVEX encoded ones unless an operand
template of them allows for only non-SIMD-register actuals) allowing for
Dword operands - the logic when to emit a data size prefix would need
further adjustment first.
Note also that the memory forms of {,v}pinsrw get their permission for
an L or Q suffix dropped. I can only assume that it being this way was a
cut-and-paste mistake from the register forms, as the latter
specifically have NoRex64 set, and the {,v}pextrw counterparts don't
allow these suffixes either.
Convert VexW= again to their respective VexW* on lines touched anyway.
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The Q and L suffix exclusion checks in match_template() ought to be
(kept) in sync as far as their FPU and SIMD aspects go. This was
already violated by only the Q one checking for active broadcast.
Convert the code such that there'll be only one instance of the logic,
the more that subsequently the logic is liable to need further
refinement / extension. (The alternative would be to drop all SIMD-ness
from the L part, but it is in principle possible to enable all sorts of
SIMD support with just a pre-386 CPU, via suitable .arch directives.)
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When the template specifies any of the possible VexW settings, we can
use this instead of a separate NoRex64 to suppress the setting of REX_W.
Note that this ends up addressing an inconsistency between VEX- and
EVEX-encoded VEXTRACTPS, VPEXTR{B,W}, and VPINSR{B,W} - while the former
avoided setting VEX.W, the latter pointlessly set EVEX.W when there is a
64-bit GPR operand. Adjust the testcase to cover both cases.
Convert VexW= to their respective VexW* on lines touched anyway.
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It is almost entirely redundant with Size64, and the sole case (CRC32)
where direct replacement isn't possible can easily be taken care of in
another way.
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Since 16-bit addressing isn't allowed, Disp32 needs to be forced; Disp16
fails to match the templates.
The SDM leaves open whether BNDC[LNU] with a GPR operand require an
operand size override; this aspect is therefore left untouched here.
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For proper code generation in 16-bit mode (or to avoid the "same type of
prefix used twice" diagnostic there), IgnoreSize is needed on certain
templates allowing for just 32-(and maybe 64-)bit operands.
Beyond adding tests for the previously broken cases, also add ones for
the previously working cases where IgnoreSize is needed for the same
reason (leaving out MPX for now, as that'll require an assembler change
first). Some minor adjustments to tests get done such that re-use of the
same code for 16-bit code generation testing becomes easier.
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Allowing 64-bit registers is misleading here: Elsewhere these get allowed
when there's no difference between either variant, because of 32-bit
destination registers having their upper halves zeroed in 64-bit mode.
Here, however, they're source registers, and hence specifying 64-bit
registers would lead to the ambiguity of whether the upper 32 bits
actually matter.
Additionally, for proper code generation in 16-bit mode, IgnoreSize is
needed on both.
And finally, just like for e.g. MONITOR/MWAIT, add variants with all
input registers explicitly specified.
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gas/
* config/tc-riscv.c: Support the modifier %got_pcrel_hi.
* doc/c-riscv.texi: Add documentation.
* testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new
modifier %got_pcrel_hi.
* testsuite/gas/riscv/no-relax-reloc.s: Likewise.
* testsuite/gas/riscv/relax-reloc.d: Likewise.
* testsuite/gas/riscv/relax-reloc.s: Likewise.
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gas/
* doc/c-riscv.texi (relocation modifiers): Add documentation.
(RISC-V-Formats): Update the section name from "Instruction Formats"
to "RISC-V Instruction Formats".
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instruction is detected in a section with insufficient alignment.
* config/tc-arm.c (md_apply_fix): Warn if a PC-relative load is
detected in a section which does not have at least 4 byte
alignment.
* testsuite/gas/arm/armv8-ar-it-bad.s: Add alignment directive.
* testsuite/gas/arm/ldr-t.s: Likewise.
* testsuite/gas/arm/sp-pc-usage-t.s: Likewise.
* testsuite/gas/arm/sp-pc-usage-t.d: Finish test at end of
disassembly, ignoring any NOPs that may have been inserted because
of section alignment.
* testsuite/gas/arm/ldr-t.d: Likewise.
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It has been publicly documented for quite some time, albeit not in the
"General-Purpose and System Instructions" volume:
https://www.amd.com/system/files/TechDocs/24593.pdf.
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Since an instruction template can't have both IgnoreSize and DefaultSize,
this patch replaces IgnoreSize and DefaultSize with MnemonicSize.
gas/
* config/tc-i386.c (match_template): Replace ignoresize and
defaultsize with mnemonicsize.
(process_suffix): Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
with MnemonicSize.
* i386-opc.h (IGNORESIZE): New.
(DEFAULTSIZE): Likewise.
(IgnoreSize): Removed.
(DefaultSize): Likewise.
(MnemonicSize): New.
(i386_opcode_modifier): Replace ignoresize/defaultsize with
mnemonicsize.
* i386-opc.tbl (IgnoreSize): New.
(DefaultSize): Likewise.
* i386-tbl.h: Regenerated.
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disassemble of this and LD (HL),IX instruction. Also it update testsuit.
PR 25627
opcodes * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
instructions.
gas * config/tc-z80.c (emit_ld_rr_m): Fix invalid compilation of
instruction LD IY,(HL).
* testsuite/gas/z80/ez80_adl_all.d: Update expected disassembly.
* testsuite/gas/z80/ez80_adl_all.s: Add tests of the instruction.
* testsuite/gas/z80/ez80_z80_all.d: Update expected disassembly.
* testsuite/gas/z80/ez80_z80_all.s: Add tests of the instruction.
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According to gas manual, suffix in instruction mnemonics isn't always
required:
When there is no sizing suffix and no (suitable) register operands to
deduce the size of memory operands, with a few exceptions and where long
operand size is possible in the first place, operand size will default
to long in 32- and 64-bit modes.
This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and
vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they
must be allowed without suffix in AT&T syntax.
gas/
PR gas/25622
* testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
x86-64-default-suffix-avx.
* testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
* testsuite/gas/i386/noreg64.d: Updated.
* testsuite/gas/i386/noreg64.l: Likewise.
* testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
* testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
* testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
opcodes/
PR gas/25622
* i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
* i386-tbl.h: Regenerated.
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According to intel SDM manual, not all compare flag-modifying instructions
are marcro-fusible with subsequent jcc instructions. For those non-fusible
instructions, -malign-branch doesn't need to align them, only jcc itself
needs to be aligned.
Here are 2 restrictions which separate macro-fusible instruction from not
Restriction 1:
If TEST/AND/CMP/ADD/SUB/INC/DEC is one of the following format:
cmp m, imm
add m, imm
sub m, imm
test m, imm
and m, imm
inc m
dec m
it is unfusible with any jcc instruction.
Restriction 2:
/* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
Note it also works for Skylake and Cascadelake.
---------------------------------------------------------------------
| JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
| ------ | ----------- | ------- | -------- |
| Jo | N | N | Y |
| Jno | N | N | Y |
| Jc/Jb | Y | N | Y |
| Jae/Jnb | Y | N | Y |
| Je/Jz | Y | Y | Y |
| Jne/Jnz | Y | Y | Y |
| Jna/Jbe | Y | N | Y |
| Ja/Jnbe | Y | N | Y |
| Js | N | N | Y |
| Jns | N | N | Y |
| Jp/Jpe | N | N | Y |
| Jnp/Jpo | N | N | Y |
| Jl/Jnge | Y | Y | Y |
| Jge/Jnl | Y | Y | Y |
| Jle/Jng | Y | Y | Y |
| Jg/Jnle | Y | Y | Y |
Update maybe_fused_with_jcc_p to check if operands of CMP like instructions
can be fused with condition jump.
* gas/config/tc-i386.h (i386_tc_frag_data): Add member mf_type.
(TC_FRAG_INIT): Init mf_type.
* gas/config/tc-i386.c (enum mf_jcc_kind): New enum.
(enum mf_cmp_kind): Ditto.
(maybe_fused_with_jcc_p): Add argument mf_cmp_p to get
mf_type of corresponding instructons, exclude unfusible
instructions.
(add_fused_jcc_padding_frag_p): Likewise.
(add_branch_padding_frag_p): Likewise.
(output_insn): Record mf_type for corresponding instructions.
(i386_macro_fusible_p): New function.
(i386_next_fusible_jcc_frag): Rename from i386_next_jcc_frag,
add argument cmp_fragP to return next fusible jcc frag only.
(i386_classify_machine_dependant_frag): Seperate macro-fusible
instructions from condition jump.
* gas/testsuite/gas/i386/align-branch-9.s: New file.
* gas/testsuite/gas/i386/align-branch-9.d: Ditto.
* gas/testsuite/gas/i386/x86-64-align-branch-9.s: Ditto.
* gas/testsuite/gas/i386/x86-64-align-branch-9.d: Ditto.
* gas/testsuite/gas/i386/i386.exp: Run new tests.
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