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AgeCommit message (Expand)AuthorFilesLines
2016-11-07X86: Properly handle bad FPU opcodeH.J. Lu3-0/+16
2016-11-04arc/nps400: Validate address type operands correctlyAndrew Burgess2-0/+46
2016-11-04S/390: Fix 16 bit pc relative relocs.Andreas Krebbel2-3/+13
2016-11-03[ARC] Fix ldbit test on 32-bit systemsGraham Markall2-7/+7
2016-11-03arc: Implement NPS-400 dcmac instructionGraham Markall2-0/+95
2016-11-03X86: Decode opcode 0x82 as opcode 0x80 in 32-bit modeH.J. Lu3-0/+25
2016-11-03[ARM] Allow MOV/MOV.W to accept all possible immediatesJiong Wang8-1/+23
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist13-0/+736
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist21-0/+1069
2016-11-01Add support for RISC-V architecture.Nick Clifton5-4/+42
2016-10-27gas/arc: Don't rely on bfd list of cpu type for cpu selectionAndrew Burgess1-0/+1
2016-10-21X86: Remove pcommit instructionH.J. Lu7-80/+0
2016-10-20Check invalid mask registersH.J. Lu3-0/+23
2016-10-19[GAS][ARM]Generate unpredictable warning for pc used in data processing instr...Renlin Li3-0/+80
2016-10-17Fixed matching in newly added test.Cupertino Miranda1-1/+1
2016-10-17Removed pseudo invalid instructions opcodes.Cupertino Miranda2-0/+16
2016-10-14[ARC] Disassembler: fix LIMM detection for short instructions.Claudiu Zissulescu4-0/+40
2016-10-11Enhance objdump so that it will use .got, .plt and .plt.got section symbols w...Nick Clifton1-2/+2
2016-10-11[AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudoJiong Wang1-17/+17
2016-10-10MIPS64: Adjust cfi* testcases.Andreas Krebbel9-17/+17
2016-10-07[AArch64] PR target/20667, fix disassembler for the "special" optional SYS_Rt...Jiong Wang2-0/+155
2016-10-06[ARC] Fix parsing leave_s and enter_s mnemonics.Claudiu Zissulescu4-0/+58
2016-10-06Refine .cfi_sections check to only consider compact eh_frameMatthew Fortune3-0/+28
2016-09-30[AArch64] PR target/20553, fix opcode mask for SIMD multiply by elementJiong Wang2-0/+15
2016-09-29Add .cfi_val_offset GAS command.Andreas Krebbel3-0/+30
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra2-3/+3
2016-09-21[AArch64] Print spaces after commas in addressesRichard Sandiford14-9611/+9611
2016-09-21[AArch64] Use "must" rather than "should" in error messagesRichard Sandiford4-76/+76
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford9-44/+178
2016-09-21Fix misplaced ChangeLogRichard Sandiford1-11/+0
2016-09-21[AArch64][SVE 32/32] Add SVE testsRichard Sandiford15-0/+79428
2016-09-21[AArch64][SVE 12/32] Remove boolean parameters from parse_address_mainRichard Sandiford2-0/+20
2016-09-21[AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interfaceRichard Sandiford3-233/+238
2016-09-21[AArch64][SVE 09/32] Improve error messages for invalid floatsRichard Sandiford2-0/+9
2016-09-16[ARC] Disassemble correctly extension instructions.Claudiu Zissulescu2-0/+22
2016-09-15gas: run the sparc test dcti-couples-v9 only in ELF targets.Jose E. Marchesi1-1/+1
2016-09-14Modify POWER9 support to match final ISA 3.0 documentation.Peter Bergner2-65/+11
2016-09-14gas: detect DCTI couples in sparcJose E. Marchesi7-0/+45
2016-09-14[ARC] Fix parsing dtpoff relocation expression.Claudiu Zissulescu2-0/+22
2016-09-12S/390: Fix kmctr instruction type.Patrick Steuer1-1/+1
2016-09-07X86: Allow additional ISAs for IAMCU in assemblerH.J. Lu9-9/+32
2016-08-26opcodes, gas: fix mnemonic of sparc camellia_flJose E. Marchesi2-2/+2
2016-08-26Add missing ARMv8-M special registersThomas Preud'homme4-48/+296
2016-08-25Remove _S version of ARM MSR/MRS special registersThomas Preud'homme4-32/+0
2016-08-24X86: Add ptwrite instructionH.J. Lu7-0/+115
2016-08-19ARM: Issue a warning when the MRRC and MRRC2 instructions are used with the s...Tamar Christina3-0/+36
2016-08-19Place .shstrtab section after .symtab and .strtab, thus restoring monotonical...Nick Clifton21-85/+85
2016-08-11[AArch64] Reject -0.0 as an 8-bit FP immediateRichard Sandiford2-1/+25
2016-08-05Ensure ARM VPUSH and VPOP instructions do not affect more than 16 registers.Nick Clifton3-0/+27
2016-08-05Fix the generation of alignment frags in code sections for AArch64.Nick Clifton2-0/+41
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