| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-11-07 | RISC-V: Remove RV32EF conflict | Tsukasa OI | 2 | -5/+0 |
| 2022-11-04 | x86: adjust recently introduced testcases | Jan Beulich | 8 | -0/+8 |
| 2022-11-04 | Support Intel AVX-NE-CONVERT | konglin1 | 7 | -0/+1018 |
| 2022-11-02 | RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment. | Nelson Chu | 3 | -9/+31 |
| 2022-11-02 | Support Intel MSRLIST | Hu, Lin1 | 6 | -0/+42 |
| 2022-11-02 | Support Intel WRMSRNS | Hu, Lin1 | 6 | -0/+39 |
| 2022-11-02 | Support Intel CMPccXADD | Haochen Jiang | 6 | -0/+812 |
| 2022-11-02 | Support Intel AVX-VNNI-INT8 | Cui,Lili | 7 | -0/+542 |
| 2022-11-02 | Support Intel AVX-IFMA | Hongyu Wang | 12 | -12/+245 |
| 2022-11-01 | opcodes/arm: use '@' consistently for the comment character | Andrew Burgess | 121 | -2291/+2291 |
| 2022-10-31 | x86: Silence GCC 12 warning on tc-i386.c | H.J. Lu | 1 | -4/+4 |
| 2022-10-31 | Support Intel PREFETCHI | Cui, Lili | 10 | -0/+91 |
| 2022-10-31 | RX assembler: switch arguments of thw MVTACGU insn. | Yoshinori Sato | 1 | -4/+4 |
| 2022-10-29 | RISC-V: Always generate mapping symbols at the start of the sections. | Nelson Chu | 2 | -28/+0 |
| 2022-10-28 | RISC-V: Output mapping symbols with ISA string. | Nelson Chu | 22 | -291/+273 |
| 2022-10-27 | PowerPC: Add support for RFC02658 - MMA+ Outer-Product Instructions | Peter Bergner | 3 | -0/+80 |
| 2022-10-27 | PowerPC: Add support for RFC02653 - Dense Math Facility | Peter Bergner | 5 | -64/+258 |
| 2022-10-27 | re: Support Intel AMX-FP16 | Alan Modra | 2 | -0/+2 |
| 2022-10-24 | x86: consolidate VPCLMUL tests | Jan Beulich | 15 | -268/+156 |
| 2022-10-24 | x86: consolidate VAES tests | Jan Beulich | 15 | -352/+211 |
| 2022-10-24 | x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns | Jan Beulich | 31 | -361/+361 |
| 2022-10-21 | Support Intel AMX-FP16 | Cui,Lili | 6 | -0/+92 |
| 2022-10-20 | x86: Check VEX/EVEX encoding before checking vector operands | H.J. Lu | 4 | -0/+4 |
| 2022-10-20 | x86: re-work AVX-VNNI support | Jan Beulich | 6 | -6/+36 |
| 2022-10-19 | aarch64-pe support for LD, GAS and BFD | Jedidiah Thompson | 3 | -0/+31 |
| 2022-10-17 | Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp} | CaiJingtao | 5 | -205/+566 |
| 2022-10-16 | PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many | Alan Modra | 4 | -0/+15 |
| 2022-10-14 | PowerPC SPE disassembly and tests | Alan Modra | 4 | -14/+11 |
| 2022-10-14 | e200 LSP support | Alan Modra | 3 | -7/+3 |
| 2022-10-14 | RISC-V: Imply 'Zicsr' from privileged extensions with CSRs | Tsukasa OI | 1 | -0/+6 |
| 2022-10-14 | RISC-V: Test DWARF register number for "fp" | Tsukasa OI | 2 | -0/+4 |
| 2022-10-05 | x86/gas: support quoted address scale factor in AT&T syntax | Jan Beulich | 3 | -0/+16 |
| 2022-10-05 | Arm64: support CLEARBHB alias | Jan Beulich | 2 | -1/+3 |
| 2022-10-04 | RISC-V/gas: allow generating up to 176-bit instructions with .insn | Jan Beulich | 6 | -4/+56 |
| 2022-10-03 | RISC-V: Assign DWARF numbers to vector registers | Tsukasa OI | 2 | -2/+70 |
| 2022-10-03 | RISC-V: Add testcase for DWARF register numbers | Tsukasa OI | 2 | -0/+296 |
| 2022-09-30 | RISC-V: Relax "fmv.[sdq]" requirements | Tsukasa OI | 6 | -0/+6 |
| 2022-09-30 | RISC-V: Reorganize and enhance 'Zfinx' tests | Tsukasa OI | 6 | -106/+207 |
| 2022-09-30 | RISC-V: fallout from "re-arrange opcode table for consistent alias handling" | Jan Beulich | 4 | -14/+14 |
| 2022-09-30 | RISC-V: drop stray INSN_ALIAS flags | Jan Beulich | 2 | -0/+35 |
| 2022-09-30 | RISC-V: re-arrange opcode table for consistent alias handling | Jan Beulich | 21 | -159/+375 |
| 2022-09-30 | x86: improve match_template()'s diagnostics | Jan Beulich | 6 | -36/+36 |
| 2022-09-30 | x86/Intel: restrict suffix derivation | Jan Beulich | 4 | -0/+145 |
| 2022-09-23 | RISC-V: Add Zawrs ISA extension support | Christoph Müllner | 3 | -0/+25 |
| 2022-09-22 | RISC-V: Add T-Head MemPair vendor extension | Christoph Müllner | 5 | -0/+83 |
| 2022-09-22 | RISC-V: Add T-Head MemIdx vendor extension | Christoph Müllner | 5 | -0/+132 |
| 2022-09-22 | RISC-V: Add T-Head FMemIdx vendor extension | Christoph Müllner | 5 | -0/+80 |
| 2022-09-22 | RISC-V: Add T-Head MAC vendor extension | Christoph Müllner | 2 | -0/+22 |
| 2022-09-22 | RISC-V: Add T-Head CondMov vendor extension | Christoph Müllner | 2 | -0/+14 |
| 2022-09-22 | RISC-V: Add T-Head Bitmanip vendor extension | Christoph Müllner | 15 | -0/+126 |
