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AgeCommit message (Expand)AuthorFilesLines
2019-09-20x86-64: fix handling of PUSH/POP of segment registerJan Beulich2-2/+14
2019-09-10Enhance the disassembler so that it will reliably determine whether a reloc a...Nick Clifton2-0/+35
2019-09-10[PATCH][ARM][GAS]: Support to MVE VCTP instruction.Srinath Parvathaneni5-0/+136
2019-08-30[PATCH][ARM][GAS]: Assembler support to interpret MVE VMOV instruction correc...Srinath Parvathaneni2-0/+79
2019-08-27Add support for the MVE VMOV instruction to the ARM assembler. This instruct...Srinath Parvathaneni3-200/+231
2019-08-25RISC-V: Improve li expansion for better code density.Kito Cheng4-0/+75
2019-08-22Arm: Add support for missing CPUsDennis Zhang3-0/+18
2019-08-22Fix the assembler's floating point number parser so that it can correctly han...Bosco Garc?a3-0/+7
2019-08-22Implement a float16 directive for assembling 16 bit IEEE 754 floating point n...Barnaby Wilks3-0/+41
2019-08-22[AArch64][gas] Update MTE system register encodingsKyrylo Tkachov1-10/+10
2019-08-20Remove test files for a different patch accidentally committed with patch for...Nick Clifton2-35/+0
2019-08-20Adds support for following CPUs to the ARM and Aarch64 assemblers: Cortex-A77...Dennis Zhang8-0/+66
2019-08-19MIPS/gas: Retain ISA mode bit for labels with .insn annotationFaraz Shahbazker3-0/+31
2019-08-12Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions.Srinath Parvathaneni4-6/+22
2019-08-12Add generic and ARM specific support for half-precision IEEE 754 floating poi...Barnaby Wilks15-0/+124
2019-08-09x86-64: generalize SIMD test expectationsJan Beulich6-927/+201
2019-08-08Change the output of readelf's note display so that the "Data size" column he...Nick Clifton4-4/+4
2019-08-08Move the h8300 assembler's MOVFPE and MOVTPE tests to the correct location.Yoshinori Sato4-50/+49
2019-08-05Removes support in the ARM assembler for the unsigned variants of the VQ(R)DM...Barnaby Wilks10-2710/+38
2019-07-30RISC-V: Fix minor issues with FP csr instructions.Jim Wilson4-1/+61
2019-07-24[ARC] Update disassembler opcode selectionClaudiu Zissulescu1-1/+1
2019-07-24Complain about mbind, ifunc, and unique in final_writeAlan Modra2-2/+2
2019-07-24Define ELF_OSABI for visiumAlan Modra3-5/+10
2019-07-23[AArch64] Add support for GMID_EL1 register for +memtagKyrylo Tkachov3-0/+3
2019-07-23SHF_GNU_MBIND requires ELFOSABI_GNUAlan Modra4-3/+7
2019-07-23gas "mbind sections" testAlan Modra1-2/+0
2019-07-22This patch addresses the change in the June Armv8.1-M Mainline specification,...Barnaby Wilks8-132/+124
2019-07-19x86: Pass -O0 to assembler in noextreg.dH.J. Lu1-0/+1
2019-07-19cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassemblerJose E. Marchesi6-52/+52
2019-07-19[AArch64] Rename +bitperm to +sve2-bitpermRichard Sandiford5-5/+5
2019-07-17gas: support .half, .word and .dword directives in eBPFJose E. Marchesi4-0/+23
2019-07-16x86: fold SReg{2,3}Jan Beulich3-305/+9
2019-07-15cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructionsJose E. Marchesi3-12/+12
2019-07-14cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructionsJose E. Marchesi3-24/+24
2019-07-09Re: gas/ELF: don't accumulate .type settingsAlan Modra1-0/+10
2019-07-05Kito's 5-part patch set to improve .insn support.Jim Wilson2-48/+70
2019-07-04gas/ELF: don't accumulate .type settingsJan Beulich4-0/+63
2019-07-03Fix assembler tests to work with toolchains that have been configured with --...Nick Clifton92-64/+98
2019-07-02This patch fixes a bug in the AArch64 assembler where an incorrect structural...Barnaby Wilks4-1/+12
2019-07-02[AArch64] Allow MOVPRFX to be used with FMOVRichard Sandiford2-0/+25
2019-07-02[AArch64] Add missing C_MAX_ELEM flags for SVE conversionsRichard Sandiford3-7/+73
2019-07-02[AArch64] Fix bogus MOVPRFX warning for GPR form of CPYRichard Sandiford3-3/+2
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson5-10/+28
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich7-0/+396
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich11-1245/+981
2019-07-01x86: optimize EVEX packed integer logical instructionsJan Beulich21-0/+897
2019-07-01x86: add missing pseudo ops for VPCLMULQDQ ISA extensionJan Beulich18-18/+122
2019-07-01x86: warn about insns exceeding the 15-byte limitJan Beulich5-0/+104
2019-06-27This fixes a bug in the ARm assembler where an immediate operand larger than ...Barnaby Wilk s7-6/+31
2019-06-27x86: add missing testJan Beulich2-0/+174
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