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2022-08-09Another gas manual typo correction.Stepan Nemec1-1/+1
2022-08-09Fix typos in assembler documentation.Stepan Nemec1-10/+11
2022-07-20gas/symbols: introduce md_resolve_symbolDmitry Selyutin1-0/+6
Assuming GMSD is a special operand, marked as O_md1, the code: .set VREG, GMSD .set REG, VREG extsw REG, 2 ...fails upon attempts to resolve the value of the symbol. This happens since machine-dependent values are not handled in the giant op switch. We introduce a custom md_resolve_symbol macro; the ports can use this macro to customize the behavior when resolve_symbol_value hits O_md operand.
2022-07-06x86: introduce a state stack for .archJan Beulich1-1/+1
When using just slightly non-trivial combinations of .arch, it can be quite useful to be able to go back to prior state without needing to re-invoke perhaps many earlier directives and without needing to invoke perhaps many "negative" ones. Like some other architectures allow saving (pushing) and restoring (popping) present/prior state. For now require the same .code<N> to be in effect for ".arch pop" that was in effect for the corresponding ".arch push". Also change the global "no_cond_jump_promotion" to be bool, to match the new struct field.
2022-07-06x86: permit "default" with .archJan Beulich1-1/+2
So far there was no way to reset the architecture to that assembly would start with in the absence of any overrides (command line or directives). Note that for Intel MCU "default" is merely an alias of "iamcu". While there also zap a stray @item from the doc section, as noticed when inspecting the generated output (which still has some quirks, but those aren't easy to address without re-flowing almost the entire section).
2022-06-27drop XC16x bitsJan Beulich2-81/+0
Commit 04f096fb9e25 ("Move the xc16x target to the obsolete list") moved the architecture from the "obsolete but still available" to the "obsolete / support removed" list in config.bfd, making the architecture impossible to enable (except maybe via "enable everything" options"). Note that I didn't touch */po/*.po{,t} on the assumption that these would be updated by some (half)automatic means.
2022-04-07IBM zSystems: Add support for z16 as CPU name.Andreas Krebbel2-4/+4
So far z16 was identified as arch14. After the machine has been announced we can now add the real name. gas/ChangeLog: * config/tc-s390.c (s390_parse_cpu): Add z16 as alternate CPU name. * doc/as.texi: Add z16 and arch14 to CPU string list. * doc/c-s390.texi: Add z16 to CPU string list. opcodes/ChangeLog: * s390-mkopc.c (main): Enable z16 as CPU string in the opcode table.
2022-03-23gas: retain whitespace between stringsJan Beulich1-0/+21
Macro arguments may be separated by commas or just whitespace. Macro arguments may also be quoted (where one level of quotes is removed in the course of determining the values for the respective formal parameters). Furthermore this quote removal knows _two_ somewhat odd escaping mechanisms: One, apparently in existence forever, is that a pair of quotes counts as the escaping of a quote, with the pair being transformed to a single quote in the course of quote removal. The other (introduced by c06ae4f232e6) looks more usual on the surface in that it deals with \" sequences, but it _retains_ the escaping \. Hence only the former mechanism is suitable when the value to be used by the macro body is to contain a quote. Yet this results in ambiguity of what "a""b" is intended to mean; elsewhere (e.g. for .ascii) it represents two successive string literals. However, in any event is the above different from "a" "b": I don't think this can be viewed the same as "a""b" when processing macro arguments. Change the scrubber to retain such whitespace, by making the processing of strings more similar to that of symbols. And indeed this appears to make sense when taking into account that for quite a while gas has been supporting quoted symbol names. Taking a more general view, however, the change doesn't go quite far enough. There are further cases where significant whitespace is removed by the scrubber. The new testcase enumerates a few in its ".if 0" section. I'm afraid the only way that I see to deal with this would be to significantly simplify the scrubber, such that it wouldn't do much more than collapse sequences of unquoted whitespace into a single blank. To be honest problems in this area aren't really surprising when seeing that there's hardly any checking of .macro use throughout the testsuite (and in particular in the [relatively] generic tests under all/).
2022-03-20RISC-V: Fix misplaced @end tableAndreas Schwab1-1/+1
Move the csr-check and arch items inside the table for the .option directive.
2022-03-17x86: drop L1OM/K1OM support from gasJan Beulich1-3/+1
This was only rudimentary support anyway; none of the sub-architecture specific insns were ever supported.
2022-02-11gas/doc: Fix "a true results" typoRichard Sandiford1-1/+1
2022-01-24gas: drop old cygnus install hackMike Frysinger1-4/+0
This was needed when gas was using the automake cygnus option, but this was removed years ago by Simon in d0ac1c44885daf68f631befa37e ("Bump to autoconf 2.69 and automake 1.15.1"). So delete it here. The info pages are already & still installed by default w/out it.
2022-01-11gas/doc: mention quoted symbol namesJan Beulich1-1/+4
2022-01-02Update year range in copyright notice of binutils filesAlan Modra65-67/+67
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
2021-12-16arm: Add support for Armv8.7-A and Armv8.8-ARichard Sandiford1-0/+2
This patch adds AArch32 support for -march=armv8.[78]-a. The behaviour of the new options can be expressed using a combination of existing feature flags and tables. The cpu_arch_ver entries are technically redundant but it seemed less surprising to include them anyway. include/ * opcode/arm.h (ARM_ARCH_V8_7A, ARM_ARCH_V8_8A): New macros. gas/ * doc/c-arm.texi: Add armv8.7-a and armv8.8-a. * config/tc-arm.c (armv87a_ext_table, armv88a_ext_table): New macros. (arm_archs): Add armv8.7-a and armv8.8-a. (cpu_arch_ver): Add ARM_ARCH_V8_7A and ARM_ARCH_V8_8A. * NEWS: Mention the above. * testsuite/gas/arm/attr-march-armv8_7-a.d: New test. * testsuite/gas/arm/attr-march-armv8_8-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv8.7-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv8.8-a.d: Likewise. * testsuite/gas/arm/i8mm-armv8.7-a.d: Likewise. * testsuite/gas/arm/i8mm-armv8.8-a.d: Likewise.
2021-12-16aarch64: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford1-1/+2
This patch adds AArch64 support for -march=armv9.[123]-a. The behaviour of the new options can be expressed using a combination of existing feature flags, so we don't need to eat into the vanishing number of spare AARCH64_FEATURE_* bits. Hoewver, it was more convenient to separate out the |s of feature flags so that Armv9.1-A could reuse the set for Armv8.6-A, and so on. include/ * opcode/aarch64.h (AARCH64_ARCH_V8_FEATURES): New macro, split out from... (AARCH64_ARCH_V8): ...here. (AARCH64_ARCH_V8_1_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_1): ...here. (AARCH64_ARCH_V8_2_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_2): ...here. (AARCH64_ARCH_V8_3_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_3): ...here. (AARCH64_ARCH_V8_4_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_4): ...here. (AARCH64_ARCH_V8_5_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_5): ...here. (AARCH64_ARCH_V8_6_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_6): ...here. (AARCH64_ARCH_V8_7_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_7): ...here. (AARCH64_ARCH_V8_8_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_8): ...here. (AARCH64_ARCH_V9_FEATURES): New macro, split out from... (AARCH64_ARCH_V9): ...here. (AARCH64_ARCH_V9_1_FEATURES, AARCH64_ARCH_V9_1): New macros. (AARCH64_ARCH_V9_2_FEATURES, AARCH64_ARCH_V9_2): New macros. (AARCH64_ARCH_V9_3_FEATURES, AARCH64_ARCH_V9_3): New macros. gas/ * doc/c-aarch64.texi: Add armv9.1-a, armv9-2-a and armv9.3-a. * config/tc-aarch64.c (aarch64_archs): Likewise. * NEWS: Mention the above. * testsuite/gas/aarch64/armv9_invalid.d, testsuite/gas/aarch64/armv9_invalid.s, testsuite/gas/aarch64/armv9_invalid.l: New test. * testsuite/gas/aarch64/armv9_1.d, testsuite/gas/aarch64/armv9_1.s: Likewise. * testsuite/gas/aarch64/armv9_1_invalid.d, testsuite/gas/aarch64/armv9_1_invalid.s, testsuite/gas/aarch64/armv9_1_invalid.l: Likewise. * testsuite/gas/aarch64/armv9_2.d, testsuite/gas/aarch64/armv9_2.s: Likewise. * testsuite/gas/aarch64/armv9_2_invalid.d, testsuite/gas/aarch64/armv9_2_invalid.s, testsuite/gas/aarch64/armv9_2_invalid.l: Likewise. * testsuite/gas/aarch64/armv9_3.d, testsuite/gas/aarch64/armv9_3.s: Likewise.
2021-12-02aarch64: Add BC instructionRichard Sandiford1-0/+2
This patch adds support for the Armv8.8-A BC instruction. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions/BC-cond--Branch-Consistent-conditionally-?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_HBC): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_HBC. opcodes/ * aarch64-tbl.h (aarch64_feature_hbc): New variable. (HBC, HBC_INSN): New macros. (aarch64_opcode_table): Add BC.C. * aarch64-dis-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document +hbc. * config/tc-aarch64.c (aarch64_features): Add "hbc". * testsuite/gas/aarch64/hbc.s, testsuite/gas/aarch64/hbc.d: New test. * testsuite/gas/aarch64/hbc-invalid.s, testsuite/gas/aarch64/hbc-invalid.l, testsuite/gas/aarch64/hbc-invalid.d: New test.
2021-12-02aarch64: Add support for +mopsRichard Sandiford1-0/+2
This patch adds support for FEAT_MOPS, an Armv8.8-A extension that provides memcpy and memset acceleration instructions. I took the perhaps controversial decision to generate the individual instruction forms using macros rather than list them out individually. This becomes useful with a follow-on patch to check that code follows the correct P/M/E sequence. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS. (AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd. (AARCH64_OPND_MOPS_ADDR_Rs): Likewise. (AARCH64_OPND_MOPS_WB_Rn): Likewise. opcodes/ * aarch64-asm.h (ins_x0_to_x30): New inserter. * aarch64-asm.c (aarch64_ins_x0_to_x30): New function. * aarch64-dis.h (ext_x0_to_x30): New extractor. * aarch64-dis.c (aarch64_ext_x0_to_x30): New function. * aarch64-tbl.h (aarch64_feature_mops): New feature set. (aarch64_feature_mops_memtag): Likewise. (MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN) (MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN) (MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN) (MOPS_SET_INSN): New macros. (aarch64_opcode_table): Add MOPS instructions. (aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (verify_three_different_regs): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ * doc/c-aarch64.texi: Document +mops. * config/tc-aarch64.c (parse_x0_to_x30): New function. (parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (aarch64_features): Add "mops". * testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test. * testsuite/gas/aarch64/mops_invalid.s, * testsuite/gas/aarch64/mops_invalid.d, * testsuite/gas/aarch64/mops_invalid.l: Likewise.
2021-12-02aarch64: Add support for Armv8.8-ARichard Sandiford1-2/+2
This patch adds skeleton support for -march=armv8.8-a, testing only that it correctly inherits from armv8.7-a. include/ * opcode/aarch64.h (AARCH64_FEATURE_V8_8): New macro. (AARCH64_ARCH_V8_8): Likewise. gas/ * doc/c-aarch64.texi: Document armv8.8-a. * config/tc-aarch64.c (aarch64_archs): Add armv8-8-a * testsuite/gas/aarch64/v8-8-a.s, * testsuite/gas/aarch64/v8-8-a.d: New test.
2021-12-01gas: merge doc subdir up a levelMike Frysinger3-1118/+136
This avoids a recursive make into the doc subdir and speeds up the build slightly. It also allows for more parallelism.
2021-11-19RISC-V: Support new .option arch directive.Nelson Chu1-1/+14
https://github.com/riscv/riscv-asm-manual/pull/67 Format: .option arch, +<extension><version>, ... .option arch, -<extension> .option arch, =<ISA string> The new direcitve is used to enable/disable extensions for the specific code region. For example, .attribute arch, "rv64ic" # arch = rv64i2p0_c2p0 .option push .option arch, +d2p0, -c # arch = rv64i2p0_f2p0_d2p0, f is added implied .option arch, =rv32gc # arch = rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0 .option pop # arch = rv64i2p0_c2p0 Note that, 1. ".option rvc/norvc" have the same behavior as ".option arch +c/-c". 2. ".option arch -i" is illegal, since we cannot remove base i extension. 3. If arch=rv64i2p0, then ".option arch, +i3p0" will update the i's version from 2.0 to 3.0. 4. If arch=rv64i3p0, then ".option arch, +i" will update the i's version from 2.0 to the default one according to the chosen isa spec. bfd/ * elfxx-riscv.c (riscv_add_subset): If the subset is already added, and the new versions are not RISCV_UNKNOWN_VERSION, then update the versions to the subset list. (riscv_copy_subset): New function. Copy the subset from list. (riscv_copy_subset_list): New function. Return the new copyed list. (riscv_update_subset): Updated to make .option arch directives workable. * elfxx-riscv.h: Updated. gas/ * config/tc-riscv.c (riscv_subsets): Defined as a pointer. (riscv_rps_as): Init the subset_list to NULL, we will set it later once riscv_opts_stack is created or updated. (struct riscv_option_stack, riscv_opts_stack): Moved forward. (riscv_set_arch): Updated. (s_riscv_option): Support new .option arch directive, to add, remove or update subsets for the specific code region. (riscv_write_out_attrs): Updated. * doc/c-riscv.texi: Added document for new .option arch directive. * testsuite/gas/riscv/option-arch-01a.d: New testcase. * testsuite/gas/riscv/option-arch-01b.d: Likewise. * testsuite/gas/riscv/option-arch-01.s: Likewise.. * testsuite/gas/riscv/option-arch-02.d: Likewise. * testsuite/gas/riscv/option-arch-02.s: Likewise. * testsuite/gas/riscv/option-arch-fail.d: Likewise. * testsuite/gas/riscv/option-arch-fail.l: Likewise. * testsuite/gas/riscv/option-arch-fail.s: Likewise.
2021-11-18Add multibyte character warning option to the assembler.Nick Clifton1-4/+26
* as.c (parse_args): Add support for --multibyte-handling. * as.h (multibyte_handling): Declare. * app.c (scan_for_multibyte_characters): New function. (do_scrub_chars): Call the new function if multibyte warning is enabled. * input-scrub,c (input_scrub_next_buffer): Call the multibyte scanning function if multibyte warnings are enabled. * symbols.c (struct symbol_flags): Add multibyte_warned bit. (symbol_init): Call the multibyte scanning function if multibyte symbol warnings are enabled. (S_SET_SEGMENT): Likewise. * NEWS: Mention the new feature. * doc/as.texi: Document the new feature. * testsuite/gas/all/multibyte.s: New test source file. * testsuite/gas/all/multibyte1.d: New test driver file. * testsuite/gas/all/multibyte1.l: New test expected output. * testsuite/gas/all/multibyte2.d: New test driver file. * testsuite/gas/all/multibyte2.l: New test expected output. * testsuite/gas/all/gas.exp: Run the new tests.
2021-11-17aarch64: [SME] Add +sme option to -marchPrzemyslaw Wirkus1-0/+6
This series of patches (tagged [SME]) add support for the Scalable Matrix Extension. Patch introduces new command line options: +sme, +sme-f64 and +sme-i64 to -march command line options. gas/ChangeLog: * NEWS: Updated docs. * config/tc-aarch64.c: New SME command line options. * doc/c-aarch64.texi: Update docs. include/ChangeLog: * opcode/aarch64.h (AARCH64_FEATURE_SME): New flag. (AARCH64_FEATURE_SME_F64): New flag. (AARCH64_FEATURE_SME_I64): New flag. opcodes/ChangeLog: * aarch64-tbl.h (SME): New feature object.
2021-11-15Deal with full path in .file 0 directiveEric Botcazou1-7/+10
Gas uses the directory part, if present, of the .file 0 directive to set entry 0 of the directory table in DWARF 5, which represents the "current directory". Now Gas also uses the file part of the same directive to set entry 0 of the file table, which represents the "current compilation file". But the latter need not be located in the former so GCC will use a full path in the file part when it is passed a full path: gcc -c /full/path/test.c -save-temps yields: .file 0 "/current/directory" "/full/path/test.c" in the assembly file and: The Directory Table (offset 0x22, lines 2, columns 1): Entry Name 0 (indirect line string, offset: 0x25): /current/directory 1 (indirect line string, offset: 0x38): /full/path The File Name Table (offset 0x30, lines 2, columns 2): Entry Dir Name 0 0 (indirect line string, offset: 0x43): /full/path/test.c in the object file. Note the full path and the questionable Dir value in the 0 entry of the file table.
2021-11-10arm: enable Cortex-A710 CPUPrzemyslaw Wirkus1-0/+1
This patch is adding support for Cortex-A710 CPU in Arm. bfd/ * cpu-arm.c (processors): Add cortex-a710. gas/ * NEWS: Update docs. * config/tc-arm.c (arm_cpus): Add cortex-a710 to -mcpu. * doc/c-arm.texi: Update docs. * testsuite/gas/arm/cpu-cortex-a710.d: New test.
2021-11-01arm: add armv9-a architecture to -marchPrzemyslaw Wirkus1-0/+1
Update also include: + New value of Tag_CPU_arch EABI attribute (22) is added. + Updated missing Tag_CPU_arch EABI attributes. + Updated how we combine archs 'v4t_plus_v6_m' as this mechanism have to handle new Armv9 as well. Regression tested on `arm-none-eabi` cross Binutils and no issues. bfd/ * archures.c: Define bfd_mach_arm_9. * bfd-in2.h (bfd_mach_arm_9): Define bfd_mach_arm_9. * cpu-arm.c: Add 'armv9-a' option to -march. * elf32-arm.c (using_thumb2_bl): Update assert check. (arch_has_arm_nop): Add TAG_CPU_ARCH_V9. (bfd_arm_get_mach_from_attributes): Add case for TAG_CPU_ARCH_V9. Update assert. (tag_cpu_arch_combine): Updated table. (v9): New table.. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Update with elfcpp/ * arm.h: Update TAG_CPU_ARCH_ enums with correct values. gas/ * NEWS: Update docs. * config/tc-arm.c (get_aeabi_cpu_arch_from_fset): Return Armv9-a for -amarch=all. (aeabi_set_public_attributes): Update assert. * doc/c-arm.texi: Update docs. * testsuite/gas/arm/armv9-a_arch.d: New test. * testsuite/gas/arm/attr-march-all.d: Update test with v9. include/ * elf/arm.h Update TAG_CPU_ARCH_ defines with correct values. * opcode/arm.h (ARM_EXT3_V9A): New macro. (ARM_ARCH_NONE): Updated with arm_feature_set.core size. (FPU_NONE): Updated. (ARM_ANY): Updated. (ARM_ARCH_UNKNOWN): New macro. (ARM_FEATURE_LOW): Updated. (ARM_FEATURE_CORE): Updated. (ARM_FEATURE_CORE_LOW): Updated. (ARM_FEATURE_CORE_HIGH): Updated. (ARM_FEATURE_COPROC): Updated. (ARM_FEATURE): Updated. (ARM_FEATURE_ALL): New macro. opcodes/ * arm-dis.c (select_arm_features): Support bfd_mach_arm_9. Also Update bfd_mach_arm_unknown to use new macro ARM_ARCH_UNKNOWN.
2021-10-24LoongArch gas supportliuzhensong2-0/+70
2021-10-22 Chenghua Xu <xuchenghua@loongson.cn> Zhensong Liu <liuzhensong@loongson.cn> Weinan Liu <liuweinan@loongson.cn> Xiaolin Tang <tangxiaolin@loongson.cn> gas/ * Makefile.am: Add LoongArch. * NEWS: Mention LoongArch support. * config/loongarch-lex-wrapper.c: New. * config/loongarch-lex.h: New. * config/loongarch-lex.l: New. * config/loongarch-parse.y: New. * config/tc-loongarch.c: New. * config/tc-loongarch.h: New. * configure.ac: Add LoongArch. * configure.tgt: Likewise. * doc/as.texi: Likewise. * doc/c-loongarch.texi: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. gas/testsuite/ * gas/all/gas.exp: Add LoongArch. * gas/elf/elf.exp: Likewise. * gas/loongarch/4opt_op.d: New. * gas/loongarch/4opt_op.s: Likewise. * gas/loongarch/fix_op.d: Likewise. * gas/loongarch/fix_op.s: Likewise. * gas/loongarch/float_op.d: Likewise. * gas/loongarch/float_op.s: Likewise. * gas/loongarch/imm_op.d: Likewise. * gas/loongarch/imm_op.s: Likewise. * gas/loongarch/jmp_op.d: Likewise. * gas/loongarch/jmp_op.s: Likewise. * gas/loongarch/load_store_op.d: Likewise. * gas/loongarch/load_store_op.s: Likewise. * gas/loongarch/loongarch.exp: Likewise. * gas/loongarch/macro_op.d: Likewise. * gas/loongarch/macro_op.s: Likewise. * gas/loongarch/nop.d: Likewise. * gas/loongarch/nop.s: Likewise. * gas/loongarch/privilege_op.d: Likewise. * gas/loongarch/privilege_op.s: Likewise. * gas/loongarch/syscall.d: Likewise. * gas/loongarch/syscall.s: Likewise. * lib/gas-defs.exp: Add LoongArch.
2021-10-22x86: Add -muse-unaligned-vector-move to assemblerH.J. Lu1-0/+6
Unaligned load/store instructions on aligned memory or register are as fast as aligned load/store instructions on modern Intel processors. Add a command-line option, -muse-unaligned-vector-move, to x86 assembler to encode encode aligned vector load/store instructions as unaligned vector load/store instructions. * NEWS: Mention -muse-unaligned-vector-move. * config/tc-i386.c (use_unaligned_vector_move): New. (encode_with_unaligned_vector_move): Likewise. (md_assemble): Call encode_with_unaligned_vector_move for -muse-unaligned-vector-move. (OPTION_MUSE_UNALIGNED_VECTOR_MOVE): New. (md_longopts): Add -muse-unaligned-vector-move. (md_parse_option): Handle -muse-unaligned-vector-move. (md_show_usage): Add -muse-unaligned-vector-move. * doc/c-i386.texi: Document -muse-unaligned-vector-move. * testsuite/gas/i386/i386.exp: Run unaligned-vector-move and x86-64-unaligned-vector-move. * testsuite/gas/i386/unaligned-vector-move.d: New file. * testsuite/gas/i386/unaligned-vector-move.s: Likewise. * testsuite/gas/i386/x86-64-unaligned-vector-move.d: Likewise.
2021-10-01Fix mistake in RX assembler documentation (special section names)Nick Clifton1-2/+2
2021-09-30arm: enable Cortex-R52+ CPUPrzemyslaw Wirkus1-0/+1
Patch is adding Cortex-R52+ as 'cortex-r52plus' command line flag for -mcpu option. bfd/ * cpu-arm.c: New Cortex-R52+ CPU. gas/ * NEWS: Update docs. * config/tc-arm.c: New Cortex-R52+ CPU. * doc/c-arm.texi: Update docs. * testsuite/gas/arm/cpu-cortex-r52plus.d: New test.
2021-09-30aarch64: Enable Cortex-X2 CPUPrzemyslaw Wirkus1-1/+2
This patch is adding support for Cortex-X2 CPU. gas: * NEWS: Update docs. * config/tc-aarch64.c: Add Cortex-X2. * doc/c-aarch64.texi: Update docs.
2021-09-30aarch64: Enable Cortex-A710 CPUPrzemyslaw Wirkus1-0/+1
This patch is adding support for Cortex-A710 CPU. gas/ * NEWS: Update docs. * config/tc-aarch64.c: Add Cortex-A710. * doc/c-aarch64.texi: Update docs.
2021-09-30aarch64: Enable Cortex-A510 CPUPrzemyslaw Wirkus1-0/+1
This patch is adding support for Cortex-A510 CPU. gas/ * NEWS: Update docs. * config/tc-aarch64.c: Add Cortex-A510. * doc/c-aarch64.texi: Update docs.
2021-09-30aarch64: Update AArch64 features command line options docs 2/2Przemyslaw Wirkus1-49/+52
Patch is only sorting by 'Extension` column 'Architecture Extension' table. gas/ * doc/c-aarch64.texi: Update docs.
2021-09-30aarch64: Update AArch64 features command line options docs 1/2Przemyslaw Wirkus1-7/+8
Patch is improving entries in "Architecture extensions" table in GAS documentation. gas/ * doc/c-aarch64.texi: Update docs.
2021-09-30aarch64: add armv9-a architecture to -marchPrzemyslaw Wirkus1-3/+4
Patch is adding new 'armv9-a` command line flag to -march for AArch64. gas/ * config/tc-aarch64.c: Add 'armv9-a' command line flag. * docs/c-aarch64.text: Update docs. * NEWS: Update docs. include/ * opcode/aarch64.h (AARCH64_FEATURE_V9): New define. (AARCH64_ARCH_V9): New define.
2021-08-31RISC-V: Extend .insn directive to support hardcode encoding.Nelson Chu1-2/+12
The .insn directive can let users use their own instructions, or some new instruction, which haven't supported in the old binutils. For example, if users want to use sifive cache instruction, they cannot just write "cflush.d1.l1" in the assembly code, they should use ".insn i SYSTEM, 0, x0, x10, -0x40". But the .insn directive may not easy to use for some cases, and not so friendly to users. Therefore, I believe most of the users will use ".word 0xfc050073", to encode the instructions directly, rather than use .insn. But once we have supported the mapping symbols, the .word directives are marked as data, so disassembler won't dump them as instructions as usual. I have discussed this with Kito many times, we all think extend the .insn direcitve to support the hardcode encoding, is the easiest way to resolve the problem. Therefore, there are two more .insn formats are proposed as follows, (original) .insn <type>, <operand1>, <operand2>, ... .insn <insn-length>, <value> .insn <value> The <type> is string, and the <insn-length> and <value> are constants. gas/ * config/tc-riscv.c (riscv_ip_hardcode): Similar to riscv_ip, but assembles an instruction according to the hardcode values of .insn directive. * doc/c-riscv.texi: Document two new .insn formats. * testsuite/gas/riscv/insn-fail.d: New testcases. * testsuite/gas/riscv/insn-fail.l: Likewise. * testsuite/gas/riscv/insn-fail.s: Likewise. * testsuite/gas/riscv/insn.d: Updated. * testsuite/gas/riscv/insn.s: Likewise.
2021-08-11Add a -mno-dollar-line-separator command line option to the AVR assembler.Matt Jacobson1-1/+8
Some frontends, like the gcc Objective-C frontend, emit symbols with $ characters in them. The AVR target code in gas treats $ as a line separator, so the code doesn?t assemble correctly. Provide a machine-specific option to disable treating $ as a line separator. * config/tc-avr.c (enum options): Add option flag. (struct option): Add option -mno-dollar-line-separator. (md_parse_option): Adjust treatment of $ when option is present. * config/tc-avr.h: Use avr_line_separator_chars.
2021-08-11x86: introduce .bfloat16 directiveJan Beulich1-6/+8
This is to be able to generate data acted upon by AVX512-BF16 and AMX-BF16 insns. While not part of the IEEE standard, the format is sufficiently standardized to warrant handling in config/atof-ieee.c. Arm, where custom handling was implemented, may want to leverage this as well. To be able to also use the hex forms supported for other floating point formats, a small addition to the generic hex_float() is needed. Extend existing x86 testcases.
2021-08-11x86: introduce .hfloat directiveJan Beulich1-5/+8
This is to be able to generate data passed to {,V}CVTPH2PS and acted upon by AVX512-FP16 insns. To be able to also use the hex forms supported for other floating point formats, a small addition to the generic hex_float() is needed. Extend existing x86 testcases.
2021-08-11x86/ELF: fix .ds.x outputJan Beulich1-2/+2
The ELF psABI-s are quite clear here: On 32-bit the underlying data type is 12 bytes long (with 2 bytes of trailing padding), while on 64-bit it is 16 bytes long (with 6 bytes of padding). Make s_space() capable of handling 'x' (and 'p') type floating point being other than 12 bytes wide (also adjusting documentation). This requires duplicating the definition of X_PRECISION in the target speciifc header; the compiler would complain if this was out of sync with config/atof-ieee.c. Note that for now padding space doesn't get separated from actual storage, which means that things will work correctly only for little- endian cases, and which also means that by specifying large enough numbers padding space can be set to non-zero. Since the logic is needed for a single little-endian architecture only for now, I'm hoping that this might be acceptable for the time being; otherwise the change will become more intrusive. Note also that this brings the emitted data size of .ds.x vs .tfloat in line for non-ELF targets as well; the issue will be even more obvious when further taking into account a subsequent patch fixing .dc.x/.dcb.x (where output sizes currently differ depending on input format). Extend existing x86 testcases.
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili1-1/+3
Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14gas: drop TC_ADDRESS_BYTES conditionalsJan Beulich1-1/+2
I've been repeatedly confused by, in particular, the .dc.a potable[] entry being conditional. Grepping in gas/config/ reveals only very few targets actually #define-ing it. But as of 7be1c4891a20 the symbol is always defined, so #ifdef-s are pointless (and, as said, potentially confusing). Also adjust documentation to reflect this.
2021-05-26i386: Replace movsb with movsxbSebastien Villemot1-1/+1
PR gas/27906 * doc/c-i386.texi: Replace movsb with movsxb as an alias for movsbq.
2021-05-08support generating multi-html pages in parallelMike Frysinger2-2/+12
Use the pattern from other projects where we generate the html pages in a dir named the same as the project. So now we have: gas/doc/gas.html - single html page gas/doc/gas/ - multiple html pages This works for projects that have a doc/ subdir already, but gprof & ld require a little tweaking since they generate their docs in their respective toplevels.
2021-05-08generate single html manual page by defaultMike Frysinger2-2/+4
This better matches other GNU projects like autoconf/automake where the html manual is the single page form. We'll support the multi-page form in a follow up change.
2021-05-07Add a generic .bss directive for ELF based targets.Nick Clifton1-0/+13
PR 3136 * config/obj-elf.c (elf_pseudo_table): Add entry for .bss. (obj_elf_bss): New function. Change to the .bss section. Support an optional subsection number. (obj_elf_change_section): Call obj_elf_section_change_hook. (obj_elf_section): Likewise. (obj_elf_data): Likewise. (obj_elf_text): Likewise. (obj_elf_struct): Likewise. (obj_elf_subsection): Likewise. (obj_elf_previous): Likewise. * config/obj-elf.h (obj_elf_bss): Prototype. * doc/as.texi (Bss): New node.
2021-04-19gas: drop sprint_value()Jan Beulich1-7/+0
Its (documented) behavior is unhelpful in particular in 64-bit build environments: While printing large 32-bit numbers in decimal already isn't very meaningful to most people, this even more so goes for yet larger 64-bit numbers. bfd_sprintf_vma() still tries to limit the number of digits printed (without depending on a build system property), but uniformly produces hex output.
2021-04-05C99 gas configuryAlan Modra1-1/+0
Also remove alloca stuff since we don't use alloca in gas nowadays. * configure.ac: Don't check for string.h, strings.h, stdlib.h, errno.h, limits.h, locale.h or time.h. Don't check for unlink, remove, sbrk (unused) or setlocale. Adjust gas_test_headers. Don't check for errno, free, malloc, realoc, sbrk, strstr, getenv strstr, or vsnprintf declarations. (AC_ISC_POSIX, AC_FUNC_ALLOCA, AC_C_INLINE): Don't invoke. * as.h: Don't include alloca-conf.h, include config.h instead. Include string.h, stdlib.h, errno.h unconditionally. Remove various fallback declarations. * asintl.h: Don't test HAVE_LOCALE_H. * as.c: Don't test HAVE_SETLOCALE. * dwarf2dbg.c: Include limits.h unconditionally. * expr.c: Likewise. * sb.c: Likewise. * symbols.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-d30v.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-tic54x.c (tic54x_mlib): Call remove rather than unlink. * config.in: Regenerate. * configure: Regenerate. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate.
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu1-67/+93
* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types, [VALID/EXTRACT/ENCODE macros] BTYPE_IMM: Renamed from SBTYPE_IMM. JTYPE_IMM: Renamed from UJTYPE_IMM. CITYPE_IMM: Renamed from RVC_IMM. CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM. CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM. CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM. CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM. CIWTYPE_IMM: Renamed from RVC_UIMM8. CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM. CSSTYPE_IMM: Added for .insn without special encoding. CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM. CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM. CLTYPE_IMM: Added for .insn without special encoding. CLTYPE_LW_IMM: Renamed from RVC_LW_IMM. CLTYPE_LD_IMM: Renamed from RVC_LD_IMM. RVC_SIMM3: Unused and removed. CBTYPE_IMM: Renamed from RVC_B_IMM. CJTYPE_IMM: Renamed from RVC_J_IMM. * Added new operands and removed the unused ones, C5: Unsigned CL(CS) immediate, added for .insn directive. C6: Unsigned CSS immediate, added for .insn directive. Ci: Unused and removed. C<: Unused and removed. bfd/ PR 27158 * elfnn-riscv.c (perform_relocation): Updated encoding macros. (_bfd_riscv_relax_call): Likewise. (_bfd_riscv_relax_lui): Likewise. * elfxx-riscv.c (howto_table): Likewise. gas/ PR 27158 * config/tc-riscv.c (riscv_ip): Updated encoding macros. (md_apply_fix): Likewise. (md_convert_frag_branch): Likewise. (validate_riscv_insn): Likewise. Also arranged operands, including added C5 and C6 operands, and removed unused Ci and C< operands. * doc/c-riscv.texi: Updated and added CSS/CL/CS types. * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions. * testsuite/gas/riscv/insn.s: Likewise. gdb/ PR 27158 * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros. (decode_j_type_insn): Likewise. (decode_cj_type_insn): Likewise. (decode_b_type_insn): Likewise. (decode): Likewise. include/ PR 27158 * opcode/riscv.h: Updated encoding macros. opcodes/ PR 27158 * riscv-dis.c (print_insn_args): Updated encoding macros. * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. (match_c_addi16sp): Updated encoding macros. (match_c_lui): Likewise. (match_c_lui_with_hint): Likewise. (match_c_addi4spn): Likewise. (match_c_slli): Likewise. (match_slli_as_c_slli): Likewise. (match_c_slli64): Likewise. (match_srxi_as_c_srxi): Likewise. (riscv_insn_types): Added .insn css/cl/cs. sim/ PR 27158 * riscv/sim-main.c (execute_i): Updated encoding macros.
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