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2017-04-25gas: sparc: fix relaxation of CALL instruction into branches in a.out targetsJose E. Marchesi1-2/+7
This patch avoids CALL instructions to be optimized into branches if the symbols referred to in the CALL instruction are not fully resolved at the time the assembler writes its output. Tested in sparc64-linux-gnu and sparc-sun-sunos4.1.3 targets. No regressions. gas/ChangeLog: 2017-04-25 Jose E. Marchesi <jose.marchesi@oracle.com> PR gas/21407 * config/tc-sparc.c (md_apply_fix): Do not transform `call' instructions into branch instructions in fixups generating additional relocations. * testsuite/gas/sparc/call-relax.s: New file. * testsuite/gas/sparc/call-relax.d: Likewise. * testsuite/gas/sparc/call-relax-aout.d: Likewise. * testsuite/gas/sparc/sparc.exp: Test call-relax and call-relax-aout.
2017-04-24[GAS/ARM] Fix expansion of ldr pseudo instructionThomas Preud'homme1-9/+5
The LDR rX, =cst pseudo-instruction suffers from two issues for loading integer constants in Thumb mode: - movs is used if the constant and register can be encoded using that instruction which leads to unexpected behavior due to its flag-setting behavior - mov.w, movw and mvn are used for r13 (sp) and r15 (pc) but these encoding are marked as UNPREDICTABLE This patch fixes those issues and update testing accordingly. 2017-04-24 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (move_or_literal_pool): Remove code generating MOVS. Forbid MOV.W and MOVW if destination is SP or PC. * testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: Explain expectation of LDR not generating a MOVS for low registers and small constants. Add tests of MOVW generation. * testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: Update expected disassembly.
2017-04-11Bye bye PPC_OPCODE_HTM and -mhtmAlan Modra1-1/+0
The -mhtm option is fairly useless too. include/ * opcode/ppc.h (PPC_OPCODE_HTM): Delete. gas/ * config/tc-ppc.c (md_show_usage): Delete mention of -mhtm. * testsuite/gas/ppc/htm.d: Pass -mpower8 and -Mpower8. opcodes/ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_HTM and "htm". * ppc-opc.c (PPCHTM): Define as PPC_OPCODE_POWER8.
2017-04-10gas: xtensa: fix incorrect code generated with auto litpoolsMax Filippov1-29/+37
* config/tc-xtensa.c (xtensa_maybe_create_literal_pool_frag): Initialize lps->frag_count with auto_litpool_limit. (xg_promote_candidate_litpool): New function. (xtensa_move_literals): Extract candidate litpool promotion code into separate function. Call it for all possible found candidates. (xtensa_switch_to_literal_fragment): Drop 'recursive' flag and call to xtensa_mark_literal_pool_location that it guards. Replace it with call to xtensa_maybe_create_literal_pool_frag. Initialize pool_location with created literal pool candidate. * testsuite/gas/xtensa/all.exp: Add new tests. * testsuite/gas/xtensa/auto-litpools-first1.d: New test results. * testsuite/gas/xtensa/auto-litpools-first1.s: New test. * testsuite/gas/xtensa/auto-litpools-first2.d: New test results. * testsuite/gas/xtensa/auto-litpools-first2.s: New test. * testsuite/gas/xtensa/auto-litpools.d: Fix offsets changed due to additional jump instruction.
2017-04-04Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXXH.J. Lu9-21/+70
Mark an ALLOC section, which should be placed in special memory area, with SHF_GNU_MBIND. Its sh_info field indicates the special memory type. GNU_MBIND section names start with ".mbind" so that they are placed as orphan sections by linker. All input GNU_MBIND sections with the same sh_type, sh_flags and sh_info are placed in one output GNU_MBIND section. In executable and shared object, create a GNU_MBIND segment for each GNU_MBIND section and its segment type is PT_GNU_MBIND_LO plus the sh_info value. Each GNU_MBIND segment is aligned at page boundary. The assembler syntax: .section .mbind.foo,"adx",%progbits ^ 0: Special memory type. | 'd' for SHF_GNU_MBIND. .section .mbind.foo,"adx",%progbits,0x1 ^ 1: Special memory type. | 'd' for SHF_GNU_MBIND. .section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2 ^ 2: Special memory type. | 'd' for SHF_GNU_MBIND. bfd/ * elf.c (get_program_header_size): Add a GNU_MBIND segment for each GNU_MBIND section and align GNU_MBIND section to page size. (_bfd_elf_map_sections_to_segments): Create a GNU_MBIND segment for each GNU_MBIND section. (_bfd_elf_init_private_section_data): Copy sh_info from input for GNU_MBIND section. binutils/ * NEWS: Mention support for ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX. * readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX. (get_elf_section_flags): Handle SHF_GNU_MBIND. (process_section_headers): Likewise. * testsuite/binutils-all/mbind1.s: New file. * testsuite/binutils-all/objcopy.exp: Run readelf test on mbind1.s. gas/ * NEWS: Mention support for ELF SHF_GNU_MBIND. * config/obj-elf.c (section_match): New. (get_section): Match both sh_info and group name. (obj_elf_change_section): Add argument for sh_info. Pass both sh_info and group name to get_section. Issue an error for SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info. (obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'. (obj_elf_section): Support SHF_GNU_MBIND section info. * config/obj-elf.h (obj_elf_change_section): Add argument for sh_info. * config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to obj_elf_change_section. * config/tc-ia64.c (obj_elf_vms_common): Likewise. * config/tc-microblaze.c (microblaze_s_data): Likewise. (microblaze_s_sdata): Likewise. (microblaze_s_rdata): Likewise. (microblaze_s_bss): Likewise. * config/tc-mips.c (s_change_section): Likewise. * config/tc-msp430.c (msp430_profiler): Likewise. * config/tc-rx.c (parse_rx_section): Likewise. * config/tc-tic6x.c (tic6x_start_unwind_section): Likewise. * doc/as.texinfo: Document 'd' for SHF_GNU_MBIND. * testsuite/gas/elf/elf.exp: Run section12a, section12b and section13. * testsuite/gas/elf/section10.d: Updated. * testsuite/gas/elf/section10.s: Likewise. * testsuite/gas/elf/section12.s: New file. * testsuite/gas/elf/section12a.d: Likewise. * testsuite/gas/elf/section12b.d: Likewise. * testsuite/gas/elf/section13.l: Likewise. * testsuite/gas/elf/section13.d: Likewise. * testsuite/gas/elf/section13.s: Likewise. include/ * elf/common.h (PT_GNU_MBIND_NUM): New. (PT_GNU_MBIND_LO): Likewise. (PT_GNU_MBIND_HI): Likewise. (SHF_GNU_MBIND): Likewise. ld/ * NEWS: Mention support for ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX. * emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place input GNU_MBIND sections with the same type, attributes and sh_info field into a single output GNU_MBIND section. * testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b. * testsuite/ld-elf/mbind1.s: New file. * testsuite/ld-elf/mbind1a.d: Likewise. * testsuite/ld-elf/mbind1b.d: Likewise. * testsuite/ld-elf/mbind1c.d: Likewise. * testsuite/ld-elf/mbind2a.s: Likewise. * testsuite/ld-elf/mbind2b.c: Likewise.
2017-04-03RISC-V: Avoid a const warningPalmer Dabbelt1-1/+1
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com> * config/tc-riscv.c (riscv_clear_subsets): Cast argument to free to avoid const warnings.
2017-03-31RISC-V: Allow ISA subsets to be disabledPalmer Dabbelt1-0/+15
Without this patch, passing "-march=rv64ic -march=rv64i" results in you getting a "RV64IC" toolchain, which isn't expected. gas/ChangeLog: 2017-03-30 Palmer Dabbelt <palmer@dabbelt.com> * config/tc-riscv.c (riscv_clear_subsets): New function. (riscv_add_subset): Call riscv_clear_subsets and riscv_set_rvc to clear RVC when it's been previously set.
2017-03-31Reduce the size of s390 symbol tables by allowing relocations in mergeable ↵Nick Clifton1-2/+4
string sections (eg .debug_str) to be made section relative rather than symbol relative. PR gas/21333 * config/tc-s390.c (tc_s390_fix_adjustable): Allow non pc-relative fixups in mergeable sections to be adjusted.
2017-03-30Add support for the WebAssembly file format and the wasm32 ELF conversion to ↵Pip Cet2-0/+910
gas and the binutils. binutils * readelf.c: Add support for wasm32 ELF format WebAssembly files. (guess_is_rela): Likewise. (dump_relocations): Likewise. (is_32bit_abs_reloc): Likewise. (is_none_reloc_): Likewise. * NEWS: Mention the new support. * testsuite/lib/binutils-common.exp (is_elf_format): Mark wasm32 as ELF target. (supports_gnu_unique): Mark wasm32 as supporting STB_GNU_UNIQUE. * testsuite/binutils-all/nm.exp: Mark wasm32 as requiring .size annotations. * testsuite/binutils-all/wasm32: New directory. * testsuite/binutils-all/wasm32/create-wasm.d: New file. * testsuite/binutils-all/wasm32/create-wasm.s: Likewise. * testsuite/binutils-all/wasm32/custom-section.d: Likewise. * testsuite/binutils-all/wasm32/custom-section.s: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.d: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.s: Likewise. * testsuite/binutils-all/wasm32/long-sections.d: Likewise. * testsuite/binutils-all/wasm32/long-sections.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.s: Likewise. * testsuite/binutils-all/wasm32/prepared-section.d: Likewise. * testsuite/binutils-all/wasm32/prepared-section.s: Likewise. * testsuite/binutils-all/wasm32/wasm32.exp: New file, run tests. gas * config/tc-wasm32.h: New file: Add WebAssembly assembler target. * config/tc-wasm32.c: New file: Add WebAssembly assembler target. * Makefile.am: Add WebAssembly assembler target. * configure.tgt: Add WebAssembly assembler target. * doc/c-wasm32.texi: New file: Start documenting WebAssembly assembler. * doc/all.texi: Define WASM32. * doc/as.texinfo: Add WebAssembly entries. * NEWS: Mention the new support. * Makefile.in: Regenerate. * po/gas.pot: Regenerate. * po/POTFILES.in: Regenerate. * testsuite/gas/wasm32: New directory. * testsuite/gas/wasm32/allinsn.d: New file. * testsuite/gas/wasm32/allinsn.s: New file. * testsuite/gas/wasm32/illegal.l: New file. * testsuite/gas/wasm32/illegal.s: New file. * testsuite/gas/wasm32/illegal-2.l: New file. * testsuite/gas/wasm32/illegal-2.s: New file. * testsuite/gas/wasm32/illegal-3.l: New file. * testsuite/gas/wasm32/illegal-3.s: New file. * testsuite/gas/wasm32/illegal-4.l: New file. * testsuite/gas/wasm32/illegal-4.s: New file. * testsuite/gas/wasm32/illegal-5.l: New file. * testsuite/gas/wasm32/illegal-5.s: New file. * testsuite/gas/wasm32/illegal-6.l: New file. * testsuite/gas/wasm32/illegal-6.s: New file. * testsuite/gas/wasm32/illegal-7.l: New file. * testsuite/gas/wasm32/illegal-7.s: New file. * testsuite/gas/wasm32/illegal-8.l: New file. * testsuite/gas/wasm32/illegal-8.s: New file. * testsuite/gas/wasm32/illegal-9.l: New file. * testsuite/gas/wasm32/illegal-9.s: New file. * testsuite/gas/wasm32/illegal-10.l: New file. * testsuite/gas/wasm32/illegal-10.s: New file. * testsuite/gas/wasm32/illegal-11.l: New file. * testsuite/gas/wasm32/illegal-11.s: New file. * testsuite/gas/wasm32/illegal-12.l: New file. * testsuite/gas/wasm32/illegal-12.s: New file. * testsuite/gas/wasm32/illegal-13.l: New file. * testsuite/gas/wasm32/illegal-13.s: New file. * testsuite/gas/wasm32/illegal-14.l: New file. * testsuite/gas/wasm32/illegal-14.s: New file. * testsuite/gas/wasm32/illegal-15.l: New file. * testsuite/gas/wasm32/illegal-15.s: New file. * testsuite/gas/wasm32/illegal-16.l: New file. * testsuite/gas/wasm32/illegal-16.s: New file. * testsuite/gas/wasm32/illegal-17.l: New file. * testsuite/gas/wasm32/illegal-17.s: New file. * testsuite/gas/wasm32/illegal-18.l: New file. * testsuite/gas/wasm32/illegal-18.s: New file. * testsuite/gas/wasm32/illegal-19.l: New file. * testsuite/gas/wasm32/illegal-19.s: New file. * testsuite/gas/wasm32/illegal-20.l: New file. * testsuite/gas/wasm32/illegal-20.s: New file. * testsuite/gas/wasm32/illegal-21.l: New file. * testsuite/gas/wasm32/illegal-21.s: New file. * testsuite/gas/wasm32/illegal-22.l: New file. * testsuite/gas/wasm32/illegal-22.s: New file. * testsuite/gas/wasm32/illegal-24.l: New file. * testsuite/gas/wasm32/illegal-24.s: New file. * testsuite/gas/wasm32/illegal-25.l: New file. * testsuite/gas/wasm32/illegal-25.s: New file. * testsuite/gas/wasm32/reloc.d: New file. * testsuite/gas/wasm32/reloc.s: New file. * testsuite/gas/wasm32/wasm32.exp: New tests for WebAssembly architecture. opcodes * configure.ac: Add (empty) bfd_wasm32_arch target. * configure: Regenerate * po/opcodes.pot: Regenerate. include * opcode/wasm.h: New file to support wasm32 architecture. * elf/wasm32.h: Add R_WASM32_32 relocation. bfd * elf32-wasm32.c: Add relocation code, two relocs. * reloc.c: Add wasm32 relocations. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. * bfd/po/bfd.pot: Regenerate.
2017-03-29PowerPC -Mraw disassemblyAlan Modra1-1/+2
This adds -Mraw for PowerPC objdump, a disassembler option to display the underlying machine instruction rather than aliases. For example, "rlwinm" always rather than "rotlwi" when the instruction is performing a simple rotate. binutils/ * doc/binutils.texi (objdump): Document PowerPC -M options. gas/ * config/tc-ppc.c (md_parse_option): Reject -mraw. include/ * opcode/ppc.h (PPC_OPCODE_RAW): Define. (PPC_OPCODE_*): Make them all unsigned long long constants. opcodes/ * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add "raw" option. (lookup_powerpc): Don't special case -1 dialect. Handle PPC_OPCODE_RAW. (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first lookup_powerpc call, pass it on second.
2017-03-24[GAS/ARM] Fix selected_cpu with default CPU and -mcpuThomas Preud'homme1-2/+2
When GAS is compiled with DEFAULT_CPU set and then run with a -mcpu or -march option, selected_cpu will be set to the default CPU. This means the -mcpu is ignored which is surprising behavior. This commit instead sets selected_cpu from the value passed to -mcpu/-march. 2017-03-24 Thomas preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.: (md_begin): Set selected_cpu from *mcpu_cpu_opt when CPU_DEFAULT is defined.
2017-03-22Sanitize RISC-V GAS help text, documentationPalmer Dabbelt1-7/+2
It looks like I missed the GAS help text when going through all the documentation last time, so it printed some of the old-format (never upstream) arguments. I fixed this, and when I went to check doc/ I noticed it was missing the '-fpic'/'-fno-pic' options.
2017-03-22gas: xtensa: make trampolines relaxation work with jumps in slots other than 0Max Filippov1-4/+16
add_jump_to_trampoline assumes that jump instruction is in slot 0, when it's in other slot that results in fixup that references NULL symbol, which results in segfault later in xtensa_make_cached_fixup. Search for the non-NULL symbol in the tc_frag_data.slot_symbols and check that there's exactly one such slot. xtensa_relax_frag for RELAX_TRAMPOLINE reassigns fixup from the original instruction with jump to generated jump in the trampoline frag, but does not fix its fx_r_type or fx_size. That results in "undecodable fix" or "fixup not contained within frag" error messages during relaxation. Fix both these fields. gas/ 2017-03-22 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (xtensa_relax_frag): Change fx_size of the reassigned fixup to size of jump instruction (3) and fx_r_type to BFD_RELOC_XTENSA_SLOT0_OP, as there's only one slot. (add_jump_to_trampoline): Search origfrag->tc_frag_data.slot_symbols for the slot with non-NULL symbol and use that slot instead of slot 0.
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel1-4/+2
This patch removes the vx2 facility flag. It will not be used by GCC and was a misnomer anyway. Committed to mainline and 2.28 branch. include/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h (S390_INSTR_FLAG_VX2): Remove. (S390_INSTR_FLAG_FACILITY_MASK): Adjust value. gas/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2 from cpu_table. Remove vx2, and novx2 from cpu_flags. opcodes/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Remove vx2 check. * s390-opc.txt: Remove vx2 instruction flags.
2017-03-20[arm] Document missing -mfpu entries.Richard Earnshaw1-3/+3
Nick pointed out that I hadn't documented the new -mfpu option neon-vfpv3 and mentioned that some others were missing. Having looked through the list only one (neon-fp16) really should be documented; the other two entries in the real table should not be documented as they are aliases kept for legacy compatibility reasons. This patch adds the missing entries and notes in the main table that the other two entries should not be documented. I've also fixed a small spelling error in the accompanying text. * config/tc-arm.c (arm_fpus): Note entires that should not be documented. * doc/c-arm.texi (-mfpu): Add missing FPU entries for neon-vfpv3 and neon-fp16. Fix spelling error.
2017-03-20[arm] Add neon-vfp3 as an alias for neon to -mfpu.Richard Earnshaw1-0/+1
GCC recently added neon-vfpv3 as an alias for neon in -mfpu. This patch adds a similar alias in GAS. * config/tc-arm.c (arm_fpus): Add neon-vfpv3 as an alias for neon.
2017-03-16gas/arc: Limit special handling of t/nt flag to ARCv2Rinat Zelig1-5/+13
In a later commit I'll be adding a new version of the ".nt" flag for an ARC700 extension (NPS400) which does not require this same special handling. In this commit I have restricted the special flag handling to only apply if we are assembling for ARCv2. This is a restructuring commit, and there should be no user visible changes after this commit. gas/ChangeLog: * config/tc-arc.c (assemble_insn): Only handle ".t" and ".nt" specially for ARCv2.
2017-03-15RISC-V: Fix assembler for c.li, c.andi and c.addiwKito Cheng1-0/+8
- They can accept 0 in imm field 2017-03-14 Kito Cheng <kito.cheng@gmail.com> * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding. <c.andi>: Likewise. <c.addiw> Likewise.
2017-03-15Fix building riscv targets with gcc v6.3.1Nick Clifton1-1/+1
* config/tc-riscv.c (riscv_pre_output_hook): Fix compile time warning about discarding a const qualifier.
2017-03-14RISC-V: Define DWARF2_USE_FIXED_ADVANCE_PC.Kuan-Lin Chen1-0/+3
gas/ChangeLog 2017-03-02 Kuan-Lin Chen <rufus@andestech.com> * config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define.
2017-03-14RISC-V: Fix DW_CFA_advance_loc relocation.Kuan-Lin Chen1-0/+2
gas/ChangeLog: 2017-03-02 Kuan-Lin Chen <rufus@andestech.com> * config/tc-riscv.c (md_apply_fix): Set fx_frag and fx_next->fx_frag for CFA_advance_loc relocations.
2017-03-14RISC-V: Fix the offset of CFA relocation.Kuan-Lin Chen1-10/+10
gas/ChangeLog: 2017-03-02 Kuan-Lin Chen <rufus@andestech.com> * config/tc-riscv.c (md_apply_fix): Compute the correct offsets for CFA relocations.
2017-03-13Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and ↵Nick Clifton1-6/+6
R_AARCH64_TLSDESC_ADD_LO12_NC to R_AARCH64_TLSDESC_ADD_LO12. PR binutils/21202 include * elf/aarch64.h (R_AARCH64_TLSDESC_LD64_LO12_NC): Rename to R_AARCH64_TLSDESC_LD64_LO12. (R_AARCH64_TLSDESC_ADD_LO12_NC): Rename to R_AARCH64_TLSDESC_ADD_LO12_NC. bfd * reloc.c (BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC): Rename to BFD_RELOC_AARCH64_TLSDESC_LD64_LO12. (BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC): Rename to BFD_RELOC_AARCH64_TLSDESC_ADD_LO12. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (IS_AARCH64_TLS_RELAX_RELOC): Update reloc names. (IS_AARCH64_TLSDESC_RELOC): Likewise. (elfNN_aarch64_howto_table): Likewise. (aarch64_tls_transition_without_check): Likewise. (aarch64_reloc_got_type): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_tls_relax): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. gas * config/tc-aarch64.c (reloc_table): Rename BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC to BFD_RELOC_AARCH64_TLSDESC_LD64_LO12. Rname BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC to BFD_RELOC_AARCH64_TLSDESC_ADD_LO12. (md_apply_fix): Likewise. (aarch64_force_relocation): Likewise. * testsuite/gas/aarch64/tls.d: Update regexp. ld * testsuite/ld-aarch64/ifunc-5r-local.d: Update regexp.
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu1-44/+114
Many x86 instructions have more than one encodings. Assembler picks the default one, usually the shortest one. Although the ".s", ".d8" and ".d32" suffixes can be used to swap register operands or specify displacement size, they aren't very flexible. This patch adds pseudo prefixes, {xxx}, to control instruction encoding. The available pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3} and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and ".d32" suffixes, which are deprecated. gas/ * config/tc-i386.c (_i386_insn): Add dir_encoding and vec_encoding. Remove swap_operand and need_vrex. (extra_symbol_chars): Add '}'. (md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in mnemonic. (build_vex_prefix): Don't use 2-byte VEX encoding with {vex3}. Check dir_encoding and load. (parse_insn): Check pseudo prefixes. Set dir_encoding. (VEX_check_operands): Likewise. (match_template): Check dir_encoding and load. (parse_real_register): Set vec_encoding instead of need_vrex. (parse_register): Likewise. * doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32" * testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos. * testsuite/gas/i386/pseudos.d: New file. * testsuite/gas/i386/pseudos.s: Likewise. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. * testsuite/gas/i386/x86-64-pseudos.s: Likewise. opcodes/ * i386-gen.c (opcode_modifiers): Replace S with Load. * i386-opc.h (S): Removed. (Load): New. (i386_opcode_modifier): Replace s with load. * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3} and {evex}. Replace S with Load. * i386-tbl.h: Regenerated.
2017-03-06Add support for Intel CET instructionsH.J. Lu1-0/+2
Support Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * config/tc-i386.c (cpu_arch): Add .cet. * doc/c-i386.texi: Document cet. * testsuite/gas/i386/cet-intel.d: New file. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/cet.s: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/x86-64-cet.s: Likewise. * testsuite/gas/i386/i386.exp: Run Intel CET tests. opcodes/ * i386-dis.c (REG_0F1E_MOD_3): New enum. (MOD_0F1E_PREFIX_1): Likewise. (MOD_0F38F5_PREFIX_2): Likewise. (MOD_0F38F6_PREFIX_0): Likewise. (RM_0F1E_MOD_3_REG_7): Likewise. (PREFIX_MOD_0_0F01_REG_5): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise. (PREFIX_0F1E): Likewise. (PREFIX_MOD_0_0FAE_REG_5): Likewise. (PREFIX_0F38F5): Likewise. (dis386_twobyte): Use PREFIX_0F1E. (reg_table): Add REG_0F1E_MOD_3. (prefix_table): Add PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2, PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update PREFIX_0FAE_REG_6 and PREFIX_0F38F6. (three_byte_table): Use PREFIX_0F38F5. (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5. Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0. (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and PREFIX_MOD_3_0F01_REG_5_RM_2. * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS. (cpu_flags): Add CpuCET. * i386-opc.h (CpuCET): New enum. (CpuUnused): Commented out. (i386_cpu_flags): Add cpucet. * i386-opc.tbl: Add Intel CET instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2017-02-28Nios2 dynobj handling fixesAlan Modra1-0/+8
A number of places in elf32-nios.c created dynamic sections but didn't set the hash table dynobj. That meant we could have duplicate dynamic sections connected to a number of bfds, so size_dynamic_sections didn't properly discard or allocate contents. Also, the entire set of dynamic sections was created in check_relocs on seeing GOT relocs, when only .got related sections are needed, probably done to hide segfaults later in finish_dynamic_sections. The patch fixes these issues and makes the assembler emit errors when nios2 lacks the necessary pc-relative relocs for subtraction expressions, rather than silently generating bad code. eg. ld-elf/merge. I've also tidied uses of elf32_nios2_hash_table and elf_hash_table. bfd/ PR 20995 * elf32-nios2.c (nios2_elf32_relocate_section): Use htab rather than elf32_nios2_hash_table or elf_hash_table. (create_got_section): Likewise. (nios2_elf32_finish_dynamic_symbol): Likewise. (nios2_elf32_adjust_dynamic_symbol): Likewise. (nios2_elf32_size_dynamic_sections): Likewise. (nios2_elf32_check_relocs): Delete dynobj, sgot, and srelgot vars. Use htab equivalents directly instead. Don't create all dynamic sections on needing just the GOT. Use a goto rather than a fall-through with reloc test. Ensure htab->dynobj is set when making dynamic sreloc section. (nios2_elf32_finish_dynamic_sections): Delete dynobj, use htab equivalent directly instead. Don't segfault on looking for .dynamic when dynamic sections have not been created. Don't segfault on .got.plt being discarded. (nios2_elf32_size_dynamic_sections): Delete plt and got vars. Don't set "relocs" on .rela.plt. Do handle .sbss. Delete fixme and another not so relevant comment. (nios2_elf_add_symbol_hook): Delete dynobj var. If not already set, set hash table dynobj on creating .sbss. gas/ * config/tc-nios2.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define. ld/ * testsuite/ld-elf/merge.d: xfail for nios.
2017-02-28PowerPC addpcis fixAlan Modra2-81/+61
This came up because I was looking at ld/tmpdir/addpcis.o and noticed the odd addends on REL16DX_HA. They ought to both be -4. The error crept in due REL16DX_HA howto being pc-relative (as indeed it should be), and code at gas/write.c:1001 after this comment /* Make it pc-relative. If the back-end code has not selected a pc-relative reloc, cancel the adjustment we do later on all pc-relative relocs. */ *not* cancelling the pc-relative adjustment. So I've made a dummy non-relative split reloc so that the generic code handles this, rather than attempting to add hacks later in md_apply_fix which would not be very robust. Having the new internal reloc also makes it easy to support addpcis rx,sym@ha as an equivalent to addpcis rx,(sym-0f)@ha 0: The patch also fixes overflow checking, which must test whether the addi will overflow too since @l relocs don't have any overflow check. Lastly, since I was poking at md_apply_fix, I arranged to have the generic gas/write.c code emit errors for subtraction expressions where we lack reloc support. include/ * elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment. * elf/ppc.h (R_PPC_16DX_HA): Likewise. bfd/ * reloc.c (BFD_RELOC_PPC_16DX_HA): New. * elf64-ppc.c (ppc64_elf_howto_raw <R_PPC64_16DX_HA>): New howto. (ppc64_elf_reloc_type_lookup): Translate new bfd reloc. (ppc64_elf_ha_reloc): Correct overflow test on REL16DX_HA. (ppc64_elf_relocate_section): Likewise. * elf32-ppc.c (ppc_elf_howto_raw <R_PPC_16DX_HA>): New howto. (ppc_elf_reloc_type_lookup): Translate new bfd reloc. (ppc_elf_check_relocs): Handle R_PPC_16DX_HA to pacify gcc. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis. (md_apply_fix): Remove fx_subsy check. Move code converting to pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA. Remove code emiiting errors on seeing fx_pcrel set on unexpected relocs, as that is done now by the generic code via.. * config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define. (TC_VALIDATE_FIX_SUB): Define. ld/ * testsuite/ld-powerpc/addpcis.d: Define ext1 and ext2 at limits of addpcis range.
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-3/+10
This patch supports some additions to the SVE architecture prior to its public release. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16) (AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2) (AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX) (AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds. opcodes/ * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD) (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD) (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S) (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H) (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH) (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD) (OP_SVE_V_HSD): New macros. (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD) (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD) (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete. (aarch64_opcode_table): Add new SVE instructions. (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate for rotation operands. Add new SVE operands. * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter. (ins_sve_quad_index): Likewise. (ins_imm_rotate): Split into... (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters. * aarch64-asm.c (aarch64_ins_imm_rotate): Split into... (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two functions. (aarch64_ins_sve_addr_ri_s4): New function. (aarch64_ins_sve_quad_index): Likewise. (do_misc_encoding): Handle "MOV Zn.Q, Qm". * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor. (ext_sve_quad_index): Likewise. (ext_imm_rotate): Split into... (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors. * aarch64-dis.c (aarch64_ext_imm_rotate): Split into... (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two functions. (aarch64_ext_sve_addr_ri_s4): New function. (aarch64_ext_sve_quad_index): Likewise. (aarch64_ext_sve_index): Allow quad indices. (do_misc_decoding): Likewise. * aarch64-dis-2.c: Regenerate. * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New aarch64_field_kinds. (OPD_F_OD_MASK): Widen by one bit. (OPD_F_NO_ZR): Bump accordingly. (get_operand_field_width): New function. * aarch64-opc.c (fields): Add new SVE fields. (operand_general_constraint_met_p): Handle new SVE operands. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum. * config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q to be used with SVE registers. (parse_operands): Handle new SVE operands. (aarch64_features): Make "sve" require F16 rather than FP. Also require COMPNUM. * testsuite/gas/aarch64/sve.s: Add tests for new instructions. Include compnum tests. * testsuite/gas/aarch64/sve.d: Update accordingly. * testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions. * testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also update expected output for new FMOV and MOV alternatives.
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford1-0/+3
This patch adds a named "compnum" feature for the ARMv8.3-A FCADD and FCMLA extensions. include/ * opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro. (AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM. opcodes/ * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with... (aarch64_feature_compnum): ...this. (SIMD_V8_3): Replace with... (COMPNUM): ...this. (CNUM_INSN): New macro. (aarch64_opcode_table): Use it for the complex number instructions. gas/ * doc/c-aarch64.texi: Add a "compnum" entry. * config/tc-aarch64.c (aarch64_features): Likewise, * testsuite/gas/aarch64/advsimd-compnum.s: New test. * testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
2017-02-23S/390: Add support for new cpu architecture - arch12.Andreas Krebbel1-2/+6
This adds support of new instructions to the S/390 specific parts. The important feature of the new instruction set is the support of single and extended precision floating point vector operations. Note: arch12 is NOT the official name of the new CPU. It just continues the series of archXX options supported as alternate names. The archXX terminology refers to the edition number of the Principle of Operations manual. The official CPU name will be added later while keeping support of the arch12 for backwards compatibility. No testsuite regressions. Committed to mainline. Bye, -Andreas- opcodes/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Accept arch12 as cpu string and vx2 as facility. * s390-opc.c: Add new operand description macros, new instruction types, instruction masks, and new .insn instruction types. * s390-opc.txt: Add new arch12 instructions. include/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): New value S390_OPCODE_ARCH12. (S390_INSTR_FLAG_VX2): New macro definition. gas/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch12. * doc/as.texinfo: Document arch12 as cpu type. * doc/c-s390.texi: Likewise. * testsuite/gas/s390/s390.exp: Run arch12 specific tests. * testsuite/gas/s390/zarch-arch12.d: New test. * testsuite/gas/s390/zarch-arch12.s: New test. * testsuite/gas/s390/zarch-z13.d: Rename some mnemonics in the output patterns.
2017-02-23opcodes,gas: associate SPARC ASIs with an architecture level.Sheldon Lobo1-7/+46
With this change an architecture level bump due to assembly ASIs will show up as a warning/error depending on options passed to gas. Tested with sparc64-linux-gnu, and it does not introduce any regressions. gas/ChangeLog: Add support for associating SPARC ASIs with an architecture level. * config/tc-sparc.c (parse_sparc_asi): New encode SPARC ASIs. opcodes/ChangeLog: Add support for associating SPARC ASIs with an architecture level. * include/opcode/sparc.h (sparc_asi): New sparc_asi struct. * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/ decoding of SPARC ASIs.
2017-02-22GAS: Consistently fix labels at the `.end' pseudo-opMaciej W. Rozycki1-4/+4
Fix a functional regression with the `.end' pseudo-op, introduced with commit ecb4347adecd ("Last take: approval for MIPS_STABS_ELF killing"), <https://sourceware.org/ml/binutils/2002-06/msg00443.html>, and commit dcd410fe1544 ("GNU as 2.14 on IRIX 6: crashes with shared libs"), <https://sourceware.org/ml/binutils/2003-07/msg00415.html>, which caused symbol values for labels placed between the end of a function's contents and its terminating `.end' followed by one of the alignment pseudo-ops to be different depending on whether either `-mdebug', or `-mno-pdr', or neither of the command-line options is in effect, be it implied or specified. Given debug-label-end.s as follows and the `mips-linux' target we have: $ cat debug-label-end.s .text .globl foo .globl bar .align 4, 0 .ent foo foo: nop .aent bar bar: .insn .end foo .align 4, 0 .space 16 .globl baz .ent baz baz: nop .end baz .align 4, 0 .space 16 $ as -o debug-label-end.o debug-label-end.s $ readelf -s debug-label-end.o | grep bar 9: 00000004 0 FUNC GLOBAL DEFAULT 1 bar $ as -mdebug -o debug-label-end.o debug-label-end.s $ readelf -s debug-label-end.o | grep bar 9: 00000010 0 FUNC GLOBAL DEFAULT 1 bar $ as -mno-pdr -o debug-label-end.o debug-label-end.s $ readelf -s debug-label-end.o | grep bar 8: 00000010 0 FUNC GLOBAL DEFAULT 1 bar $ The reason is the call to `md_flush_pending_output', which in the case of `mips*-*-*' targets expands to `mips_emit_delays', which in turn calls `mips_no_prev_insn', which calls `mips_clear_insn_labels', which clears the list of outstanding labels. That list is in turn consulted in `mips_align', called in the interpretation of alignment directives, and the labels adjusted to the current location. A call to `md_flush_pending_output' is only made from `s_mips_end' and then only if `-mpdr' is in effect, which is the default for `*-*-linux*' and some other `mips*-*-*' targets. A call to `md_flush_pending_output' is never made from `ecoff_directive_end', which is used in place of `s_mips_end' when `-mdebug' is in effect. Consequently if `-mno-pdr' or `-mdebug' is in effect the list of outstanding labels makes it through to any alignment directive that follows and the labels are differently interpreted depending on the command-lines options used. And we want code produced to be always the same. Call `md_flush_pending_output' unconditionally then in `s_mips_end' and add such a call from `ecoff_directive_end' as well, as long as the macro is defined. While `ecoff_directive_end' is shared among targets, the only one other than `mips*-*-*' actually using it is `alpha*-*-*' and it does not define `md_flush_pending_output'. So the semantics isn't going to change for it and neither it has to have its `s_alpha_end' updated or have code in `ecoff_directive_end' conditionalized. gas/ * ecoff.c (ecoff_directive_end) [md_flush_pending_output]: Call `md_flush_pending_output'. * config/tc-mips.c (s_mips_end) [md_flush_pending_output]: Call `md_flush_pending_output' unconditionally. * testsuite/gas/mips/debug-label-end-1.d: New test. * testsuite/gas/mips/debug-label-end-2.d: New test. * testsuite/gas/mips/debug-label-end-3.d: New test. * testsuite/gas/mips/debug-label-end.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2017-02-20Downgrade powerpc register error to warningAlan Modra1-3/+3
PR 21118 * NEWS: Revise powerpc register check. * config/tc-ppc.c (ppc_optimize_expr, md_assemble): Make "invalid register expression" a warning.
2017-02-17GAS: Add ECOFF `.aent' pseudo-op supportMaciej W. Rozycki2-2/+4
Implement the ECOFF `.aent' pseudo-op for ECOFF-style `.mdebug' section support with ELF objects and, for consistency, also with ECOFF objects. This is so that the same MIPS source can be assembled without and with `.mdebug' section generation enabled. Taking the `gas/testsuite/gas/mips/aent.s' test case source as an example and the `mips-linux' target we have: $ as -o aent.o aent.s $ as -mdebug -o aent.o aent.s aent.s: Assembler messages: aent.s:10: Error: unknown pseudo-op: `.aent' $ because for the !ECOFF_DEBUGGING case (which is the default) the pseudo-op is already handled by the MIPS backend with `s_mips_ent', however no handler is present for the opposite case. For the MIPS target this is a functional regression introduced with commit ecb4347adecd ("Last take: approval for MIPS_STABS_ELF killing"), <https://sourceware.org/ml/binutils/2002-06/msg00443.html>, where support for the `.mdebug' section was added along with its associated `-mdebug'/`-no-mdebug' command-line options, bringing an inconsistency between the assembly syntax supported for each of these options as far as the `.aent' pseudo-op is concerned. Assembly language documentation available describes the pseudo-op respectively as follows[1]: " .aent name, symno Sets an alternate entry point for the current procedure. Use this information when you want to generate information for the debugger. It must appear inside an .ent/.end pair." and[2]: " .aent name [,symno] Sets an alternate entry point for the current procedure. Use this information when you want to generate information for the debugger. This directive must appear between a pair of .ent and .end directives. (The optional symno is for compiler use only. It refers to a dense number in a .T file (symbol table).)" Copy the approach from `s_mips_ent' then and add `.aent' support to the `.ent' pseudo-op handler shared between the ELF and ECOFF object file format backends, by setting BSF_FUNCTION for the symbol requested. References: [1] "MIPSpro Assembly Language Programmer's Guide", Silicon Graphics, Inc., Document Number 007-2418-004, Section 8.1 "Op-Codes", p. 96 <http://techpubs.sgi.com/library/manuals/2000/007-2418-004/pdf/007-2418-004.pdf> [2] "Digital UNIX Assembly Language Programmer's Guide", Digital Equipment Corporation, Order Number: AA-PS31D-TE, March 1996, Chapter 5 "Assembler Directives", p. 5-2 <http://h41361.www4.hpe.com/docs/base_doc/DOCUMENTATION/V40G_PDF/APS31DTE.PDF> gas/ * ecoff.c (ecoff_directive_ent, add_procedure): Handle `.aent'. * config/obj-ecoff.c (obj_pseudo_table): Add "aent" entry. * config/obj-elf.c (ecoff_debug_pseudo_table): Likewise. * testsuite/gas/mips/aent-2.d: New test. * testsuite/gas/mips/aent-mdebug.d: New test. * testsuite/gas/mips/aent-mdebug-2.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests.
2017-02-15[ARC] Fix assembler relaxation.Claudiu Zissulescu1-9/+32
Fix assembler relaxation step for add, ld, mov, mpy and sub instructions. Add tests to it. gas/ 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (md_convert_frag): Remove @pcl relocation information from input expression. (assemble_insn): Make sure pcrel is correctly set. (arc_pcrel_adjust): Compensate for PCL rounding. * testsuite/gas/arc/relax-add01.d: New file. * testsuite/gas/arc/relax-add01.s: Likewise. * testsuite/gas/arc/relax-add02.d: Likewise. * testsuite/gas/arc/relax-add02.s: Likewise. * testsuite/gas/arc/relax-add03.d: Likewise. * testsuite/gas/arc/relax-add03.s: Likewise. * testsuite/gas/arc/relax-add04.d: Likewise. * testsuite/gas/arc/relax-add04.s: Likewise. * testsuite/gas/arc/relax-ld01.d: Likewise. * testsuite/gas/arc/relax-ld01.s: Likewise. * testsuite/gas/arc/relax-ld02.d: Likewise. * testsuite/gas/arc/relax-ld02.s: Likewise. * testsuite/gas/arc/relax-mov01.d: Likewise. * testsuite/gas/arc/relax-mov01.s: Likewise. * testsuite/gas/arc/relax-mov02.d: Likewise. * testsuite/gas/arc/relax-mov02.s: Likewise. * testsuite/gas/arc/relax-mpy01.d: Likewise. * testsuite/gas/arc/relax-mpy01.s: Likewise. * testsuite/gas/arc/relax-sub01.d: Likewise. * testsuite/gas/arc/relax-sub01.s: Likewise. * testsuite/gas/arc/relax-sub02.d: Likewise. * testsuite/gas/arc/relax-sub02.s: Likewise. * testsuite/gas/arc/relax-sub03.d: Likewise. * testsuite/gas/arc/relax-sub03.s: Likewise. * testsuite/gas/arc/relax-sub04.d: Likewise. * testsuite/gas/arc/relax-sub04.s: Likewise. opcodes/ 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (UIMM6_20R): Define. (SIMM12_20): Use above. (SIMM12_20R): Define. (SIMM3_5_S): Use above. (UIMM7_A32_11R_S): Define. (UIMM7_9_S): Use above. (UIMM3_13R_S): Define. (SIMM11_A32_7_S): Use above. (SIMM9_8R): Define. (UIMM10_A32_8_S): Use above. (UIMM8_8R_S): Define. (W6): Use above. (arc_relax_opcodes): Use all above defines.
2017-02-14PowerPC register expression checksAlan Modra2-484/+548
This stops powerpc gas blithely accepting such nonsense as "addi %f4,%cr3,%r31". PR 21118 gas/ * NEWS: Mention powerpc register checks. * config/tc-ppc.c (struct pd_reg): Make value a short. Add flags. (pre_defined_registers): Delete fpscr and pmr entries. Set register type in flags. (cr_names): Set type in flags. (reg_name_search): Return pointer to struct pd_reg rather than value. (register_name): Adjust to suit. Set X_md from flags. (ppc_parse_name): Likewise. (ppc_optimize_expr): New function. (md_assemble): Verify expresion reg flags match operand. * config/tc-ppc.h (md_optimize_expr): Define. (ppc_optimize_expr): Declare. include/ * opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first. (PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define. opcodes/ * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
2017-02-13[ARM] Allow immediate without prefix in unified syntax for VCMPThomas Preud'homme1-3/+7
2017-02-13 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (parse_ifimm_zero): Make prefix optional in unified syntax. * testsuite/gas/arm/vcmp-noprefix-imm.d: New file. * testsuite/gas/arm/vcmp-noprefix-imm.s: New file.
2017-02-06[ARC] Provide an interface to decode ARC instructions.Claudiu Zissulescu1-0/+4
gas/ 2017-02-06 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (parse_opcode_flags): Ignore implicit flags. include/ 2017-02-06 Claudiu Zissulescu <claziss@synopsys.com> Anton Kolesov <anton.kolesov@synopsys.com> * opcode/arc.h (insn_class_t): Add ENTER, LEAVE, POP, PUSH, BBIT0, BBIT1, BI, BIH, BRCC, EI, JLI, and SUB instruction classes. (flag_class_t): Add F_CLASS_WB, F_CLASS_ZZ, and F_CLASS_IMPLICIT flag classes. opcode/ 2017-02-06 Claudiu Zissulescu <claziss@synopsys.com> Anton Kolesov <anton.kolesov@synopsys.com> * arc-dis.c (arc_disassemble_info): New structure. (init_arc_disasm_info): New function. (find_format_from_table): Ignore implicit flags. (find_format): Update dissassembler private data. (print_flags): Likewise. (print_insn_arc): Likewise. (arc_opcode_to_insn_type): Consider the new added instruction classes. (arcAnalyzeInstr): Remove. (arc_insn_decode): New function. * arc-dis.h (arc_ldst_writeback_mode): New enum. (arc_ldst_data_size): Likewise. (arc_condition_code): Likewise. (arc_operand_kind): Likewise. (arc_insn_kind): New struct. (arc_instruction): Likewise. (arc_insn_decode): Declare function. (ARC_Debugger_OperandType): Deleted. (Flow): Likewise. (NullifyMode): Likewise. (allOperandsSize): Likewise. (arcDisState): Likewise. (arcAnalyzeInstr): Likewise. * arc-dis.c (arc_opcode_to_insn_type): Handle newly introduced insn_class_t enums. * arc-opc.c (F_SIZED): New define. (C_CC_EQ, C_CC_GE, C_CC_GT, C_CC_HI, C_CC_HS): Likewise. (C_CC_LE, C_CC_LO, C_CC_LS, C_CC_LT, C_CC_NE): Likewise. (C_CC_NE, C_AA_AB, C_AA_AW, C_ZZ_D, C_ZZ_H, C_ZZ_B): Likewise. (arc_flag_classes): Add F_CLASS_COND/F_CLASS_IMPLICIT flags. * opcodes/arc-tbl.h: Update instructions to include new F_CLASS_IMPLICIT flags. (bbit0, lp): Change class. (bbit1, bi, bih, br*, ei_s, jli_s): Likewsie
2017-01-30MIPS: Add options to control branch ISA checksMaciej W. Rozycki1-0/+22
Complement commit 9d862524f6ae ("MIPS: Verify the ISA mode and alignment of branch and jump targets") and add GAS and LD options to control the checks for invalid branches between ISA modes introduced there, to help with some handwritten code lacking `.insn' annotation for labels used as branch targets and code produced by older versions of GCC which suffers from the issue with branches to code that has been optimized away, addressed with GCC commit 242424 ("MIPS/GCC: Mark trailing labels with `.insn'"), <https://gcc.gnu.org/ml/gcc-patches/2016-11/msg01061.html>. bfd/ * elfxx-mips.h (_bfd_mips_elf_insn32): Rename prototype to... (_bfd_mips_elf_linker_flags): ... this. Add another parameter. * elfxx-mips.c (mips_elf_link_hash_table): Add `ignore_branch_isa' member. (mips_elf_perform_relocation): Do not treat an ISA mode mismatch in branch relocation calculation as an error if `ignore_branch_isa' has been set. (_bfd_mips_elf_insn32): Rename to... (_bfd_mips_elf_linker_flags): ... this. Rename the `on' parameter to `insn32' and add an `ignore_branch_isa' parameter. Handle the new parameter. gas/ * config/tc-mips.c (mips_ignore_branch_isa): New variable. (options): Add OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA enum values. (md_longopts): Add "mignore-branch-isa" and "mno-ignore-branch-isa" options. (md_parse_option): Handle OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA. (fix_bad_cross_mode_branch_p): Return FALSE if `mips_ignore_branch_isa' has been set. (md_show_usage): Add `-mignore-branch-isa' and `-mno-ignore-branch-isa'. * doc/as.texinfo (Target MIPS options): Add `-mignore-branch-isa' and `-mno-ignore-branch-isa' options. (-mignore-branch-isa, -mno-ignore-branch-isa): New options. * doc/c-mips.texi (MIPS Options): Add `-mignore-branch-isa' and `-mno-ignore-branch-isa' options. * testsuite/gas/mips/branch-local-ignore-2.d: New test. * testsuite/gas/mips/branch-local-ignore-3.d: New test. * testsuite/gas/mips/branch-local-ignore-n32-2.d: New test. * testsuite/gas/mips/branch-local-ignore-n32-3.d: New test. * testsuite/gas/mips/branch-local-ignore-n64-2.d: New test. * testsuite/gas/mips/branch-local-ignore-n64-3.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * emultempl/mipself.em (ignore_branch_isa): New variable. (mips_create_output_section_statements): Rename `_bfd_mips_elf_insn32' called to `_bfd_mips_elf_linker_flags', add `ignore_branch_isa' argument. (PARSE_AND_LIST_PROLOGUE): Add OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA enum values. (PARSE_AND_LIST_LONGOPTS): Add "ignore-branch-isa" and "no-ignore-branch-isa" options. (PARSE_AND_LIST_OPTIONS): Add `--ignore-branch-isa' and `--no-ignore-branch-isa'. (PARSE_AND_LIST_ARGS_CASES): Handle OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA. * ld.texinfo (Options specific to MIPS targets): Add `--ignore-branch-isa' and `--no-ignore-branch-isa' options. (ld and the MIPS family): Likewise. * testsuite/ld-mips-elf/bal-jalx-pic-ignore.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-n64.d: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-2.d: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-mips16: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-micromips: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2017-01-23Fix spelling mistakes and typos in the GAS sources.Nick Clifton68-355/+355
PR gas/21072 * asintl.h: Fix spelling mistakes and typos. * atof-generic.c: Likewise. * bit_fix.h: Likewise. * config/atof-ieee.c: Likewise. * config/bfin-defs.h: Likewise. * config/bfin-parse.y: Likewise. * config/obj-coff-seh.h: Likewise. * config/obj-coff.c: Likewise. * config/obj-evax.c: Likewise. * config/obj-macho.c: Likewise. * config/rx-parse.y: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-avr.c: Likewise. * config/tc-bfin.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-cris.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-d10v.c: Likewise. * config/tc-d30v.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-epiphany.c: Likewise. * config/tc-frv.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i370.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m32r.c: Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mcore.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-mep.h: Likewise. * config/tc-metag.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-msp430.h: Likewise. * config/tc-nds32.c: Likewise. * config/tc-nds32.h: Likewise. * config/tc-nios2.c: Likewise. * config/tc-nios2.h: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-pdp11.c: Likewise. * config/tc-ppc.c: Likewise. * config/tc-pru.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-s390.c: Likewise. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-sh64.c: Likewise. * config/tc-sparc.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-v850.c: Likewise. * config/tc-vax.c: Likewise. * config/tc-visium.c: Likewise. * config/tc-xgate.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * config/tc-z8k.c: Likewise. * config/te-vms.c: Likewise. * config/xtensa-relax.c: Likewise. * doc/as.texinfo: Likewise. * doc/c-arm.texi: Likewise. * doc/c-hppa.texi: Likewise. * doc/c-i370.texi: Likewise. * doc/c-i386.texi: Likewise. * doc/c-m32r.texi: Likewise. * doc/c-m68k.texi: Likewise. * doc/c-mmix.texi: Likewise. * doc/c-msp430.texi: Likewise. * doc/c-nds32.texi: Likewise. * doc/c-ns32k.texi: Likewise. * doc/c-riscv.texi: Likewise. * doc/c-rx.texi: Likewise. * doc/c-s390.texi: Likewise. * doc/c-tic6x.texi: Likewise. * doc/c-tilegx.texi: Likewise. * doc/c-tilepro.texi: Likewise. * doc/c-v850.texi: Likewise. * doc/c-xgate.texi: Likewise. * doc/c-xtensa.texi: Likewise. * dwarf2dbg.c: Likewise. * ecoff.c: Likewise. * itbl-ops.c: Likewise. * listing.c: Likewise. * macro.c: Likewise. * po/gas.pot: Likewise. * read.c: Likewise. * struc-symbol.h: Likewise. * symbols.h: Likewise. * testsuite/gas/arc/relocs-errors.err: Likewise. * write.c: Likewise.
2017-01-20Fix potential array overrun in x86 assembler.Nick Clifton1-1/+1
* config/tc-i386.c (parse_operands): Check for operand overflow before setting the unspecified bit.
2017-01-18PR gas/20649: MIPS: Fix GOT16/LO16 reloc pairing with comdat sectionsMaciej W. Rozycki1-5/+6
Correct a regression from commit 8614eeee67f9 ("Traditional MIPS patches"), <https://sourceware.org/ml/binutils/2000-07/msg00018.html>, which caused symbols in linkonce or what is these days known as comdat sections to be treated as external for the purpose of PIC relocation generation even if their binding remains STB_LOCAL. This in turn disabled GOT16/LO16 relocation pairing with references to such symbols, as no complementing LO16 relocation is expected for external GOT16 references in the o32 ABI, which ultimately leads to link errors, e.g.: ld: comdat-reloc.o: Can't find matching LO16 reloc against `foo' for R_MIPS_GOT16 at 0x24 in section `.text.bar[bar]' as with the LD test case included with this change. Revert the special case for symbols in comdat sections then, making code actually match `adjust_reloc_syms' as indicated in its explanatory comment, and adjust calling code accordingly. Also bring back the corresponding description of what now is `s_is_linkonce', lost with commit 5f0fe04bc550 ("Improved MIPS16/MIPS32 code intermixing for gas."), <https://www.sourceware.org/ml/binutils/2006-07/msg00039.html>. gas/ PR gas/20649 * config/tc-mips.c (pic_need_relax): Don't check for linkonce symbols, remove the `segtype' parameter. (mips_frob_file, md_estimate_size_before_relax): Adjust accordingly. (s_is_linkonce): Add an explanatory comment. * testsuite/gas/mips/comdat-reloc.d: New test. * testsuite/gas/mips/comdat-reloc.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test. ld/ PR gas/20649 * testsuite/ld-mips-elf/mips-elf.exp: Add PIC comdat GOT16/LO16 relocation pairing link test.
2017-01-18Add support for processing lex source files with flex v 2.6.3Bernhard Rosenkranzer1-9/+2
PR 21059 binutils* arlex.l: Support processing with flex 2.6.3. * deflex.l: Likewise. gas * config/bfin-lex.l: Support processing with flex 2.6.3. * itbl-lex.l: Likewise.
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-0/+3
gas/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq. (cpu_noarch): Add noavx512_vpopcntdq. * doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq. * testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests. * testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file. * testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto. opcodes/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VPOPCNTDQ. * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. (i386_cpu_flags): Add cpuavx512_vpopcntdq. * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2017-01-09RISC-V/GAS: Support more relocs against constant addressesAndrew Waterman1-3/+2
Previously, some pseudoinstructions like "call" only accepted symbolic addresses and rejected constant addresses with an esoteric internal error. This patch enables them by deferring application of constant relocations to md_apply_fix, rather than eagerly applying them during instruction assembly. gas/ChangeLog 2017-01-09 Andrew Waterman <andrew@sifive.com> * config/tc-riscv.c (append_insn): Don't eagerly apply relocations against constants. (md_apply_fix): Mark relocations against constants as "done."
2017-01-09RISC-V/GAS: Improve handling of invalid relocsAndrew Waterman1-1/+9
TLS relocs against constants previously segfaulted, and illegal symbol subtractions were silently ignored. The previous behavior was to segfault. gas/ChangeLog 2017-01-09 Andrew Waterman <andrew@sifive.com> * config/tc-riscv.c (md_apply_fix): Report TLS relocations against constants. Report disallowed symbol subtractions.
2017-01-09RISC-V/GAS: Correct branch relaxation for weak symbols.Andrew Waterman1-0/+1
* config/tc-riscv.c (relaxed_branch_length): Use the long sequence when the target is a weak symbol.
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy1-0/+2
The weaker release consistency support of ARMv8.3-A is allowed as an optional extension for ARMv8.2-A, so separate command line option and feature flag is added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on. opcodes/ * aarch64-tbl.h (RCPC, RCPC_INSN): Define. (aarch64_opcode_table): Use RCPC_INSN. include/ * opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define. (AARCH64_ARCH_V8_3): Update. gas/ * config/tc-aarch64.c (aarch64_features): Add rcpc. * doc/c-aarch64.texi (AArch64 Extensions): Document rcpc. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.d: This. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.s: This. * testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng1-2/+12
gas * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA extension. (riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is enabled and no other ABI is specified. include * opcode/riscv-opc.h: Add support for the "q" ISA extension. opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA extension. * riscv-opcodes/all-opcodes: Likewise.
2017-01-03Fix PRU GAS for 32-bit hostsDimitar Dimitrov1-7/+12
The PRU GAS port I originally submitted does not build on 32bit hosts. This patch fixes it by aligning md_number_to_chars's definition with the global declaration in tc.h. Here is the original bug report I got: https://github.com/rcn-ee/repos/pull/23#issuecomment-269915175 * config/tc-pru.c (md_number_to_chars): Fix parameter to be valueT, as declared in tc.h. (md_apply_fix): Fix to work on 32-bit hosts. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
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