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This is a testcase for the bug fixed by commit 5b4846283c3d. When
running the testcase on ia64 targets I found timeouts along with lots
of memory being consumed, due to ia64 gas not tracking text
sub-sections. Trying to add nops for ".nop 16" in ".text 1" resulting
in them being added to subsegment 0, with no increase to subsegment 1
size. This patch also fixes that problem.
Note that the testcase fails on ft32-elf, mn10200-elf, score-elf,
tic5x-elf, and xtensa-elf. The first two are relocation errors, the
last three appear to be the .nop directive failing to emit the right
number of nops. I didn't XFAIL any of them.
* config/tc-ia64.c (md): Add last_text_subseg.
(ia64_flush_insns, dot_endp): Use last_text_subseg.
(ia64_frob_label, md_assemble): Set last_text_subseg.
* testsuite/gas/elf/dwarf2-21.d,
* testsuite/gas/elf/dwarf2-21.s: New test.
* testsuite/gas/elf/elf.exp: Run it.
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There are two main reasons for this patch,
* In the past we had two extension tables, one is used to record all
supported extensions in bfd/elfxx-riscv.c, another is used to get the
default extension versions in gas/config/tc-riscv.c. It is hard to
maintain lots of tables in different files, but in fact we can merge
them into just one table. Therefore, we now define many riscv_supported_std*
tables, which record names and versions for all supported extensions.
We not only use these tables to initialize the riscv_ext_order, but
also use them to get the default versions of extensions, and decide if
the extensions should be enbaled by default.
* We add a new filed `default_enable' for the riscv_supported_std* tables,
to decide if the extension should be enabled by default. For now if the
`default_enable' field of the extension is set to EXT_DEFAULT, then we
should enable the extension when the -march and elf architecture attributes
are not set. In the future, I suppose the `default_enable' can be set
to lots of EXT_<VENDOR>, each vendor can decide to open which extensions,
when the target triple of vendor is chosen.
The elf/linux regression tests of riscv-gnu-toolchain are passed.
bfd/
* elfnn-riscv.c (cpu-riscv.h): Removed sine it is included in
bfd/elfxx-riscv.h.
(riscv_merge_std_ext): Updated since the field of rpe is changed.
* elfxx-riscv.c (cpu-riscv.h): Removed.
(riscv_implicit_subsets): Added implicit extensions for g.
(struct riscv_supported_ext): Used to be riscv_ext_version. Moved
from gas/config/tc-riscv.c, and added new field `default_enable' to
decide if the extension should be enabled by default.
(EXT_DEFAULT): Defined for `default_enable' field.
(riscv_supported_std_ext): It used to return the supported standard
architecture string, but now we move ext_version_table from
gas/config/tc-riscv.c to here, and rename it to riscv_supported_std_ext.
Currently we not only use the table to initialize riscv_ext_order, but
also get the default versions of extensions, and decide if the extensions
should be enbaled by default.
(riscv_supported_std_z_ext): Likewise, but is used for z* extensions.
(riscv_supported_std_s_ext): Likewise, but is used for s* extensions.
(riscv_supported_std_h_ext): Likewise, but is used for h* extensions.
(riscv_supported_std_zxm_ext): Likewise, but is used for zxm* extensions.
(riscv_all_supported_ext): Includes all supported extension tables.
(riscv_known_prefixed_ext): Updated.
(riscv_valid_prefixed_ext): Updated.
(riscv_init_ext_order): Init the riscv_ext_order table according to
riscv_supported_std_ext.
(riscv_get_default_ext_version): Moved from gas/config/tc-riscv.c.
Get the versions of extensions from riscv_supported_std* tables.
(riscv_parse_add_subset): Updated.
(riscv_parse_std_ext): Updated.
(riscv_set_default_arch): Set the default subset list according to
the default_enable field of riscv_supported_*ext tables.
(riscv_parse_subset): If the input ARCH is NULL, then we call
riscv_set_default_arch to set the default subset list.
* elfxx-riscv.h (cpu-riscv.h): Included.
(riscv_parse_subset_t): Removed get_default_version field, and added
isa_spec field to replace it.
(extern riscv_supported_std_ext): Removed.
gas/
* (bfd/cpu-riscv.h): Removed.
(struct riscv_ext_version): Renamed and moved to bfd/elfxx-riscv.c.
(ext_version_table): Likewise.
(riscv_get_default_ext_version): Likewise.
(ext_version_hash): Removed.
(init_ext_version_hash): Removed.
(riscv_set_arch): Updated since the field of rps is changed. Besides,
report error when the architecture string is empty.
(riscv_after_parse_args): Updated.
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s_change_section() later calling obj_elf_section(), it seems better to pre-parse the section name by the same function that will be used there. This way no differences in what is accepted will result.
gas * config/tc-mips.c (s_change_section): Use obj_elf_section_name to
parse the section name.
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later calling obj_elf_section(), it seems better to pre-parse the section name by the same function that will be used there. This way no differences in what is accepted will result.
gas * config/tc-ia64.c (cross_section): Use obj_elf_section_name to
parse the section name.
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patches we have been grooming and maintaining for quite a few years over on git.haiku-os.org. All of these architectures are working and most have been stable for quite some time.
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PR 28292
gas * config/tc-v850.c (handle_lo16): Also accept
BFD_RELOC_V850_LO16_SPLIT_OFFSET.
* testsuite/gas/v850/split-lo16.s: Add extra line.
* testsuite/gas/v850/split-lo16.d: Update expected disassembly.
opcodes * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
of BFD_RELOC_16.
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The .insn directive can let users use their own instructions, or
some new instruction, which haven't supported in the old binutils.
For example, if users want to use sifive cache instruction, they
cannot just write "cflush.d1.l1" in the assembly code, they should
use ".insn i SYSTEM, 0, x0, x10, -0x40". But the .insn directive
may not easy to use for some cases, and not so friendly to users.
Therefore, I believe most of the users will use ".word 0xfc050073",
to encode the instructions directly, rather than use .insn. But
once we have supported the mapping symbols, the .word directives
are marked as data, so disassembler won't dump them as instructions
as usual. I have discussed this with Kito many times, we all think
extend the .insn direcitve to support the hardcode encoding, is the
easiest way to resolve the problem. Therefore, there are two more
.insn formats are proposed as follows,
(original) .insn <type>, <operand1>, <operand2>, ...
.insn <insn-length>, <value>
.insn <value>
The <type> is string, and the <insn-length> and <value> are constants.
gas/
* config/tc-riscv.c (riscv_ip_hardcode): Similar to riscv_ip,
but assembles an instruction according to the hardcode values
of .insn directive.
* doc/c-riscv.texi: Document two new .insn formats.
* testsuite/gas/riscv/insn-fail.d: New testcases.
* testsuite/gas/riscv/insn-fail.l: Likewise.
* testsuite/gas/riscv/insn-fail.s: Likewise.
* testsuite/gas/riscv/insn.d: Updated.
* testsuite/gas/riscv/insn.s: Likewise.
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Similar to ARM/AARCH64, we add mapping symbols in the symbol table,
to mark the start addresses of data and instructions. The $d means
data, and the $x means instruction. Then the disassembler uses these
symbols to decide whether we should dump data or instruction.
Consider the mapping-04 test case,
$ cat tmp.s
.text
.option norelax
.option norvc
.fill 2, 4, 0x1001
.byte 1
.word 0
.balign 8
add a0, a0, a0
.fill 5, 2, 0x2002
add a1, a1, a1
.data
.word 0x1 # No need to add mapping symbols.
.word 0x2
$ riscv64-unknown-elf-as tmp.s -o tmp.o
$ riscv64-unknown-elf-objdump -d tmp.o
Disassembly of section .text:
0000000000000000 <.text>:
0: 00001001 .word 0x00001001 # Marked $d, .fill directive.
4: 00001001 .word 0x00001001
8: 00000001 .word 0x00000001 # .byte + part of .word.
c: 00 .byte 0x00 # remaining .word.
d: 00 .byte 0x00 # Marked $d, odd byte of alignment.
e: 0001 nop # Marked $x, nops for alignment.
10: 00a50533 add a0,a0,a0
14: 20022002 .word 0x20022002 # Marked $d, .fill directive.
18: 20022002 .word 0x20022002
1c: 2002 .short 0x2002
1e: 00b585b3 add a1,a1,a1 # Marked $x.
22: 0001 nop # Section tail alignment.
24: 00000013 nop
* Use $d and $x to mark the distribution of data and instructions.
Alignments of code are recognized as instructions, since we usually
fill nops for them.
* If the alignment have odd bytes, then we cannot just fill the nops
into the spaces. We always fill an odd byte 0x00 at the start of
the spaces. Therefore, add a $d mapping symbol for the odd byte,
to tell disassembler that it isn't an instruction. The behavior
is same as Arm and Aarch64.
The elf/linux toolchain regressions all passed. Besides, I also
disable the mapping symbols internally, but use the new objudmp, the
regressions passed, too. Therefore, the new objudmp should dump
the objects corretly, even if they don't have any mapping symbols.
bfd/
pr 27916
* cpu-riscv.c (riscv_elf_is_mapping_symbols): Define mapping symbols.
* cpu-riscv.h: extern riscv_elf_is_mapping_symbols.
* elfnn-riscv.c (riscv_maybe_function_sym): Do not choose mapping
symbols as a function name.
(riscv_elf_is_target_special_symbol): Add mapping symbols.
binutils/
pr 27916
* testsuite/binutils-all/readelf.s: Updated.
* testsuite/binutils-all/readelf.s-64: Likewise.
* testsuite/binutils-all/readelf.s-64-unused: Likewise.
* testsuite/binutils-all/readelf.ss: Likewise.
* testsuite/binutils-all/readelf.ss-64: Likewise.
* testsuite/binutils-all/readelf.ss-64-unused: Likewise.
gas/
pr 27916
* config/tc-riscv.c (make_mapping_symbol): Create a new mapping symbol.
(riscv_mapping_state): Decide whether to create mapping symbol for
frag_now. Only add the mapping symbols to text sections.
(riscv_add_odd_padding_symbol): Add the mapping symbols for the
riscv_handle_align, which have odd bytes spaces.
(riscv_check_mapping_symbols): Remove any excess mapping symbols.
(md_assemble): Marked as MAP_INSN.
(riscv_frag_align_code): Marked as MAP_INSN.
(riscv_init_frag): Add mapping symbols for frag, it usually called
by frag_var. Marked as MAP_DATA for rs_align and rs_fill, and
marked as MAP_INSN for rs_align_code.
(s_riscv_insn): Marked as MAP_INSN.
(riscv_adjust_symtab): Call riscv_check_mapping_symbols.
* config/tc-riscv.h (md_cons_align): Defined to riscv_mapping_state
with MAP_DATA.
(TC_SEGMENT_INFO_TYPE): Record mapping state for each segment.
(TC_FRAG_TYPE): Record the first and last mapping symbols for the
fragments. The first mapping symbol must be placed at the start
of the fragment.
(TC_FRAG_INIT): Defined to riscv_init_frag.
* testsuite/gas/riscv/mapping-01.s: New testcase.
* testsuite/gas/riscv/mapping-01a.d: Likewise.
* testsuite/gas/riscv/mapping-01b.d: Likewise.
* testsuite/gas/riscv/mapping-02.s: Likewise.
* testsuite/gas/riscv/mapping-02a.d: Likewise.
* testsuite/gas/riscv/mapping-02b.d: Likewise.
* testsuite/gas/riscv/mapping-03.s: Likewise.
* testsuite/gas/riscv/mapping-03a.d: Likewise.
* testsuite/gas/riscv/mapping-03b.d: Likewise.
* testsuite/gas/riscv/mapping-04.s: Likewise.
* testsuite/gas/riscv/mapping-04a.d: Likewise.
* testsuite/gas/riscv/mapping-04b.d: Likewise.
* testsuite/gas/riscv/mapping-norelax-04a.d: Likewise.
* testsuite/gas/riscv/mapping-norelax-04b.d: Likewise.
* testsuite/gas/riscv/no-relax-align.d: Updated.
* testsuite/gas/riscv/no-relax-align-2.d: Likewise.
include/
pr 27916
* opcode/riscv.h (enum riscv_seg_mstate): Added.
opcodes/
pr 27916
* riscv-dis.c (last_map_symbol, last_stop_offset, last_map_state):
Added to dump sections with mapping symbols.
(riscv_get_map_state): Get the mapping state from the symbol.
(riscv_search_mapping_symbol): Check the sorted symbol table, and
then find the suitable mapping symbol.
(riscv_data_length): Decide which data size we should print.
(riscv_disassemble_data): Dump the data contents.
(print_insn_riscv): Handle the mapping symbols.
(riscv_symbol_is_valid): Marked mapping symbols as invalid.
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bfd/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add
'Tag_PACRET_use' case.
binutils/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* readelf.c (arm_attr_tag_PAC_extension): Declare.
(arm_attr_public_tags): Add 'PAC_extension' lookup.
elfcpp/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* arm.h: Define 'Tag_PACRET_use' enum.
gas/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (arm_convert_symbolic_attribute): Add
'Tag_PACRET_use' to the attribute_table.
include/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf/arm.h (elf_arm_reloc_type): Add 'Tag_PACRET_use'.
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bfd/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add
'Tag_BTI_use' case.
binutils/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* readelf.c (arm_attr_tag_PAC_extension): Declare.
(arm_attr_public_tags): Add 'PAC_extension' lookup.
elfcpp/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* arm.h: Define 'Tag_BTI_use' enum.
gas/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (arm_convert_symbolic_attribute): Add
'Tag_BTI_use' to the attribute_table.
include/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf/arm.h (elf_arm_reloc_type): Add 'Tag_BTI_use'.
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bfd/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add
'Tag_BTI_extension' case.
binutils/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* readelf.c (arm_attr_tag_PAC_extension): Declare.
(arm_attr_public_tags): Add 'PAC_extension' lookup.
elfcpp/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* arm.h: Define 'Tag_BTI_extension' enum.
gas/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (arm_convert_symbolic_attribute): Add
'Tag_BTI_extension' to the attribute_table.
include/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf/arm.h (elf_arm_reloc_type): Add 'Tag_BTI_extension'.
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bfd/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add
'Tag_PAC_extension' case.
binutils/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* readelf.c (arm_attr_tag_PAC_extension): Declare.
(arm_attr_public_tags): Add 'PAC_extension' lookup.
elfcpp/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* arm.h: Define 'Tag_PAC_extension' enum.
gas/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (arm_convert_symbolic_attribute): Add
'Tag_PAC_extension' to the attribute_table.
include/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf/arm.h (elf_arm_reloc_type): Add 'Tag_PAC_extension'.
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.tfloat output should always be 10 bytes without padding, independent
of psABIs. In glibc, x86 assembly codes expect 10-byte .tfloat output.
This also reduces .ds.x output and .tfloat output with hex input from
12 bytes to 10 bytes to match .tfloat output.
PR gas/28230
* NEWS: Mention changes of .ds.x output and .tfloat output with
hex input.
* config/tc-i386.c (x86_tfloat_pad): Removed.
* config/tc-i386.h (X_PRECISION_PAD): Changed to 0.
(x86_tfloat_pad): Removed.
* testsuite/gas/i386/fp.s: If NO_TFLOAT_PADDING isn't defined,
add explicit paddings after .tfloat, .ds.x, .dc.x and .dcb.x
directives.
* testsuite/gas/i386/i386.exp (ASFLAGS): Append
"--defsym NO_TFLOAT_PADDING=1" when running the fp test.
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When a symbol removed by .symver is used in relocation and there is one
and only one versioned symbol, don't remove the symbol. Instead, mark
it to be removed and replace the removed symbol used in relocation with
the versioned symbol before generating relocation.
PR gas/28157
* symbols.c (symbol_flags): Add removed.
(symbol_entry_find): Updated.
(symbol_mark_removed): New function.
(symbol_removed_p): Likewise.
* symbols.h (symbol_mark_removed): New prototype.
(symbol_removed_p): Likewise.
* write.c (write_relocs): Call obj_fixup_removed_symbol on
removed fixp->fx_addsy and fixp->fx_subsy if defined.
(set_symtab): Don't add a symbol if symbol_removed_p returns true.
* config/obj-elf.c (elf_frob_symbol): Don't remove the symbol
if it is used on relocation. Instead, mark it as to be removed
and issue an error if the symbol has more than one versioned name.
(elf_fixup_removed_symbol): New function.
* config/obj-elf.h (elf_fixup_removed_symbol): New prototype.
(obj_fixup_removed_symbol): New.
* testsuite/gas/symver/symver11.d: Updated expected error
message.
* testsuite/gas/symver/symver16.d: New file.
* testsuite/gas/symver/symver16.s: Likewise.
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exception handling control register name is DECNT not DCENT.
* config/rx-parse.y (DECNT): Fixed typo.
* testsuite/gas/rx/dpopm.sm (DECNT): Fixed typo.
* testsuite/gas/rx/dpushm.sm (DECNT): Fixed typo.
* testsuite/gas/rx/macros.inc (DECNT): Fixed typo.
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overlarge constant.
PR 28215
* config/tc-csky.c (md_apply_fix): Correctly handle a fixup that
involves an overlarge constant.
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Some frontends, like the gcc Objective-C frontend, emit symbols with $
characters in them. The AVR target code in gas treats $ as a line separator,
so the code doesn?t assemble correctly.
Provide a machine-specific option to disable treating $ as a line separator.
* config/tc-avr.c (enum options): Add option flag.
(struct option): Add option -mno-dollar-line-separator.
(md_parse_option): Adjust treatment of $ when option is present.
* config/tc-avr.h: Use avr_line_separator_chars.
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The respective results differ only by the sign bits - there's no need to
have basically identical (partially even arch-specific) logic twice.
Simply set the sign bit at the end of encoding the various formats.
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Like for infinity, there isn't just a single NaN. The sign bit may be
of interest and, going beyond infinity, whether the value is quiet or
signalling may be even more relevant to be able to encode.
Note that an anomaly with x86'es double extended precision NaN values
gets taken care of at the same time: For all other formats a positive
value with all mantissa bits set was used, while here a negative value
with all non-significant mantissa bits clear was chose for an unknown
reason.
For m68k, since I don't know their X_PRECISION floating point value
layout, a warning gets issued if any of the new flavors was attempted
to be encoded that way. However likely it may be that, given that the
code lives in a source file supposedly implementing IEEE-compliant
formats, the bit patterns of the individual words match x86'es, I didn't
want to guess so. And my very, very old paper doc doesn't even mention
floating point formats other than single and double.
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With x86 support having been implemented by extending atof-ieee.c, avoid
unnecessary code duplication in md_atof(). This will then also allow to
take advantage of adjustments made there without needing to mirror them
here.
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With x86 support having been implemented by extending atof-ieee.c, avoid
unnecessary code duplication in md_atof(). This will then also allow to
take advantage of adjustments made there without needing to mirror them
here.
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This is to be able to generate data acted upon by AVX512-BF16 and
AMX-BF16 insns. While not part of the IEEE standard, the format is
sufficiently standardized to warrant handling in config/atof-ieee.c.
Arm, where custom handling was implemented, may want to leverage this as
well. To be able to also use the hex forms supported for other floating
point formats, a small addition to the generic hex_float() is needed.
Extend existing x86 testcases.
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This is to be able to generate data passed to {,V}CVTPH2PS and acted
upon by AVX512-FP16 insns. To be able to also use the hex forms
supported for other floating point formats, a small addition to the
generic hex_float() is needed.
Extend existing x86 testcases.
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The ELF psABI-s are quite clear here: On 32-bit the underlying data type
is 12 bytes long (with 2 bytes of trailing padding), while on 64-bit it
is 16 bytes long (with 6 bytes of padding). Make s_space() capable of
handling 'x' (and 'p') type floating point being other than 12 bytes
wide (also adjusting documentation). This requires duplicating the
definition of X_PRECISION in the target speciifc header; the compiler
would complain if this was out of sync with config/atof-ieee.c.
Note that for now padding space doesn't get separated from actual
storage, which means that things will work correctly only for little-
endian cases, and which also means that by specifying large enough
numbers padding space can be set to non-zero. Since the logic is needed
for a single little-endian architecture only for now, I'm hoping that
this might be acceptable for the time being; otherwise the change will
become more intrusive.
Note also that this brings the emitted data size of .ds.x vs .tfloat in
line for non-ELF targets as well; the issue will be even more obvious
when further taking into account a subsequent patch fixing .dc.x/.dcb.x
(where output sizes currently differ depending on input format).
Extend existing x86 testcases.
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The ELF psABI-s are quite clear here: On 32-bit the data type is 12
bytes long (with 2 bytes of trailing padding), while on 64-bit it is 16
bytes long (with 6 bytes of padding). Make ieee_md_atof() capable of
handling such padding, and specify the needed padding for x86 (leaving
non-ELF targets alone for now). Split the existing x86 testcase.
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Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits
in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32
in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx).
There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8
operands predated our current conventions; those instructions moved to map 3.
FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3
is very sparsely populated. Most of the FP16 instructions share opcodes and
prefix (EVEX.pp) bits with the related FP32 operations.
Intel AVX512 FP16 instructions has new displacements scaling rules, please refer
to the public software developer manual for detail information.
gas/
2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Wei Xiao <wei3.xiao@intel.com>
Lili Cui <lili.cui@intel.com>
* config/tc-i386.c (struct Broadcast_Operation): Adjust comment.
(cpu_arch): Add .avx512_fp16.
(cpu_noarch): Add noavx512_fp16.
(pte): Add evexmap5 and evexmap6.
(build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6.
(check_VecOperations): Handle {1to32}.
(check_VecOperands): Handle CheckRegNumb.
(check_word_reg): Handle Toqword.
(i386_error): Add invalid_dest_and_src_register_set.
(match_template): Handle invalid_dest_and_src_register_set.
* doc/c-i386.texi: Document avx512_fp16, noavx512_fp16.
opcodes/
2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Wei Xiao <wei3.xiao@intel.com>
Lili Cui <lili.cui@intel.com>
* i386-dis.c (EXwScalarS): New.
(EXxh): Ditto.
(EXxhc): Ditto.
(EXxmmqh): Ditto.
(EXxmmqdh): Ditto.
(EXEvexXwb): Ditto.
(DistinctDest_Fixup): Ditto.
(enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode
and w_swap_mode.
(enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0,
PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56,
PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67,
PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11,
PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C,
PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F,
PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59,
PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1,
PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1,
PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E,
PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79,
PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C,
PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56,
PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7
(enum): Add EVEX_MAP5 and EVEX_MAP6.
(enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B,
EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0,
EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3,
EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2,
EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2,
(get_valid_dis386): Properly handle new instructions.
(intel_operand_size): Handle new modes.
(OP_E_memory): Ditto.
(OP_EX): Ditto.
* i386-dis-evex.h: Updated for AVX512_FP16.
* i386-dis-evex-mod.h: Updated for AVX512_FP16.
* i386-dis-evex-prefix.h: Updated for AVX512_FP16.
* i386-dis-evex-reg.h : Updated for AVX512_FP16.
* i386-dis-evex-w.h : Updated for AVX512_FP16.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS,
and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS
and CPU_ANY_AVX512BW_FLAGS.
(cpu_flags): Add CpuAVX512_FP16.
(opcode_modifiers): Add DistinctDest.
* i386-opc.h (enum): (AVX512_FP16): New.
(i386_opcode_modifier): Add reqdistinctreg.
(i386_cpu_flags): Add cpuavx512_fp16.
(EVEXMAP5): Defined as a macro.
(EVEXMAP6): Ditto.
* i386-opc.tbl: Add Intel AVX512_FP16 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Ditto.
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Global tbss symbols weren't correctly handled and were generating
a symbol with XTY_SD instead of XTY_CM as expected.
gas/
* config/tc-ppc.c (ppc_frog_symbol): Generate a XTY_CM when
a symbol has a storage class of XMC_UL.
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Most of the algorithms for XCOFF in tc-ppc.c assume that
the csects field of a ppc_xcoff_section isn't NULL.
This was already made for most of the sections with the creation
of a dummy symbol.
This patch simply mades it default when creating a xcoff_section.
gas/
* config/tc-ppc.c (ppc_init_xcoff_section): Always create
the dummy symbol.
(md_begin): Adjust ppc_init_xcoff_section call.
(ppc_comm): Likewise.
(ppc_change_csect): Likewise.
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debug_abbrev doesn't use end_exp to compute its size. However, it must
be NULL. Otherwise, ppc_xcoff_end might try to access uninitialized
memory.
gas/
* config/tc-ppc.c (ppc_dwsect): Use XCNEW instead of XNEW when creating
a new subsection.
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A C_BSTAT debug symbol specifies the beginning of a static block.
Its n_value is the index of the csect containing static symbols.
A C_STSYM debug symbol represents the stabstring of a statically
allocated symbol. Its n_value is the offset in the csect pointed
by the containing C_BSTAT.
These two special n_value were not correctly handled both when
generating object files with gas or when reading them with objdump.
This patch tries to improve that and, above all, to allow gas-generated
object files with such symbols to be accepted by AIX ld.
bfd/
* coff-bfd.c (bfd_coff_get_syment): Adjust n_value of symbols
having fix_value = 1 in order to be an index and not a memory
offset.
* coffgen.c (coff_get_symbol_info): Likewize.
(coff_print_symbol): Likewize.
gas/
* config/tc-ppc.c (ppc_frob_label): Don't change within if
already set.
(ppc_stabx): Remove workaround changing exp.X_add_symbol's
within.
* config/tc-ppc.h (struct ppc_tc_sy): Update comments.
* symbols.c (resolve_symbol_value): Remove symbol update
when final_val is 0 and it's an AIX debug symbol.
* testsuite/gas/ppc/aix.exp: Add new tests.
* testsuite/gas/ppc/xcoff-stsym-32.d: New test.
* testsuite/gas/ppc/xcoff-stsym-64.d: New test.
* testsuite/gas/ppc/xcoff-stsym.s: New test.
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If any pair of operands in AMX instructions with 3 TMM register operands
are the same, the instruction will UD. Don't call register_number to
check for distinct TMM register operands since all TMM register operands
have the same size.
* config/tc-i386.c (check_VecOperands): Remove register_number
call when checking for distinct TMM register operands.
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PowerPC gas and objdump for a long time have allowed certain -m/-M
options that extend a base cpu with extra functional units to be
specified before the base cpu. For example, "-maltivec -mpower4" is
the same as "-mpower4 -maltivec". See
https://sourceware.org/pipermail/binutils/2008-January/054935.html
It doesn't make as much sense that .machine keep any of these
"sticky" flags when handling a new base cpu. See gcc PR101393. I
think that instead .machine ought to override the command line.
That's what this patch does. It is still possible to extend cpu
functionality with .machine. For example the following can be
assembled when selecting a basic -mppc on the command line:
.machine power5
.machine altivec
frin 1,2
lvsr 3,4,5
Here, ".machine altivec" extends the ".machine power5" so that both
the power5 "frin" instruction and the altivec "lvsr" instruction are
enabled. Swapping the two ".machine" directives would result in
failure to assemble "lvsr".
This change will expose some assembly errors, such as the one in
glibc/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c, a file
compiled with -maltivec but containing
asm volatile (".machine push;\n"
".machine \"power5\";\n"
"vspltisb %0,0;\n"
"vspltisb %1,-1;\n"
"vpkuwus %0,%0,%1;\n"
"mfvscr %0;\n"
"stvx %0,0,%2;\n"
".machine pop;"
: "=v" (v0), "=v" (v1)
: "r" (vscr_ptr)
: "memory");
It's just wrong to choose power5 for a bunch of altivec instructions
and in fact all of those .machine directives are unnecessary.
* config/tc-ppc.c (ppc_machine): Don't use command line
sticky options.
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gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (reg_names): Alias 'ra_auth_code' to r12.
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gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (T16_32_TAB): Add '_pacg'.
(do_t_pacbti_pacg): New function.
(insns): Define 'pacg' insn.
* testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacg' test.
* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.
opcodes/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* arm-dis.c (thumb32_opcodes): Add 'pacg'.
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gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (T16_32_TAB): Add '_autg'.
(insns): Define 'autg' insn.
* testsuite/gas/arm/armv8_1-m-pacbti.d: Add autg test.
* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.
opcodes/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* arm-dis.c (thumb32_opcodes): Add 'autg'.
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gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (T16_32_TAB): Add '_bxaut'.
(do_t_pacbti_nonop): New function.
(insns): Define 'bxaut' insn.
* testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'bxaut' test.
* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.
opcodes/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* arm-dis.c (thumb32_opcodes): Add 'bxaut'.
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gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (pacbti_ext): Define.
(BAD_PACBTI): New macro.
(armv8_1m_main_ext_table): Add 'pacbti' extension.
include/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* opcode/arm.h (ARM_EXT3_PACBTI, ARM_AEXT3_V8_1M_MAIN_PACBTI): New
macro.
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gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (T16_32_TAB): Add '_pac'.
(insns): Add 'pac' insn.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Add pac tests.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise.
* testsuite/gas/arm/armv8_1-m-pacbti.d: Likewise.
* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.
opcodes/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* arm-dis.c (thumb32_opcodes): Add 'pac'.
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gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (insns): Add 'aut.'
(T16_32_TAB): Add '_aut'.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Add 'aut' tests.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise.
* testsuite/gas/arm/armv8_1-m-pacbti.d: Likewise.
* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.
opcodes/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* arm-dis.c (thumb32_opcodes): Add 'aut'.
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gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c
(enum operand_parse_code): Add OP_SP and OP_R12.
(parse_operands): Add switch cases for OP_SP and OP_R12.
(T16_32_TAB): Add '_pacbti'.
(do_t_pacbti): New function.
(insns): Add 'pacbti'.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.d: New file.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Likewise.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise.
* testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacbti' to testcase.
* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.
opcodes/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* arm-dis.c (thumb32_opcodes): Add 'pacbti' instruction.
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gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (insns): Add 'bti' insn.
* testsuite/gas/arm/armv8_1-m-pacbti.d: New file.
* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.
opcodes/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* arm-dis.c (thumb32_opcodes): Add bti instruction.
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Many places report errors of the nature "can't resolve a - b".
This provides a utility function to report such errors consistently.
I removed the section reporting and quotes around symbol names while I
was at it. Compare
ifunc-2.s:4: Error: can't resolve `bar1' {.text.1 section} - `foo1' {.text.1 section}
with
ifunc-2.s:4: Error: can't resolve bar1 - foo1
In many cases the section names don't help the user very much in
figuring out what went wrong, and the quotes if present arguably ought
to be placed around the entire expression:
can't resolve `bar1 - foo1'
The patch also tidies some tc_get_reloc functions that leak memory on
error paths.
* write.h (as_bad_subtract): Declare.
* write.c (as_bad_subtract): New function.
(fixup_segment): Use as_bad_subtract.
* config/tc-arc.c (md_apply_fix): Likewise.
* config/tc-avr.c (md_apply_fix, tc_gen_reloc): Likewise.
* config/tc-cris.c (md_apply_fix): Likewise.
* config/tc-d10v.c (md_apply_fix): Likewise.
* config/tc-d30v.c (md_apply_fix): Likewise.
* config/tc-ft32.c (md_apply_fix): Likewise.
* config/tc-h8300.c (tc_gen_reloc): Likewise.
* config/tc-m68hc11.c (md_apply_fix): Likewise.
* config/tc-mmix.c (mmix_frob_file): Likewise.
* config/tc-mn10200.c (tc_gen_reloc): Likewise.
* config/tc-nds32.c (nds32_apply_fix): Likewise.
* config/tc-pru.c (md_apply_fix): Likewise.
* config/tc-riscv.c (md_apply_fix): Likewise.
* config/tc-s12z.c (md_apply_fix): Likewise.
* config/tc-s390.c (md_apply_fix): Likewise.
* config/tc-tilegx.c (md_apply_fix): Likewise.
* config/tc-tilepro.c (md_apply_fix): Likewise.
* config/tc-v850.c (md_apply_fix): Likewise.
* config/tc-vax.c (md_apply_fix): Likewise.
* config/tc-xc16x.c (tc_gen_reloc): Likewise.
* config/tc-xgate.c (md_apply_fix): Likewise.
* config/tc-xstormy16.c (xstormy16_md_apply_fix): Likewise.
* config/tc-xtensa.c (md_apply_fix): Likewise.
* config/tc-z80.c (tc_gen_reloc): Likewise.
* config/tc-spu.c (md_apply_fix): Likewise.
(tc_gen_reloc): Delete dead code. Free memory on error.
* config/tc-cr16.c (tc_gen_reloc): Use as_bad_subtract. Free
on error.
* config/tc-crx.c (tc_gen_reloc): Likewise.
* config/tc-ppc.c (tc_gen_reloc): Likewise.
* testsuite/gas/i386/ifunc-2.l: Adjust to suit changed error message.
* testsuite/gas/mips/lui-2.l: Likewise.
* testsuite/gas/tic6x/reloc-bad-1.l: Likewise.
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gas/write.c provides a fallback TC_VALIDATE_FIX_SUB define that can be
a problem for some targets, the problem being that a non-zero
definition of TC_VALIDATE_FIX_SUB says that some uses of fx_subsy are
OK, in effect that the target will handle fx_subsy in md_apply_fix
and/or tc_gen_reloc. A lot of targets don't have the necessary
md_apply_fix and tc_gen_reloc support. So a safer default is to
disallow fx_subsy by default.
I've had a good look over target usage of fx_subsy, and think I've
caught all the cases where targets need TC_VALIDATE_FIX_SUB. Possible
failures would be limited to alpha, microblaze, ppc and s390 (the
targets that define UNDEFINED_DIFFERENCE_OK), or targets that generate
fixups with BFD_RELOC_GPREL32/16 and use a syntax explicitly showing
a difference expression.
* write.c (TC_VALIDATE_FIX_SUB): Default to 0.
* config/tc-hppa.h (TC_VALIDATE_FIX_SUB): Define.
* config/tc-microblaze.h (TC_VALIDATE_FIX_SUB): Define.
* config/tc-alpha.h (TC_VALIDATE_FIX_SUB): Define for ECOFF.
* config/tc-ppc.h (TC_VALIDATE_FIX_SUB): Don't define for ELF.
Do define for XCOFF.
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DWARF sections have special names on AIX which need be handled
by objdump in order to correctly print them.
This patch also adds the correlation in bfd for future uses.
bfd/
* libxcoff.h (struct xcoff_dwsect_name): Add DWARF name.
* coff-rs6000.c (xcoff_dwsect_names): Update.
* coffcode.h (sec_to_styp_flags): Likewise.
(coff_new_section_hook): Likewise.
binutils/
* dwarf.h (struct dwarf_section): Add XCOFF name.
* dwarf.c (struct dwarf_section_display): Update.
* objdump.c (load_debug_section): Add XCOFF name handler.
(dump_dwarf_section): Likewise.
gas/
* config/tc-ppc.c (ppc_change_debug_section): Update to
match new name's field.
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PR 28054
gas * config/obj-elf.c (obj_elf_change_section): Set the
SEF_ELF_OCTETS flag on debug sections.
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of a string.
PR 28051
gas * config/tc-i386.c (offset_in_range): Reformat error messages in
order to fix problems when translating.
(md_assemble): Likewise.
* messages.c (as_internal_value_out_of_range): Likewise.
* read.c (emit_expr_with_reloc): Likewise.
* testsuite/gas/all/overflow.l Change expected output format.
* po/gas.pot: Regenerate.
bfd * coff-rs6000.c (xcoff_reloc_type_tls): Reformat error messages in
order to fix problems when translating.
* cofflink.c (_bfd_coff_write_global_sym): Likewise.
* elfnn-aarch64.c (_bfd_aarch64_erratum_843419_branch_to_stub):
Likewise.
* po/bfd.pot: Regenerate.
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-> relocation.
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