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2015-11-27[AArch64] Add feature flags and command line for ARMv8.2 FP16 support.Matthew Wahab1-0/+2
ARMv8.2 adds optional support for 16-bit operations to the FP and Adv.SIMD instructions. This patch adds a feature macro for this support with a new command line option "+fp16" to enable/disable it. Although the command line option is added as an architecture extension, it only affects instructions available with when +fp or +simd is enabled. If +fp16 is specified then it will also enable +fp. There are currently no FP16 instructions implemented in binutils, this patch is to enable subsequent work on supporting the extension. gas/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_features): Add "fp16". * doc/c-aarch64.texi (Architecture Extensions): Add "fp16". include/opcode/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_F16): New. (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2 features. Change-Id: Id2021e0513946e16d0935c2a5b9605574cdff95a
2015-11-24[GAS, ARM] Invalid LDR immediate transformationChristophe Monat1-1/+2
2015-11-24 Christophe Monat <christophe.monat@st.com> * config/tc-arm.c (move_or_literal_pool): Do not transform ldr ri,=imm into movs when ri is a high register in T1. 2015-11-24 Christophe Monat <christophe.monat@st.com> * gas/arm/thumb2_ldr_immediate_armv6t2.s: Added high register tests. * gas/arm/thumb2_ldr_immediate_armv6t2.d: Accounted for new test cases. * gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: New. * gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: New.
2015-11-19[ARM] Add ARMv8.2 architecture feature and command line option.Matthew Wahab1-0/+1
ARMv8.2 is an architectural extension of ARMv8. This patch adds an architecture feature macro for ARMv8.2 to the binutils ARM target with GAS command line option -march=armv8.2-a. gas/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c (arm_archs): Add "armv8.2-a". * doc/c-arm.texi (-march): Add "armv8.2-a". include/opcode/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * arm.h (ARM_EXT2_V8_2A): New. (ARM_ARCH_V8_2A): New. Change-Id: I9e0f50e3c6cea24e6b87b8b862fd4e1cdcc1052e
2015-11-19[AArch64] Add ARMv8.2 command line option and feature flag.Matthew Wahab1-0/+1
ARMv8.2 is an architectural extension of ARMv8. This patch adds an architecture feature macro for ARMv8.2 to the binutils AArch64 target with GAS command line option -march=armv8.2-a. gas/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_archs): Add "armv8.2-a". * doc/c-aarch64.texi (-march): Likewise. include/opcode/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_V8_2): New. (AARCH64_ARCH_V8_2): New. Change-Id: I129232ab00234a07d18ce4b619607344acb3cbaf
2015-11-19Use default sub-segment align for non-ELF powerpcAlan Modra1-0/+2
Defining this to zero for COFF and PE meant that code sections were padded with zeros. The fact that no one has complained since 2006 says these targets are dead, I guess. * config/tc-ppc.h (SUB_SEGMENT_ALIGN): Define only for ELF.
2015-11-16gas: microblaze: fix shift overflowMike Frysinger1-1/+1
This code tries to shift an integer 31 bits which triggers a werror: gas/config/tc-microblaze.c:742:21: error: integer overflow in expression [-Werror=overflow] e->X_add_number |= -(1 << 31); Cast the 1 to offsetT to match X_add_number to fix things.
2015-11-12[AArch64] Add support for Cortex-A35James Greenhalgh1-0/+2
This patch adds support to the AArch64 back-end for the Cortex-A35 processor, as recently announced by ARM. The ARM Cortex-A35 provides full support for the ARMv8-A architecture, including the CRC extension, with optional Advanced-SIMD and Floating-Point support. We therefore set feature flags for this CPU to AARCH64_ARCH_V8 and AARCH64_FEATURE_CRC, in the same fashion as Cortex-A53 and Cortex-A57. Tested in a cross environment for AArch64 with no issues.
2015-11-12Add support for Cortex-A35Ramana Radhakrishnan1-0/+2
2015-11-12 James Greenhalgh <james.greenhalgh@arm.com> * config/tc-arm.c (arm_cpus): Likewise. * doc/c-arm.texi (-mcpu=): Likewise.
2015-11-12Fix PR gas/19217Ramana Radhakrishnan1-20/+11
2015-11-11 Matthew Wahab <matthew.wahab@arm.com> PR gas/19217 * config/tc-arm.c (move_or_literal_pool): Remove redundant feature check. Fix some code formatting. Drop use of MOVT. Add some comments. 2015-11-11 Matthew Wahab <matthew.wahab@arm.com> PR gas/19217 * gas/arm/thumb2_ldr_immediate_armv6t2.d: Update expected output.
2015-11-11Add assembler, disassembler and linker support for power9.Peter Bergner1-9/+22
include/opcode/ * ppc.h (PPC_OPCODE_POWER9): New define. (PPC_OPCODE_VSX3): Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries. Add PPC_OPCODE_VSX3 to the vsx entry. (powerpc_init_dialect): Set default dialect to power9. * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1, extract_l1 insert_xtq6, extract_xtq6): New static functions. (insert_esync): Test for illegal L operand value. (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6, XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA, XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK, XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3, PPCVSX3): New defines. (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu, fcmpo, ftdiv, ftsqrt>: Use XBF_MASK. <mcrxr>: Use XBFRARB_MASK. <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq., bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc., cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first, cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx, lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll, lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw, modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last, rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx, stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx, subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh, vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh., vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd, vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d, vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx, vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq, vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd, vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait, xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp, xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp, xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz, xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp, xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp, xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo, xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo, xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo, xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp, xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp, xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp, xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw, xxinsertw, xxperm, xxpermr, xxspltib>: New instructions. <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9. <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands. include/elf/ * ppc.h (R_PPC_REL16DX_HA): New reloction. * ppc64.h (R_PPC64_REL16DX_HA): Likewise. bfd/ * elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA. (ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA. (ppc_elf_addr16_ha_reloc): Likewise. (ppc_elf_check_relocs): Likewise. (ppc_elf_relocate_section): Likewise. (is_insn_dq_form): Handle lxv and stxv instructions. * elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA. (ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA. (ppc64_elf_ha_reloc): Likewise. (ppc64_elf_check_relocs): Likewise. (ppc64_elf_relocate_section): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. * reloc.c (BFD_RELOC_PPC_REL16DX_HA): New. elfcpp/ * powerpc.h (R_POWERPC_REL16DX_HA): Define. gas/ * doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * config/tc-ppc.c (md_show_usage): Likewise. (md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA. (md_apply_fix): Likewise. (ppc_handle_align): Handle power9's group ending nop. gas/testsuite/ * gas/ppc/altivec3.s: New test. * gas/ppc/altivec3.d: Likewise. * gas/ppc/vsx3.s: Likewise. * gas/ppc/vsx3.d: Likewise. * gas/ppc/power9.s: Likewise. * gas/ppc/power9.d: Likewise. * gas/ppc/ppc.exp: Run them. * gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests. * gas/ppc/power8.d: Likewise. * gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ... <lxvd2x, stxvd2x>: ...to this. * gas/ppc/vsx.d: Likewise. gold/ * gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function. (Powerpc_relocate_functions::addr16dx_ha): Likewise. (Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA. (Target_powerpc::Scan::global): Likewise. (Target_powerpc::Relocate::relocate): Likewise. ld/testsuite/ * ld-powerpc/addpcis.d: New test. * ld-powerpc/addpcis.s: New test. * ld-powerpc/powerpc.exp: Run it.
2015-11-10Add Qualcomm qdf24xx support.Jim Wilson2-0/+7
gas/ * config/tc-aarch64.c (aarch64_cpus): Add qdf24xx. * config/tc-arm.c (arm_cpus): Likewise. * doc/c-arm.texi, doc/c-aarch64.texi: Likewise.
2015-11-09gas: Fix left shift of negative value.Dominik Vogt44-53/+53
This patch fixes all occurences of left-shifting negative constants in C cod which is undefined by the C standard. gas/ChangeLog: * read.c (parse_bitfield_cons): Fix left shift of negative value. * config/tc-xstormy16.c (md_section_align): Likewise. * config/tc-xgate.c (md_section_align): Likewise. * config/tc-visium.c (md_section_align): Likewise. * config/tc-v850.c (md_section_align): Likewise. * config/tc-tic6x.c (md_section_align): Likewise. * config/tc-sh.c (SH64PCREL32_M, SH64PCREL48_M, SH64PCREL32_M) (MOVI_32_M, MOVI_48_M, MOVI_32_M, md_section_align): Likewise. * config/tc-sh64.c (shmedia_md_estimate_size_before_relax): Likewise. * config/tc-score.c (s3_section_align): Likewise. * config/tc-score7.c (s7_section_align): Likewise. * config/tc-s390.c (md_section_align): Likewise. * config/tc-rx.c (md_section_align): Likewise. * config/tc-rl78.c (md_section_align): Likewise. * config/tc-ppc.c (md_section_align): Likewise. * config/tc-or1k.c (md_section_align): Likewise. * config/tc-nds32.c (md_section_align): Likewise. * config/tc-mt.c (md_section_align): Likewise. * config/tc-msp430.c (md_section_align): Likewise. * config/tc-mn10300.c (md_section_align): Likewise. * config/tc-mn10200.c (md_section_align): Likewise. * config/tc-mips.c (md_section_align): Likewise. * config/tc-microblaze.c (parse_imm): Likewise. * config/tc-mep.c (md_section_align): Likewise. * config/tc-m68k.c (md_section_align): Likewise. * config/tc-m68hc11.c (md_section_align): Likewise. * config/tc-m32r.c (md_section_align): Likewise. * config/tc-m32c.c (md_section_align): Likewise. * config/tc-lm32.c (md_section_align): Likewise. * config/tc-iq2000.c (md_section_align): Likewise. * config/tc-ip2k.c (md_section_align): Likewise. * config/tc-ia64.c (dot_save, dot_vframe): Likewise. * config/tc-i960.c (md_number_to_field, md_section_align): Likewise. * config/tc-i386.c (md_section_align): Likewise. * config/tc-i370.c (md_section_align): Likewise. * config/tc-frv.c (md_section_align): Likewise. * config/tc-fr30.c (md_section_align): Likewise. * config/tc-epiphany.c (md_section_align): Likewise. * config/tc-d30v.c (md_section_align): Likewise. * config/tc-d10v.c (md_section_align): Likewise. * config/tc-cr16.c (l_cons): Likewise. * config/tc-bfin.c (md_section_align): Likewise. * config/tc-arm.c (md_section_align): Likewise. * config/tc-arc.c (md_section_align): Likewise. * config/bfin-parse.y (expr_1): Likewise. gas/testsuite/ChangeLog: * gas/all/test-gen.c (random_order_16s, random_order_24s) (random_order_32s): Fix left shift of negative value.
2015-11-02Fix disassembly of RX zero-offset register indirect instructions.Nick Clifton1-3/+3
opcode * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect. opcodes * rx-decode.opc (rx_disp): If the displacement is zero, set the type to RX_Operand_Zero_Indirect. * rx-decode.c: Regenerate. * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect. gas * config/rx-parse.y: Allow zero value for 5-bit displacements. tests * gas/rx/mov.sm: Add tests for zero offset indirect moves. * gas/rx/mov.d: Update expected output.
2015-11-02Fix the RX assembler's section alignment parameter to use multiples of N ↵Nick Clifton1-4/+4
rather than powers of N * config/tc-rx.c (parse_rx_section): Align parameter provides a multiple of n argument, not a power of n argument.
2015-10-29Add support for AArch64 CloudABI binaries.Ed Schouten1-0/+5
ld * Makefile.am (ALL_64_EMULATION_SOURCES): Add support for CloudABI on aarch64. For this target we have to make sure we use ELFOSABI_CLOUDABI instead of ELFOSABI_NONE. * configure.tgt (targ_emul): Likewise. * emulparams/aarch64cloudabi.sh: New file. * emulparams/aarch64cloudabib.sh: New file. * Makefile.in: Regenerate. bfd * config.bfd (targ_defvec): Add support for CloudABI on aarch64. For this target we have to make sure we use ELFOSABI_CLOUDABI instead of ELFOSABI_NONE. * configure.ac (tb): Likewise. * elfnn-aarch64.c: Likewise. * targets.c (_bfd_target_vector): Likewise. * configure: Regenerate. gas * config/tc-aarch64.c (elf64_aarch64_target_format): Select the cloudabi format if the TARGET_OS is cloudabi.
2015-10-29Fix CPS availability.Thomas Preud'homme1-1/+1
2015-10-29 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (insns): Guard cps by arm_ext_v6_notm instead of arm_ext_v6_dsp.
2015-10-28Fix errors in the gas testsuite for the ARC target.Cupertino Miranda1-189/+213
bfd * reloc.c (BFD_RELOC_ARC_32_PCREL): New entry. (ARC_TLS_DTPOFF): Arrange it in order. * elf32-arc.c (arc_elf_howto_ini): Update formula. (get_middle_endian_relocation): New function. (PDATA): Define. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. elf * arc-reloc.def (ARC_32_PCREL): New definition. gas * config/tc-arc.c (tokenize_arguments): Avoid creating unused symbols when parsing relocation types. (md_apply_fix): Handle TLS relocations. Fix BFD_RELOC_ARC_32_PCREL relocation. (arc_check_reloc): Emit BFD_RELOC_ARC_32_PCREL relocation.
2015-10-27Prevent overflowing the selected_cpu_name buffer in the ARM assembler.Jim Wilson1-2/+8
* config/tc-arm.c (selected_cpu_name): Increase length of array to accomodate "Samsung Exynos M1". (arm_parse_cpu): Add assertion and length check to prevent overfilling selected_cpu_name.
2015-10-22Add support for MSP430 silicon errata to the assembler.Nick Clifton1-79/+257
* config/tc-msp430.c (PUSH_1X_WORKAROUND): Delete. (OPTION_SILICON_ERRATA): Define. (OPTION_SILICON_WARN): Define. (md_parse_opton): Handle silicon errata options. (md_longopts): Add silicon errata options. (ms_show_usage): Report silicon errata options. (msp430_srcoperand): Handle silicon errata. (msp430_operands): Likewise. Improve nop insertion. (msp430_fix_adjustable): Update warning generation. * doc/c-msp430.texi: Document silicon errata options. tests * gas/msp430/errata_fixes.s: New test source file. * gas/msp430/errata_fixes.d: New test control file. * gas/msp430/errata_warns.s: New test source file. * gas/msp430/errata_warns.d: New test control file. * gas/msp430/errata_warns.l: New test message file. * gas/msp430/msp430.exp: Run the new tests. * gas/msp430/bad.l: Update expected warning messages * gas/msp430/msp430.exp: Run the new tests.
2015-10-22Add R_X86_64_[REX_]GOTPCRELX support to gas and ldH.J. Lu2-6/+15
This patch adds support for the R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX relocations proposed in https://groups.google.com/forum/#!topic/x86-64-abi/n9AWHogmVY0 to gas and ld. It updates gas to generate R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX if there is a REX prefix, relocation for memory operand, foo@GOTPCREL(%rip). With the locally defined symbol, foo, we convert mov foo@GOTPCREL(%rip), %reg to lea foo(%rip), %reg and convert call/jmp *foo@GOTPCREL(%rip) to nop call foo/jmp foo nop When PIC is false, convert test %reg, foo@GOTPCREL(%rip) to test $foo, %reg and convert binop foo@GOTPCREL(%rip), %reg to binop $foo, %reg where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions. bfd/ * elf64-x86-64.c: Include opcode/i386.h. (x86_64_elf_howto_table): Add R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. (R_X86_64_standard): Replace R_X86_64_PLT32_BND with R_X86_64_REX_GOTPCRELX. (x86_64_reloc_map): Add BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. (need_convert_mov_to_lea): Renamed to ... (need_convert_load): This. (elf_x86_64_check_relocs): Handle R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. Replace need_convert_mov_to_lea with need_convert_load. (elf_x86_64_gc_sweep_hook): Handle R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. (elf_x86_64_size_dynamic_sections): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_convert_mov_to_lea): Renamed to ... (elf_x86_64_convert_load): This. Replace need_convert_mov_to_lea with need_convert_load. Support R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX transformations. * reloc.c (BFD_RELOC_X86_64_GOTPCRELX): New. (BFD_RELOC_X86_64_REX_GOTPCRELX): Likewise. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. (tc_gen_reloc): Likewise. (i386_validate_fix): Generate BFD_RELOC_X86_64_GOTPCRELX or BFD_RELOC_X86_64_REX_GOTPCRELX if fx_tcbit2 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Also return true for BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. gas/testsuite/ * gas/i386/i386.exp: Run x86-64-gotpcrel. * gas/i386/x86-64-gotpcrel.d: New file. * gas/i386/x86-64-gotpcrel.s: Likewise. * gas/i386/ilp32/x86-64-gotpcrel.d: Likewise. * gas/i386/x86-64-localpic.d: Replace R_X86_64_GOTPCREL with R_X86_64_REX_GOTPCRELX. * gas/i386/ilp32/x86-64-localpic.d: Likewise. include/elf/ * x86-64.h (R_X86_64_GOTPCRELX): New. (R_X86_64_REX_GOTPCRELX): Likewise. ld/testsuite/ * ld-ifunc/ifunc-5r-local-x86-64.d: Replace R_X86_64_GOTPCREL with R_X86_64_REX_GOTPCRELX. * ld-x86-64/plt-main1.rd: Likewise. * ld-x86-64/plt-main3.rd: Likewise. * ld-x86-64/plt-main4.rd: Likewise. * ld-x86-64/gotpcrel1.dd: New file. * ld-x86-64/gotpcrel1.out: Likewise. * ld-x86-64/gotpcrel1a.S: Likewise. * ld-x86-64/gotpcrel1b.c: Likewise. * ld-x86-64/gotpcrel1c.c: Likewise. * ld-x86-64/gotpcrel1d.S: Likewise. * ld-x86-64/load1.s: Likewise. * ld-x86-64/load1a.d: Likewise. * ld-x86-64/load1b.d: Likewise. * ld-x86-64/load1c.d: Likewise. * ld-x86-64/load1d.d: Likewise. * ld-x86-64/x86-64.exp: Run load1a, load1b, load1c and load1d tests. Run gotpcrel1 test.
2015-10-22Add R_386_GOT32X support to gas and ldH.J. Lu1-14/+63
This patch adds support for the R_386_GOT32X relocation proposed in https://groups.google.com/forum/#!topic/ia32-abi/GbJJskkid4I to gas and ld. It updates gas to generate R_386_GOT32X relocation for memory operand, foo@GOT[(%reg)]. We must encode "mov foo@GOT, %eax" with the 0x8b opcode, instead of the 0xb8 opcode, so that it can be transformed to "lea foo, %eax". With the locally defined symbol, foo, we convert mov foo@GOT[(%reg1)], %reg2 to lea foo[@GOTOFF(%reg1)], %reg2 and convert call/jmp *foo@GOT[(%reg)] to nop call foo/jmp foo nop When PIC is false, convert test %reg1, foo@GOT[(%reg2)] to test $foo, %reg1 and convert binop foo@GOT[(%reg1)], %reg2 to binop $foo, %reg2 where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions. bfd/ * elf32-i386.c: Include opcode/i386.h. (elf_howto_table): Add R_386_GOT32X. (R_386_ext2): Replace R_386_IRELATIVE with R_386_GOT32X. (elf_i386_reloc_type_lookup): Handle BFD_RELOC_386_GOT32X. (need_convert_mov_to_lea): Renamed to ... (need_convert_load): This. (elf_i386_check_relocs): Handle R_386_GOT32X. Replace need_convert_mov_to_lea with need_convert_load. (elf_i386_gc_sweep_hook): Handle R_386_GOT32X. (elf_i386_size_dynamic_sections): Likewise. (elf_i386_relocate_section): Likewise. (elf_i386_convert_mov_to_lea): Renamed to ... (elf_i386_convert_load): This. Replace need_convert_mov_to_lea with need_convert_load. Support R_386_GOT32X transformations. * reloc.c (BFD_RELOC_386_GOT32X): New. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_386_GOT32X. (tc_gen_reloc): Likewise. (match_template): Force 0x8b encoding for "mov foo@GOT, %eax". (output_disp): Check for "call/jmp *mem", "mov mem, %reg", "test %reg, mem" and "binop mem, %reg" where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions. Set fx_tcbit if the REX prefix is generated. Set fx_tcbit2 if BFD_RELOC_386_GOT32X should be generated. (i386_validate_fix): Generate BFD_RELOC_386_GOT32X if fx_tcbit2 is set. gas/testsuite/ * gas/i386/got.d: New file. * gas/i386/got.s: Likewise. * gas/i386/i386.exp: Run got. * gas/i386/localpic.d: Replace R_386_GOT32 with R_386_GOT32X. * gas/i386/mixed-mode-reloc32.d: Likewise. * gas/i386/reloc32.d: Likewise. include/elf/ * i386.h (R_386_GOT32X): New relocation. ld/testsuite/ * ld-i386/branch1.d: New file. * ld-i386/branch1.s: Likewise. * ld-i386/call1.d: Likewise. * ld-i386/call1.s: Likewise. * ld-i386/call2.d: Likewise. * ld-i386/call2.s: Likewise. * ld-i386/got1.dd: Likewise. * ld-i386/got1.out: Likewise. * ld-i386/got1a.S: Likewise. * ld-i386/got1b.c: Likewise. * ld-i386/got1c.c: Likewise. * ld-i386/got1d.S: Likewise. * ld-i386/jmp1.d: Likewise. * ld-i386/jmp1.s: Likewise. * ld-i386/jmp2.d: Likewise. * ld-i386/jmp2.s: Likewise. * ld-i386/load1.d: Likewise. * ld-i386/load1.s: Likewise. * ld-i386/load2.d: Likewise. * ld-i386/load2.s: Likewise. * ld-i386/load3.d: Likewise. * ld-i386/load3.s: Likewise. * ld-i386/load4.s: Likewise. * ld-i386/load4a.d: Likewise. * ld-i386/load4b.d: Likewise. * ld-i386/load5.s: Likewise. * ld-i386/load5a.d: Likewise. * ld-i386/load5b.d: Likewise. * ld-i386/load6.d: Likewise. * ld-i386/load6.s: Likewise. * ld-i386/i386.exp: Run branch1, call1, call2, jmp1, jmp2, load1, load2, load3, load4a, load4b, load5a, load5b and load6 tests. Run got1 test.
2015-10-19Add a gas configure option to select the default behaviour for the ↵Nick Clifton1-6/+0
generation of debug sections - compressed or uncompressed. PR gas/19109 * configure.ac: Add option --enable-compressed-debug-sections. This sets the default behaviour for compressing debug sections. * as.c (flag_compress_debug): Define and initialise to COMPRESS_DEBUG_GABI_ZLIB if DEFAULT_COMPRESS_DEBUG is set. (show_usage): Indicate whether --no-compress-debug-sections or --compress-debug-sections is the default. * config/tc-i386.c (flag_compress_debug): Delete definition. * doc/as.texinfo (--nocompress-debug-sectionas): Update description. * NEWS: Announce the new feature. * config.in: Regenerate. * configure: Regenerate.
2015-10-12Update list of known MSP430 MCU names.Nick Clifton1-62/+614
* config/tc-msp430.c (msp430_mcu_names): Rename to msp430_mcu_data. Add fields for the ISA and hardware multiply support. Update with information from the latest devices.csv file. (md_parse_option): Make use of the new array.
2015-10-12avr: Fix bugs in org/align tracking.Andrew Burgess1-3/+7
This commit fixes a few issues in the mechanism for passing information about ".org" and ".align" directives from the assembler to the linker, used by the avr target. In the original commit fdd410ac7a07dfb47dcb992201000582a280d8b2, there were some mistakes when writing out information about ".align" directives: - An align with fill does not write out its information correctly, the fill data overwrites the alignment data. - Each alignment directive is recorded at the location where the previous alignment directive should be recorded, the first alignment directive is discarded. In commit 137c83d69fad77677cc818593f9399caa777a0c5, the data produced by objdump is not correct: - It's miss-aligned due to a missing whitespace. - The fill data for align with fill records is not displayed correctly. All of the above issues are addressed in this commit, and the test is improved to cover these cases. binutils/ChangeLog: * od-elf32_avr.c (elf32_avr_dump_avr_prop): Fix printing of align specific data, fix formatting for align and org data. gas/ChangeLog: * config/tc-avr.c (avr_output_property_record): Fix overwrite bug for align and fill records. (avr_handle_align): Record fill information for align frags. (create_record_for_frag): Add next frag assertion, use correct address for align records. gas/testsuite/ChangeLog: * gas/avr/avr-prop-1.s: Use fill in some cases. * gas/avr/avr-prop-1.d: Update expected results.
2015-10-07Avoid using 'template' C++ keywordYao Qi1-8/+8
'template' is used in include/opcode/aarch64.h as below, typedef struct { const char *template; uint32_t value; int has_xt; } aarch64_sys_ins_reg; and it triggers compilation errors when GDB is built in C++ mode. In file included from git/gdb/aarch64-tdep.c:62:0: git/gdb/../include/opcode/aarch64.h:651:15: error: expected unqualified-id before 'template' const char *template; This patch is to rename field template to name. gas/ * config/tc-aarch64.c (md_begin): Access field 'name' rather than 'template'. include/opcode/ * aarch64.h (aarch64_sys_ins_reg) <template>: Removed. <name>: New field. opcodes/ * aarch64-dis.c (aarch64_ext_sysins_op): Access field 'name' rather than 'template'. * aarch64-opc.c (aarch64_print_operand): Likewise.
2015-10-07New ARC implementation.Nick Clifton2-1514/+2879
bfd * archures.c: Remove support for older ARC. Added support for new ARC cpus (ARC600, ARC601, ARC700, ARCV2). * bfd-in2.h: Likewise. * config.bfd: Likewise. * cpu-arc.c: Likewise. * elf32-arc.c: Totally changed file with a refactored inplementation of the ARC port. * libbfd.h: Added ARC specific relocation types. * reloc.c: Likewise. gas * config/tc-arc.c: Revamped file for ARC support. * config/tc-arc.h: Likewise. * doc/as.texinfo: Add new ARC options. * doc/c-arc.texi: Likewise. ld * configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*. * emulparams/arcebelf_prof.sh: New file * emulparams/arcebelf.sh: Likewise. * emulparams/arceblinux_prof.sh: Likewise. * emulparams/arceblinux.sh: Likewise. * emulparams/arcelf_prof.sh: Likewise. * emulparams/arcelf.sh: Likewise. * emulparams/arclinux_prof.sh: Likewise. * emulparams/arclinux.sh: Likewise. * emulparams/arcv2elfx.sh: Likewise. * emulparams/arcv2elf.sh: Likewise. * emultempl/arclinux.em: Likewise. * scripttempl/arclinux.sc: Likewise. * scripttempl/elfarc.sc: Likewise. * scripttempl/elfarcv2.sc: Likewise * Makefile.am: Add new ARC emulations. * Makefile.in: Regenerate. * NEWS: Mention the new feature. opcodes * arc-dis.c: Revamped file for ARC support * arc-dis.h: Likewise. * arc-ext.c: Likewise. * arc-ext.h: Likewise. * arc-opc.c: Likewise. * arc-fxi.h: New file. * arc-regs.h: Likewise. * arc-tbl.h: Likewise. binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact and ARCv2. (get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT. (guess_is_rela): Likewise. (dump_relocations): Likewise. (is_32bit_abs_reloc): Likewise. (is_16bit_abs_reloc): Likewise. (is_none_reloc): Likewise. * NEWS: Mention the new feature. include * dis-asm.h (arc_get_disassembler): Correct declaration. * arc-reloc.def: Macro file with definition of all relocation types. * arc.h: Changed macros for the newly supported ARC cpus. Altered enum defining the supported relocations. * common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added macro for EM_ARC_COMPACT2. * arc-func.h: New file. * arc.h: Likewise.
2015-10-02[GAS][AARCH64]Add TLSDESC large memory model support.Renlin Li1-0/+71
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * elfnn-aarch64.c (elfNN_aarch64_howto_table): Check overflow for BFD_RELOC_AARCH64_TLSDESC_OFF_G1. gas/ 2015-10-02 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (s_tlsdescadd): New. (s_tlsdescldr): New. (md_pseudo_table): Handle tlsdescadd and tlsdescldr pseudo ops. (reloc_table): Add entries for BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC and BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC. (process_movw_reloc_info): Support AARCH64_TLSDESC_OFF_G1 and AARCH64_TLSDESC_OFF_G0_NC. (md_apply_fix): Likewise. (aarch64_force_relocation): Likewise. gas/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * gas/aarch64/reloc-tlsdesc_off_g0_nc.d: New. * gas/aarch64/reloc-tlsdesc_off_g0_nc.s: New. * gas/aarch64/reloc-tlsdesc_off_g1.d: New. * gas/aarch64/reloc-tlsdesc_off_g1.s: New. * gas/aarch64/tls-desc.d: New. * gas/aarch64/tls-desc.s: New.
2015-10-02[Binutils][AARCH64]Add TLS IE large memory support.Renlin Li1-1/+25
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * reloc.c: Make AARCH64_TLSIE_MOVW_GOTTPREL_G1 and AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC defined in alphabetical order. * libbfd.h: Regenerate. * bfd-in2.h: Likewise. * elfnn-aarch64.c (elfNN_aarch64_howto_table): Make TLSIE_MOVW_GOTTPREL_G1 check overflow. (aarch64_reloc_got_type): Add support for TLSIE_MOVW_GOTTPREL_G1 and TLSIE_MOVW_GOTTPREL_G0_NC. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. gas/ 2015-10-02 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reloc_table): Add two entries for gottprel_g0_nc and gottprel_g1. (process_movw_reloc_info): Add support. (md_apply_fix): Likewise. (aarch64_force_relocation): Likewise. gas/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * gas/aarch64/reloc-gottprel_g0_nc.d: New. * gas/aarch64/reloc-gottprel_g0_nc.s: New. * gas/aarch64/reloc-gottprel_g1.d: New. * gas/aarch64/reloc-gottprel_g1.s: New. ld/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * ld-aarch64/tls-large-ie.d: New. * ld-aarch64/tls-large-ie.s: New. * ld-aarch64/aarch64-elf.exp: Run new test.
2015-10-02[GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC support.Renlin Li1-0/+12
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * reloc.c (BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC): New entry. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC. * libbfd.h: Regenerate. * bfd-in2.h: Likewise gas/ 2015-10-02 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reloc_table): New relocation modifier tlsgd_g0_nc. (process_movw_reloc_info): Support BFD_RELOC_AARCH64_TLSGD_MOVW_G1. (md_apply_fix): Likewise. (aarch64_force_relocation): Likewise. gas/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * gas/aarch64/reloc-tlsgd_g0_nc.d: New. * gas/aarch64/reloc-tlsgd_g0_nc.s: New.
2015-10-02[GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSGD_MOVW_G1 support.Renlin Li1-0/+13
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * reloc.c (BFD_RELOC_AARCH64_TLSGD_MOVW_G1): New entry. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_TLSGD_MOVW_G1. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. gas/ 2015-10-02 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reloc_table): New relocation modifier tlsgd_g1. (process_movw_reloc_info): Support BFD_RELOC_AARCH64_TLSGD_MOVW_G1. (md_apply_fix): Likewise. (aarch64_force_relocation): Likewise. gas/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * gas/aarch64/reloc-tlsgd_g1.s: New. * gas/aarch64/reloc-tlsgd_g1.s: New.
2015-10-02[GAS][AARCH64]Add BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC Support.Renlin Li1-0/+11
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * reloc.c (BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC): New. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry MOVW_GOTOFF_G0_NC. * libbfd.h: Regnerate. * bfd-in2.h: Regenerate. gas/ 2015-10-02 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reloc_table): New relocation modifier gotoff_g0_nc. (process_movw_reloc_info): Support gotoff_g0_nc. (md_apply_fix): Likewise. gas/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * gas/aarch64/reloc-gotoff_g0_nc.s: New. * gas/aarch64/reloc-gotoff_g0_nc.d: New.
2015-10-02[GAS][AARCH64]Add BFD_RELOC_AARCH64_MOVW_GOTOFF_G1 Support.Renlin Li1-0/+12
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * reloc.c (BFD_RELOC_AARCH64_MOVW_GOTOFF_G1): New. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for MOVW_GOTOFF_G1. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ 2015-10-02 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reloc_table): New relocation modifier gotoff_g1. (process_movw_reloc_info): Support newly added modifier. (md_apply_fix): Likewise. gas/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * gas/aarch64/reloc-gotoff_g1.s: New. * gas/aarch64/reloc-gotoff_g1.d: New.
2015-09-29Add support for extensions in the .machine pseudoop on S/390, e.g. ".machine ↵Dominik Vogt1-45/+176
zEC12+nohtm+vx" gas * doc/c-s390.texi: Add documentation. Add missing code markup. * config/tc-s390.c (current_flags): New static variable. (s390_parse_cpu): Parse cpu flags a la "+nohtm" etc. (s390_setup_opcodes): Use cpu flags to determine the set of opcodes. Fix indentation. (md_parse_option): Call s390_parse_cpu with the new signature. (s390_machine): Likewise. Keep track of current_flags. Simplify code a bit. undefine MAX_HISTORY at end of function. (s390_machinemode): undefine MAX_HISTORY at end of function. Update an error message. tests * gas/s390/s390.exp: Add new tests. * gas/s390/machine-parsing-1.s: New test file. * gas/s390/machine-parsing-1.l: Likewise. * gas/s390/machine-parsing-2.s: Likewise. * gas/s390/machine-parsing-2.l: Likewise. * gas/s390/machine-parsing-3.s: Likewise. * gas/s390/machine-parsing-3.l: Likewise. * gas/s390/machine-parsing-4.s: Likewise. * gas/s390/machine-parsing-4.l: Likewise. * gas/s390/machine-parsing-5.s: Likewise. * gas/s390/machine-parsing-5.l: Likewise. * gas/s390/machine-parsing-6.s: Likewise. * gas/s390/machine-parsing-6.l: Likewise. opcode * s390.h (S390_INSTR_FLAG_HTM): New flag. (S390_INSTR_FLAG_VX): New flag. (S390_INSTR_FLAG_FACILITY_MASK): New flag mask. opcodes * s390-mkopc.c (main): Parse htm and vx flag. * s390-opc.txt: Mark instructions from the hardware transactional memory and vector facilities with the "htm"/"vx" flag.
2015-09-25Correct the generation of OR1K pc-relative relocations.Peter Zotov2-18/+48
gas PR ld/18759 * config/tc-or1k.c (tc_gen_reloc): Correct computation of PC relative relocs. * config/tc-or1k.h (GAS_CGEN_PRCEL_R_TYPE): Delete. bfd * elf32-or1k.c (R_OR1K_32_PCREL): Set pcrel_offset to TRUE. (R_OR1K_16_PCREL): Likewise. (R_OR1K_8_PCREL): Likewise. ld/tests * ld-elf/eh-frame-hdr: Expect to pass on the or1k-linux target.
2015-09-23Fix compile time warnings generated when compiling with clang.Nick Clifton1-1/+1
bfd * bout.c (b_out_slurp_reloc_table): Cast constant to unsigned in order to avoid problems with left shifting negative values. (abs32code): Likewise. * mach-o.c (FILE_ALIGN): Likewise. * coff-rs6000.c (xcoff_debug_sections): Delete unused static array. * elf32-visium.c (visium_reloc_map): Likewise. * elf32-arm.c (elf32_arm_final_link_relocate): Remove useless calls to abs function. * elf32-frv.c (_frvfdpic_relax_tls_entries): Likewise. * elf32-score.c (score_elf_final_link_relocate): Likewise. * elf32-score7.c (score_elf_final_link_relocate): Likewise. * elf32-i860.c (i860_howto_pc26_reloc): Use multiplication instead of shifting to create a negative mask. * elf32-msp430.c (elf_backend_special_sections): Define. * elfxx-mips.c (got_ofst_reloc_p): Delete unused function. (got_hi16_reloc_p): Delete unused function. * ppcboot.c (ppcboot_bfd_print_private_bfd_data): Fix test of partition name. gas * config/tc-ppc.c (insn_validate): Cast PPC_OPSHIFT_INV to an int. opcode * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left shifting. ld * emultempl/elf32.em (ehdr_start_empty): New static variable. (before_allocation): Use it to initialise ehdr_start_save. * emultempl/pe.em (write_build_id): Remove useless double parenthesis. * emultempl/pep.em (write_build_id): Likewise. opcodes * bfin-dis.c (fmtconst): Remove unnecessary call to the abs function. * tic30-dis.c (print_branch): Likewise. * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed value before left shifting. * fr30-ibld.c (fr30_cgen_extract_operand): Likewise. * hppa-dis.c (print_insn_hppa): Likewise. * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static array. * msp430-dis.c (msp430_singleoperand): Likewise. (msp430_doubleoperand): Likewise. (print_insn_msp430): Likewise. * nds32-asm.c (parse_operand): Likewise. * sh-opc.h (MASK): Likewise. * v850-dis.c (get_operand_value): Likewise.
2015-09-22Change 7-byte NOP instruction for RX target, so that it only takes 1 cycle ↵Nick Clifton1-2/+2
to excute. * config/tc-rx.c (nop_7): Recode using MAX.
2015-09-08config/tc-avr.c (md_section_align): Append UL for -1 to avoid the latest ↵Chen Gang1-1/+1
gcc's warning The related warning is: gcc -DHAVE_CONFIG_H -I. -I../../binutils-gdb/gas -I. -I../../binutils-gdb/gas -I../bfd -I../../binutils-gdb/gas/config -I../../binutils-gdb/gas/../include -I../../binutils-gdb/gas/.. -I../../binutils-gdb/gas/../bfd -DLOCALEDIR="\"/upstream/release-avr32/share/locale\"" -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Werror -I../../binutils-gdb/gas/../zlib -g -O2 -MT tc-avr.o -MD -MP -MF .deps/tc-avr.Tpo -c -o tc-avr.o `test -f 'config/tc-avr.c' || echo '../../binutils-gdb/gas/'`config/tc-avr.c ../../binutils-gdb/gas/config/tc-avr.c: In function ‘md_section_align’: ../../binutils-gdb/gas/config/tc-avr.c:1233:43: error: left shift of negative value [-Werror=shift-negative-value] return ((addr + (1 << align) - 1) & (-1 << align)); ^ 2015-09-05 Chen Gang <gang.chen.5i5j@gmail.com> * config/tc-avr.c (md_section_align): Append UL for -1 to avoid the latest gcc's warning.
2015-08-27More fallout from "Allow symbol and label names to be enclosed in double quotes"Alan Modra16-88/+97
Some of the TC_START_LABEL implementations need to adjust the end of the symbol, when a colon doesn't mean a label definition. That means they need access to nul_char both the restore the NUL location (it may be a quote rather than a colon) and to store the new nul_char. Others need adjusting to step over a potential trailing quote. PR gas/18581 * config/tc-aarch64.h (TC_START_LABEL): Redefine. * config/tc-arm.c (tc_start_label_without_colon): Delete params. Use input_line_pointer directly. * config/tc-arm.h (TC_START_LABEL): Redefine. (TC_START_LABEL_WITHOUT_COLON): Redefine. (tc_start_label_without_colon): Update prototype. * config/tc-bfin.c (bfin_start_label): Delete ptr param. Check for NUL instead. * config/tc-bfin.h (bfin_start_label): Update prototype. (TC_START_LABEL): Redefine. * config/tc-d30v.h (TC_START_LABEL): Redefine. * config/tc-fr30.c (restore_colon): Rewrite. (fr30_is_colon_insn): Add nul_char param. Return int. Bump i_l_p over quote. Update restore_colon calls. * config/tc-fr30.h (TC_START_LABEL): Redefine. (fr30_is_colon_insn): Update prototype. * config/tc-m32c.c (restore_colon, m32c_is_colon_insn): As above. * config/tc-m32c.h (TC_START_LABEL): Redefine. (m32c_is_colon_insn): Update prototype. * config/tc-m32r.h (TC_START_LABEL): Redefine. * config/tc-mep.h (TC_START_LABEL): Redefine. * config/tc-nds32.h (TC_START_LABEL): Redefine. * config/tc-tic54x.c (tic54x_start_label): Replace params with nul_char and next_char. Step over trailing quote. * config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Redefine. (tic54x_start_label): Update prototype. * read.c (TC_START_LABEL): Redefine. Update invocation. (TC_START_LABEL_WITHOUT_COLON): Update invocation. * config/tc-nios2.c (s_nios2_set): Save initial input_line_pointer and restore if calling s_set. Don't restore delim again.
2015-08-26Fallout from "Allow symbol and label names to be enclosed in double quotes"Alan Modra3-4/+4
PR gas/18581 * config/tc-mn10200.c (md_assemble <mdr>): Move restore_line_pointer call to where input line used to be restored. * config/tc-mn10300.c (md_assemble <usp>): Remove redundant input line restore. * config/tc-tilepro.c (parse_reg_expression): Add regname var.
2015-08-25Support for the sparc %pmcdper privileged register.Jose E. Marchesi1-0/+1
opcodes/ChangeLog: 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-dis.c (print_insn_sparc): Handle the privileged register %pmcdper. gas/ChangeLog: 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (priv_reg_table): New privileged register %pmcdper. gas/testsuite/ChangeLog: 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com> * gas/sparc/wrpr.s: Test writing to the privileged %pmcdper register. * gas/sparc/wrpr.d: ...and the expected result. * gas/sparc/rdpr.s: Test reading from the privileged %pmcdper register. * gas/sparc/rdpr.d: ...and the expected result.
2015-08-21Allow symbol and label names to be enclosed in double quotes.Nick Clifton41-744/+606
gas PR gas/18581 * expr.c (get_symbol_end): Rename to get_symbol_name. Add a return parameter pointing to the start of the symbol. Allow symbol names enclosed in double quotes. (restore_line_pointer): New function. Replace the NUL character inserted into the input stream with the given character. If the character was a double quote, advance the input pointer. * expr.h (get_symbol_end): Delete. (get_symbol_name): Add prototype. (restore_line_pointer): Prototype. * read.h (SKIP_WHITESPACE_AFTER_NAME): New macro. * doc/as.texinfo (Symbol Intro): Document that symbol names can now be enclosed in double quotes. * cond.c (s_ifdef): Replace get_symbol_end with get_symbol_name. Use restore_line_pointer to replace the NUL in the input stream. Use SKIP_WHITESPACE_AFTER_NAME to skip past the end of a symbol. Check for the use of double quoted symbol names. * expr.c: Likewise. * config/obj-aout.c: Likewise. * config/obj-coff-seh.c: Likewise. * config/obj-coff.c: Likewise. * config/obj-elf.c: Likewise. * config/obj-evax.c: Likewise. * config/obj-macho.c: Likewise. * config/obj-som.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-h8300.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i370.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-iq2000.c: Likewise. * config/tc-m32r.c: Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-nios2.c: Likewise. * config/tc-ppc.c: Likewise. * config/tc-s390.c: Likewise. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sparc.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-tic6x.c: Likewise. * config/tc-tilegx.c: Likewise. * config/tc-tilepro.c: Likewise. * config/tc-v850.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * dw2gencfi.c: Likewise. * dwarf2dbgc.: Likewise. * ecoff.c: Likewise. * read.c: Likewise. * stabs.c: Likewise. tests PR gas/18581 * gas/all/byte.d: Disable this test. Quoted expressions are now allowed in .byte directives. * gas/all/quoted-sym-names.s: New test. * gas/all/quoted-sym-names.d: Expected output. * gas/all/gas.exp: Run the new test.
2015-08-19[AArch64][5/6] GAS support TLSLD load/store relocation typesJiong Wang1-10/+58
2015-08-19 Jiong Wang <jiong.wang@arm.com> bfd/ * reloc.c: New entries, including BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC. BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC. * elfnn-aarch64.c (elfNN_aarch64_howto_table): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-aarch64.c (reloc_table): New relocation types support for dtprel_lo12. (ldst_lo12_determine_real_reloc_type): Support BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC. (parse_operands): Likewise. (md_apply_fix): Likewise (aarch64_force_relocation): Likewise. (process_movw_reloc_info): Likewise. gas/testsuite/ * gas/aarch64/reloc-dtprel_lo12-ldst8.s: New testcase. * gas/aarch64/reloc-dtprel_lo12_nc-ldstc.s: Likewise. * gas/aarch64/reloc-dtprel_lo12-ldst16.s: Likewise. * gas/aarch64/reloc-dtprel_lo12_nc-ldst16.s: Likewise. * gas/aarch64/reloc-dtprel_lo12-ldst32.s: Likewise. * gas/aarch64/reloc-dtprel_lo12_nc-ldst32.s: Likewise. * gas/aarch64/reloc-dtprel_lo12-ldst64.s: Likewise. * gas/aarch64/reloc-dtprel_lo12_nc-ldst64.s: Likewise. * gas/aarch64/reloc-dtprel_lo12-ldst8.d: New expectation file. * gas/aarch64/reloc-dtprel_lo12_nc-ldst8.d: Likewise. * gas/aarch64/reloc-dtprel_lo12-ldst16.d: Likewise. * gas/aarch64/reloc-dtprel_lo12_nc-ldst16.d: Likewise. * gas/aarch64/reloc-dtprel_lo12-ldst32.d: Likewise. * gas/aarch64/reloc-dtprel_lo12_nc-ldst32.d: Likewise. * gas/aarch64/reloc-dtprel-lo12-ldst64.d: Likewise. * gas/aarch64/reloc-dtprel_lo12_nc-ldst64.d: Likewise.
2015-08-19[AArch64][3/6] GAS support TLSLD move/add relocation typesJiong Wang1-0/+71
2015-08-19 Jiong Wang <jiong.wang@arm.com> bfd/ * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12, BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0, BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC, BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1, BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC, BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2): New entries. * elfnn-aarch64.c (elfNN_aarch64_howto_table): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-aarch64.c (reloc_table): New relocation modifiers, "dtprel_hi12", "dtprel_g0", "dtprel_g0_nc", "dtprel_g1", "dtprel_g1_nc", "dtprel_g2". (md_apply_fix): Support new relocation types. (aarch64_force_relocation): Likewise. (process_movw_reloc_info): Likewise. gas/testsuite/ * gas/aarch64/reloc-dtprel_g0.s: New testcase. * gas/aarch64/reloc-dtprel_g0-ilp32.s: Likewise. * gas/aarch64/reloc-dtprel_g0_nc.s: Likewise. * gas/aarch64/reloc-dtprel_g0_nc-ilp32.s: Likewise. * gas/aarch64/reloc-dtprel_g1.s: Likewise. * gas/aarch64/reloc-dtprel_g1-ilp32.s: Likewise. * gas/aarch64/reloc-dtprel_g1_nc.s: Likewise. * gas/aarch64/reloc-dtprel_g2.s: Likewise. * gas/aarch64/reloc-dtprel_hi12.s: Likewise. * gas/aarch64/reloc-dtprel_hi12-ilp32.s: Likewise. * gas/aarch64/reloc-dtprel_g0.d: New expectation file. * gas/aarch64/reloc-dtprel_g0-ilp32.d: Likewise. * gas/aarch64/reloc-dtprel_g0_nc.d: Likewise. * gas/aarch64/reloc-dtprel_g0_nc-ilp32.d: Likewise. * gas/aarch64/reloc-dtprel_g1.d: Likewise. * gas/aarch64/reloc-dtprel_g1-ilp32.d: Likewise. * gas/aarch64/reloc-dtprel_g1_nc.d: Likewise. * gas/aarch64/reloc-dtprel_g2.d: Likewise. * gas/aarch64/reloc-dtprel_hi12.d: Likewise. * gas/aarch64/reloc-dtprel_hi12-ilp32.d: Likewise.
2015-08-19[AArch64][1/6] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NCJiong Wang1-0/+11
2015-08-19 Jiong Wang <jiong.wang@arm.com> bfd/ * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC): New entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC. gas/ * config/tc-aarch64.c (reloc_table): New relocation modifiers. (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC. (aarch64_force_relocation): Likewise. gas/testsuite/ * gas/aarch64/reloc-dtprel_lo12_nc.s: New testcase. * gas/aarch64/reloc-dtprel_lo12_nc-ilp32.s: Likewise. * gas/aarch64/reloc-dtprel_lo12_nc.d: New expectation file. * gas/aarch64/reloc-dtprel_lo12_nc-ilp32.d: Likewise.
2015-08-17Rationalize ARM .alignAlan Modra2-48/+2
* gas/config/tc-arm.c (s_align): Delete. (md_pseudo_table): Use s_align_ptwo for "align". * gas/config/tc-arm.h (TC_ALIGN_ZERO_IS_DEFAULT): Define. * read.c (s_align): Modify for TC_ALIGN_ZERO_IS_DEFAULT.
2015-08-12xtensa: add --auto-litpools optionMax Filippov2-5/+428
Auto-litpools is the automated version of text-section-literals: literal pool candidate frags are planted every N frags and during relaxation they are turned into actual literal pools where literals are moved to become reachable for their first reference by L32R instruction. 2015-08-12 David Weatherford <weath@cadence.com> gas/ * config/tc-xtensa.c (struct litpool_frag, struct litpool_seg): New structures. (xtensa_maybe_create_literal_pool_frag): New function. (litpool_seg_list, auto_litpools, auto_litpool_limit) (litpool_buf, litpool_slotbuf): New static variables. (option_auto_litpools, option_no_auto_litpools) (option_auto_litpool_limit): New enum identifiers. (md_longopts): Add entries for auto-litpools, no-auto-litpools and auto-litpool-limit. (md_parse_option): Handle option_auto_litpools, option_no_auto_litpools and option_auto_litpool_limit. (md_show_usage): Add help for --[no-]auto-litpools and --auto-litpool-limit. (xtensa_mark_literal_pool_location): Record a place for literal pool with a call to xtensa_maybe_create_literal_pool_frag. (get_literal_pool_location): Find highest priority literal pool or convert candidate to literal pool when auto-litpools are used. (xg_assemble_vliw_tokens): Create literal pool after jump instruction. (xtensa_check_frag_count): Create candidate literal pool every auto_litpool_limit frags. (xtensa_relax_frag): Add jump around literals to non-empty literal pool. (xtensa_move_literals): Estimate literal pool addresses and move unreachable literals closer to their users, converting candidate to literal pool if needed. (xtensa_switch_to_non_abs_literal_fragment): Only emit error about missing .literal_position in case auto-litpools are not used. * config/tc-xtensa.h (xtensa_relax_statesE): New relaxation state: RELAX_LITERAL_POOL_CANDIDATE_BEGIN. * doc/as.texinfo (Xtensa options): Document --auto-litpools and --no-auto-litpools options. * doc/c-xtensa.texi (Xtensa options): Likewise. 2015-08-12 Max Filippov <jcmvbkbc@gmail.com> gas/testsuite/ * gas/xtensa/all.exp: Add auto-litpools to the list of xtensa tests. * gas/xtensa/auto-litpools.s: New file: auto-litpools test. * gas/xtensa/auto-litpools.s: New file: auto-litpools test result pattern.
2015-08-12[MIPS] Map 'move' to 'or'.Simon Dardis1-8/+6
The MIPS assembly idiom 'move' now maps to the 'or' machine instruction. This change affects microMIPS, MIPS32, MIPS64. 2015-08-12 Simon Dardis <simon.dardis@imgtec.com> opcodes/ * micromips-opc.c (micromips_opcodes): Re-order table so that move based on 'or' is first. * mips-opc.c (mips_builtin_opcodes): Ditto. bfd/ * elfxx-mips.c (STUB_MOVE): Change to use 'or' only. (mips_o32_exec_plt0_entry, mips_n32_exec_plt0_entry, mips_n64_exec_plt0_entry, micromips_insn32_o32_exec_plt0_entry): Update to use 'or' instead of 'addu/daddu'. (_bfd_mips_elf_finish_dynamic_symbol): Update usage of STUB_MOVE. (move_insns_32): Reorder table. gas/ * config/tc-mips.c (move_register): Change to use 'or' only. (s_cpload, s_cpsetup, s_cprestore, s_cpreturn): Update to use or for move. gas/testsuite/ * gas/mips/elf-rel23.d: Update test. * gas/mips/elf-rel23.d: Ditto. * gas/mips/elf-rel23a.d: Ditto. * gas/mips/elf-rel23b.d: Ditto. * gas/mips/elf_e_flags1.d: Ditto. * gas/mips/elf_e_flags2.d: Ditto. * gas/mips/elf_e_flags3.d: Ditto. * gas/mips/elf_e_flags4.d: Ditto. * gas/mips/loc-swap-dis.d: Ditto. * gas/mips/micromips-insn32.d: Ditto. * gas/mips/micromips-noinsn32.d: Ditto. * gas/mips/micromips-trap.d: Ditto. * gas/mips/micromips.d: Ditto. * gas/mips/mips-abi32-pic.d: Ditto. * gas/mips/mips-abi32.d: Ditto. * gas/mips/mips-gp32-fp32-pic.d: Ditto. * gas/mips/mips-gp32-fp32.d: Ditto. * gas/mips/mips-gp32-fp64-pic.d: Ditto. * gas/mips/mips-gp32-fp64.d: Ditto. * gas/mips/mips-gp64-fp32-pic.d: Ditto. * gas/mips/mips-gp64-fp32.d: Ditto. * gas/mips/mips-gp64-fp64-pic.d: Ditto. * gas/mips/mips-gp64-fp64.d: Ditto. * gas/mips/mipsr6@loc-swap-dis.d: Ditto. * gas/mips/tls-o32.d: Ditto. * gas/mips/uld2-eb.d: Ditto. * gas/mips/uld2-el.d: Ditto. * gas/mips/ulw2-eb-ilocks.d: Ditto. * gas/mips/ulw2-eb.d: Ditto. * gas/mips/ulw2-el-ilocks.d: Ditto. * gas/mips/ulw2-el.d: Ditto. * gas/mips/move.d: New test. * gas/mips/move.s: Ditto. * gas/mips/micromips32-move.d: Ditto. * gas/mips/micromips32-move.s: Ditto. * gas/mips/mips.exp: Run the new tests. gold/ * mips.cc (plt0_entry_o32, plt0_entry_n32, plt0_entry_n64, lazy_stub_normal_1, lazy_stub_normal_1_n64, lazy_stub_normal_2, lazy_stub_normal_2_n64, lazy_stub_big, lazy_stub_big_n64, lazy_stub_micromips32_normal_1_n64, lazy_stub_micromips32_normal_2_n64, lazy_stub_micromips32_big, lazy_stub_micromips32_big_n64): Update to use 'or' for move instead of 'addu/daddu'. ld/testsuite/ * ld-mips-elf/compressed-plt-1-n32-mips16.od: Update test. * ld-mips-elf/compressed-plt-1-n32-umips.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16-got.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16-only.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16-word.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-se.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-umips-got.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-umips-word.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-umips.od: Ditto. * ld-mips-elf/jalx-2.dd: Ditto. * ld-mips-elf/mips16-pic-3.dd: Ditto. * ld-mips-elf/pic-and-nonpic-3a.dd: Ditto. * ld-mips-elf/pic-and-nonpic-3b.dd: Ditto. * ld-mips-elf/pic-and-nonpic-5b.dd: Ditto. * ld-mips-elf/pic-and-nonpic-6-n32.dd: Ditto. * ld-mips-elf/pic-and-nonpic-6-o32.dd: Ditto. * ld-mips-elf/stub-dynsym-1-10000.d: Ditto. * ld-mips-elf/stub-dynsym-1-2fe80.d: Ditto. * ld-mips-elf/stub-dynsym-1-7fff.d: Ditto. * ld-mips-elf/stub-dynsym-1-8000.d: Ditto. * ld-mips-elf/stub-dynsym-1-fff0.d: Ditto. * ld-mips-elf/tlsbin-o32.d: Ditto. * ld-mips-elf/tlsdyn-o32-1.d: Ditto. * ld-mips-elf/tlsdyn-o32-2.d: Ditto. * ld-mips-elf/tlsdyn-o32-3.d: Ditto. * ld-mips-elf/tlsdyn-o32.d: Ditto. * ld-mips-elf/tlslib-o32.d: Ditto.
2015-08-12Remove trailing spaces in gasH.J. Lu69-740/+740
2015-08-11[AArch64][7/8] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12Jiong Wang1-0/+11
2015-08-11 Jiong Wang <jiong.wang@arm.com> include/elf/ * aarch64.h (R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12): Define. bfd/ * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12): New entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12. gas/ * config/tc-aarch64.c (reloc_table): New relocation modifiers "dtprel_lo12". (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12. (aarch64_force_relocation): Likewise. gas/testsuite/ * gas/aarch64/reloc-dtprel_lo12-1.s: New testcase. * gas/aarch64/reloc-dtprel_lo12-ilp32-1.s: Likewise. * gas/aarch64/reloc-dtprel_lo12-1.d: New expectation file. * gas/aarch64/reloc-dtprel_lo12-ilp32-1.d: Likewise.
2015-08-11[AArch64][5/8] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NCJiong Wang1-0/+11
2015-08-11 Jiong Wang <jiong.wang@arm.com> bfd/ * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC): New entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC. gas/ * config/tc-aarch64.c (reloc_table): New relocation modifiers. (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC. (aarch64_force_relocation): Likewise. gas/testsuite/ * gas/aarch64/reloc-tlsldm_lo12_nc-1.s: New testcase. * gas/aarch64/reloc-tlsldm_lo12_nc-ilp32-1.s: Likewise. * gas/aarch64/reloc-tlsldm_lo12_nc-1.d: New expectation file. * gas/aarch64/reloc-tlsldm_lo12_nc-ilp32-1.d: Likewise.
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