rocket-tools/fsf-binutils-gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-07-06	Fix spelling mistakes in some of the binutils sub-directories.	Nick Clifton	1	-1/+1
2020-06-30	RISC-V: Support debug and float CSR as the unprivileged ones.	Nelson Chu	1	-29/+24
2020-06-23	RISC-V: Generate ELF priv attributes if priv instruction are explicited used.	Nelson Chu	1	-6/+42
2020-06-22	RISC-V: Report warning when linking the objects with different priv specs.	Nelson Chu	1	-27/+9
2020-06-05	RISC-V: Don't generate the ELF privilege attributes when no CSR are used.	Nelson Chu	1	-0/+9
2020-05-27	RISC-V: Fix missing initialization of riscv_csr_extra structs	Simon Cook	1	-0/+1
2020-05-24	RISC-V: Gas inserts cfa relocs in wrong section.	Jim Wilson	1	-1/+12
2020-05-20	[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...	Nelson Chu	1	-89/+425
2020-03-04	RISC-V: Support assembler modifier %got_pcrel_hi.	Nelson Chu	1	-0/+1
2020-02-26	Indent labels	Alan Modra	1	-9/+9
2020-02-20	RISC-V: Support the read-only CSR checking.	Nelson Chu	1	-0/+69
2020-02-20	RISC-V: Disable the CSR checking by default.	Nelson Chu	1	-1/+21
2020-02-20	RISC-V: Support the ISA-dependent CSR checking.	Nelson Chu	1	-7/+92
2020-01-01	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2019-12-12	gas signed overflow fixes	Alan Modra	1	-2/+2
2019-11-28	gas/riscv: Produce version 3 DWARF CIE by default	Andrew Burgess	1	-0/+6
2019-11-28	binutils/gas/riscv: Add DWARF register numbers for CSRs	Andrew Burgess	1	-0/+4
2019-11-28	gas/riscv: Remove unneeded structure	Andrew Burgess	1	-7/+1
2019-09-17	RISC-V: Gate opcode tables by enum rather than string.	Jim Wilson	1	-7/+20
2019-08-25	RISC-V: Improve li expansion for better code density.	Kito Cheng	1	-5/+33
2019-05-30	RISC-V: Fix lui argument parsing.	Jim Wilson	1	-5/+4
2019-02-08	RISC-V: Compress 3-operand beq/bne against x0.	Jim Wilson	1	-0/+6
2019-01-16	RISC-V: Support ELF attribute for gas and readelf.	Jim Wilson	1	-0/+127
2019-01-01	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2018-12-10	RISC-V: Don't segfault for two regs in auipc or lui.	Jim Wilson	1	-1/+8
2018-12-07	RISC-V: Fix 4-arg add parsing.	Jim Wilson	1	-3/+12
2018-12-03	RISC-V: Accept version, supervisor ext and more than one NSE for -march.	Jim Wilson	1	-140/+23
2018-11-27	RISC-V: Add .insn CA support.	Jim Wilson	1	-0/+31
2018-10-29	Move struc-symbol.h to symbols.c	Alan Modra	1	-6/+4
2018-08-30	RISC-V: Allow instruction require more than one extension	Jim Wilson	1	-11/+21
2018-08-23	RISC-V: Reject empty rouding mode and fence operand.	Jim Wilson	1	-0/+3
2018-06-29	RISC-V: Add gas support for "fp" register.	Jim Wilson	1	-0/+3
2018-06-20	RISC-V: Accept constant operands in la and lla	Sebastian Huber	1	-0/+11
2018-05-24	RISC-V: Fix .align handling when .option norelax.	Jim Wilson	1	-9/+21
2018-05-18	RISC-V: Add RV32E support.	Jim Wilson	1	-10/+56
2018-04-20	RISC-V: Add new option -mrelax/-mno-relax.	Jim Wilson	1	-0/+14
2018-03-16	RISC-V: Emit better warning for unknown CSR.	Jim Wilson	1	-6/+11
2018-03-14	RISC-V: Add .insn support.	Jim Wilson	1	-27/+413
2018-02-05	RISC-V/GAS: Correct an `expr' global shadowing error for pre-4.8 GCC	Maciej W. Rozycki	1	-3/+3
2018-01-17	RISC-V: Fix bug in prior addi/c.nop patch.	Jim Wilson	1	-0/+10
2018-01-03	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2017-12-20	RISC-V: Add compressed instruction hints, and a few misc cleanups.	Jim Wilson	1	-0/+3
2017-11-29	Fix riscv malloc error on small alignment after norvc.	Jim Wilson	1	-2/+10
2017-11-27	Compress loads/stores with implicit 0 offset.	Jim Wilson	1	-6/+32
2017-11-07	RISC-V: Fix riscv g++ testsuite EH failures.	Jim Wilson	1	-0/+15
2017-11-07	RISC-V: Add satp as an alias for sptbr	Palmer Dabbelt	1	-0/+1
2017-10-23	RISC-V: Don't emit 2-byte NOPs if the C extension is disabled	Palmer Dabbelt	1	-1/+1
2017-10-19	RISC-V: Relax RISCV_PCREL_* to RISCV_GPREL_*	Palmer Dabbelt	1	-1/+4
2017-09-07	RISC-V: Avoid emitting invalid instructions in mixed RVC/no-RVC code	Palmer Dabbelt	1	-17/+8
2017-07-28	Fix problems parsing RISCV architecture extenstions in the assembler.	Andrew Waterman	1	-11/+7