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2013-03-07Rewrote i386_index_checkH.J. Lu1-121/+106
* config/tc-i386.c (flag_code_names): Removed. (i386_index_check): Rewrote.
2013-02-28Replace have_hle with hle_prefixH.J. Lu1-14/+7
* config/tc-i386.c (_i386_insn): Replace have_hle with hle_prefix. (check_hle): Updated. (md_assemble): Likewise. (parse_insn): Likewise.
2013-02-28Optimize REP prefix checkH.J. Lu1-25/+12
gas/ * config/tc-i386.c (_i386_insn): Add rep_prefix. (md_assemble): Check if REP prefix is OK. (parse_insn): Remove expecting_string_instruction. Set i.rep_prefix. gas/testsuite/ * gas/i386/i386.exp: Run inval-rep and x86-64-inval-rep. * gas/i386/inval-rep.l: New file. * gas/i386/inval-rep.s: Likewise. * gas/i386/x86-64-inval-rep.l: Likewise. * gas/i386/x86-64-inval-rep.s: Likewise.
2013-02-19Implement Intel SMAP instructionsH.J. Lu1-0/+2
gas/ PR gas/15159 * config/tc-i386.c (cpu_arch): Add ".smap". * doc/c-i386.texi: Document smap. gas/testsuite/ PR gas/15159 * gas/i386/i386.exp: Run smap and x86-64-smap. * gas/i386/smap.d: New file. * gas/i386/smap.s: likewise. * gas/i386/x86-64-smap.d: likewise. opcodes/ PR gas/15159 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1. * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS. (cpu_flags): Add CpuSMAP. * i386-opc.h (CpuSMAP): New. (i386_cpu_flags): Add cpusmap. * i386-opc.tbl: Add clac and stac. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2013-01-18Support size relocation only for ELFH.J. Lu1-0/+6
* config/tc-i386.c (reloc): Support size relocation only for ELF. (tc_i386_fix_adjustable): Likewise. (lex_got): Likewise. (tc_gen_reloc): Likewise.
2013-01-17Add x86 size relocation support to gasH.J. Lu1-3/+35
gas/ * config/tc-i386.c (reloc): Support BFD_RELOC_SIZE32. (tc_i386_fix_adjustable): Keep symbol for BFD_RELOC_32_SIZE and BFD_RELOC_64_SIZE relocations. (lex_got): Support "symbol@SIZE" and don't create GOT symbol for it. (tc_gen_reloc): Resolve BFD_RELOC_SIZE32 and BFD_RELOC_SIZE64 relocations against local symbols. gas/testsuite/ * gas/i386/i386.exp: Run size-1, size-2, size-3, size-4, x86-64-size-1, x86-64-size-2, x86-64-size-3, x86-64-size-4, x86-64-size-5 and x86-64-size-inval-1. * gas/i386/size-1.d: New file. * gas/i386/size-1.s: Likewise. * gas/i386/size-2.d: Likewise. * gas/i386/size-2.s: Likewise. * gas/i386/size-3.d: Likewise. * gas/i386/size-3.s: Likewise. * gas/i386/size-4.d: Likewise. * gas/i386/size-4.s: Likewise. * gas/i386/x86-64-size-1.d: Likewise. * gas/i386/x86-64-size-2.d: Likewise. * gas/i386/x86-64-size-3.d: Likewise. * gas/i386/x86-64-size-4.d: Likewise. * gas/i386/x86-64-size-5.d: Likewise. * gas/i386/x86-64-size-5.s: Likewise. * gas/i386/x86-64-size-inval-1.l: Likewise. * gas/i386/x86-64-size-inval-1.s: Likewise. * gas/i386/ilp32/x86-64-size-1.d: Likewise. * gas/i386/ilp32/x86-64-size-2.d: Likewise. * gas/i386/ilp32/x86-64-size-3.d: Likewise. * gas/i386/ilp32/x86-64-size-4.d: Likewise. * gas/i386/ilp32/x86-64-size-5.d: Likewise. ld/testsuite/ * ld-size/size.exp: New file. * ld-size/size32-1-i386.d: Likewise. * ld-size/size32-1-x32.d: Likewise. * ld-size/size32-1-x86-64.d: Likewise. * ld-size/size32-1.s: Likewise. * ld-size/size32-2-i386.d: Likewise. * ld-size/size32-2-x32.d: Likewise. * ld-size/size32-2-x86-64.d: Likewise. * ld-size/size32-2.s: Likewise. * ld-size/size64-1-x32.d: Likewise. * ld-size/size64-1-x86-64.d: Likewise. * ld-size/size64-1.s: Likewise. * ld-size/size64-2-x32.d: Likewise. * ld-size/size64-2-x86-64.d: Likewise. * ld-size/size64-2.s: Likewise. * ld-size/size-3.c: Likewise. * ld-size/size-3.out: Likewise. * ld-size/size-3a.c: Likewise. * ld-size/size-3b.c: Likewise. * ld-size/size-3c.c: Likewise. * ld-size/size-4.out: Likewise. * ld-size/size-4a.c: Likewise. * ld-size/size-4b.c: Likewise. * ld-size/size-5.out: Likewise. * ld-size/size-5a.c: Likewise. * ld-size/size-5b.c: Likewise. * ld-size/size-6.out: Likewise. * ld-size/size-6a.c: Likewise. * ld-size/size-6b.c: Likewise. * ld-size/size-7.rd: Likewise. * ld-size/size-7a.c: Likewise. * ld-size/size-7b.c: Likewise. * ld-size/size-8.rd: Likewise. * ld-size/size-8a.c: Likewise. * ld-size/size-8b.c: Likewise.
2013-01-15Increment length by 1 if the relocation token is removedH.J. Lu1-2/+6
gas/ PR gas/15019 * config/tc-i386.c (lex_got): Increment length by 1 if the relocation token is removed. gas/testsuite/ PR gas/15019 * gas/i386/reloc32.s: Add tests for "xtrn@got -/+ 4". * gas/i386/reloc64.s: Likewise. * gas/i386/ilp32/reloc64.s: Likewise. * gas/i386/reloc32.d: Updated. * gas/i386/reloc64.d: Likewise. * gas/i386/ilp32/reloc64.d: Likewise.
2013-01-10Remove trailing white spaces on gasH.J. Lu1-2/+2
* app.c: Remove trailing white spaces. * as.c: Likewise. * as.h: Likewise. * cond.c: Likewise. * dw2gencfi.c: Likewise. * dwarf2dbg.h: Likewise. * ecoff.c: Likewise. * input-file.c: Likewise. * itbl-lex.h: Likewise. * output-file.c: Likewise. * read.c: Likewise. * sb.c: Likewise. * subsegs.c: Likewise. * symbols.c: Likewise. * write.c: Likewise. * config/tc-i386.c: Likewise. * doc/Makefile.am: Likewise. * doc/Makefile.in: Likewise. * doc/c-aarch64.texi: Likewise. * doc/c-alpha.texi: Likewise. * doc/c-arc.texi: Likewise. * doc/c-arm.texi: Likewise. * doc/c-avr.texi: Likewise. * doc/c-bfin.texi: Likewise. * doc/c-cr16.texi: Likewise. * doc/c-d10v.texi: Likewise. * doc/c-d30v.texi: Likewise. * doc/c-h8300.texi: Likewise. * doc/c-hppa.texi: Likewise. * doc/c-i370.texi: Likewise. * doc/c-i386.texi: Likewise. * doc/c-i860.texi: Likewise. * doc/c-m32c.texi: Likewise. * doc/c-m32r.texi: Likewise. * doc/c-m68hc11.texi: Likewise. * doc/c-m68k.texi: Likewise. * doc/c-microblaze.texi: Likewise. * doc/c-mips.texi: Likewise. * doc/c-msp430.texi: Likewise. * doc/c-mt.texi: Likewise. * doc/c-s390.texi: Likewise. * doc/c-score.texi: Likewise. * doc/c-sh.texi: Likewise. * doc/c-sh64.texi: Likewise. * doc/c-tic54x.texi: Likewise. * doc/c-tic6x.texi: Likewise. * doc/c-v850.texi: Likewise. * doc/c-xc16x.texi: Likewise. * doc/c-xgate.texi: Likewise. * doc/c-xtensa.texi: Likewise. * doc/c-z80.texi: Likewise. * doc/internals.texi: Likewise.
2013-01-092013-01-09 Steve Ellcey <sellcey@mips.com>Steve Ellcey1-2/+2
* config/tc-i386.c (md_begin): Remove 'internal Error' from as_fatal calls. * config/tc-mips.c (internalError): Remove, replace with abort.
2012-10-09Add AMD bdver3 support.Nagajyothi Eggone1-0/+2
gas/ * config/tc-i386.c (cpu_arch): Add CPU_BDVER3_FLAGS. * doc/c-i386.texi: Add -march=bdver3 option. gas/testsuite/ * gas/i386/i386.exp: Run bdver3 test cases. * gas/i386/nops-1-bdver3.d: New. * gas/i386/arch-10-bdver3.d: New. * gas/i386/x86-64-nops-1-bdver3.d: New. * gas/i386/x86-64-arch-2-bdver3.d: New. opcodes/ * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS. * i386-init.h: Regenerated.
2012-09-20Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu1-0/+2
gas/ * config/tc-i386.c (cpu_arch): Add .cx16. * doc/c-i386.texi: Document .cx16. gas/testsuite/ * gas/i386/x86-64-arch-2.s: Add test for cmpxchg16b. * gas/i386/x86-64-arch-2.d: Update correspondingly. * gas/i386/x86-64-arch-2-bdver2.d: Likewise. * gas/i386/x86-64-arch-2-btver1.d: Likewise. * gas/i386/x86-64-arch-2-btver2.d: Likewise. * gas/i386/x86-64-arch-2-lzcnt.d: Likewise. * gas/i386/x86-64-arch-2-prefetchw.d: Likewise. * gas/i386/ilp32/x86-64-arch-2.d: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS, CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS, CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS, CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS. (cpu_flags): Add CpuCX16. * i386-opc.h (CpuCX16): New. (i386_cpu_flags): Add cpucx16. * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b. * i386-tbl.h: Regenerate. * i386-init.h: Likewise.
2012-08-17Add AMD btver1 and btver2 supportH.J. Lu1-1/+7
gas/ 2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com> * config/tc-i386.c (cpu_arch): Add CPU_BTVER1_FLAGS and CPU_BTVER2_FLAGS. (i386_align_code): Add case for PROCESSOR_BT. * config/tc-i386.h (enum processor_type): Add PROCESSOR_BT. * doc/c-i386.texi: Add -march={btver1, btver2} options. gas/testsuite/ 2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com> * gas/i386/i386.exp: Run btver1 and btver2 test cases. * gas/i386/nops-1-btver1.d: New. * gas/i386/nops-1-btver2.d: New. * gas/i386/arch-10-btver1.d: New. * gas/i386/arch-10-btver2.d: New. * gas/i386/x86-64-nops-1-btver1.d: New. * gas/i386/x86-64-nops-1-btver2.d: New. * gas/i386/x86-64-arch-2-btver1.d: New. * gas/i386/x86-64-arch-2-btver2.d: New. opcodes/ 2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com> * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and CPU_BTVER2_FLAGS. * i386-opc.h: Update CpuPRFCHW comment. * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2012-08-14Terminate register name when reporting bad registerH.J. Lu1-0/+6
gas/ PR gas/14457 * config/tc-i386.c (i386_att_operand): Terminate register name when reporting bad register. gas/testsuite/ PR gas/14457 * gas/i386/i386.exp: Run reg-bad. * gas/i386/reg-bad.l: New. * gas/i386/reg-bad.s: Likewise.
2012-08-07Despite them being ignored by the CPU, gas issues segment overrideJan Beulich1-10/+6
prefixes for other than FS/GS in 64-bit mode. If doing so at all, it should clearly do this correctly. Determining the default segment, however, requires to take into consideration RegRex (so far, RSP, RBP, R12, and R13 were all treated equally here). gas/ 2012-08-07 Jan Beulich <jbeulich@suse.com> * config/tc-i386-intel.c (build_modrm_byte): Split determining default segment from figuring out encoding. Honor RegRex for the former. gas/testsuite/ 2012-08-07 Jan Beulich <jbeulich@suse.com> * gas/i386/x86-64-segovr.{s,l}: New. * gas/i386/i386.exp: Run new test.
2012-08-07The VGATHER group of instructions requires that all three involvedJan Beulich1-29/+84
xmm/ymm registers are distinct. This patch adds code to check for this, and at once eliminates a superfluous check for not using PC-relative addressing for these instructions (the fact that an index register is required here already excludes valid PC-relative addresses). The severity of the resulting diagnostics can be controlled via command line option or directive. gas/ 2012-08-07 Jan Beulich <jbeulich@suse.com> * config/tc-i386.c (set_check): Renamed from set_sse_check. Generalize to also handle operand checking option. (enum i386_error): New enumerator 'invalid_vector_register_set'. (match_template): Handle it. (enum check_kind): Give it a tag. Drop sse_ prefixes from enumerators. (operand_check): New. (md_pseudo_table): Add "operand_check". (check_VecOperands): Don't special case RIP addressing. Check that vSIB operands use distinct vector registers unless no checking was requested. (OPTION_MOPERAND_CHECK): New. (md_parse_option): Handle it. (OPTION_MAVXSCALAR, OPTION_X32): Adjust. (md_longopts): Add "moperand-check". (md_show_usage): Add help text for it. gas/testsuite/ 2012-08-07 Jan Beulich <jbeulich@suse.com> * gas/i386/vgather-check-error.{s,l}: New. * gas/i386/vgather-check-none.{s,d}: New. * gas/i386/vgather-check-warn.{d,e}: New. * gas/i386/vgather-check.{s,d}: New. * gas/i386/x86-64-vgather-check-error.{s,l}: New. * gas/i386/x86-64-vgather-check-none.{s,d}: New. * gas/i386/x86-64-vgather-check-warn.{d,e}: New. * gas/i386/x86-64-vgather-check.{s,d}: New. * gas/i386/i386.exp: Run new tests.
2012-08-07There were several cases where the registers in the REX encoded rangeJan Beulich1-23/+25
got treated identically to the ones in the base range, due to not paying attention to the fact that reg_entry's reg_num field doesn't fully specify the register number (reg_flags also needs to be checked for RegRex). This patch introduces and uses a new (inline) function to obtain the full register number, and uses it to fix all those cases. It additionally adds the missing operand checks for SVME instructions (which match the monitor/mwait ones). gas/ 2012-08-07 Jan Beulich <jbeulich@suse.com> * config/tc-i386.c (register_number): New function. (build_vex_prefix, process_immext, process_operands, build_modrm_byte, i386_index_check): Use it. gas/testsuite/ 2012-08-07 Jan Beulich <jbeulich@suse.com> * gas/i386/x86-64-specific-reg.{s,l}: New. * gas/i386/i386.exp: Run new test. opcodes/ 2012-08-07 Jan Beulich <jbeulich@suse.com> * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
2012-08-07 * config/tc-i386.c (lex_got): Provide implementation for PENick Clifton1-0/+103
format. * gas/i386/secrel.s: Add test of <symbol>@SECREL32. * gas/i386/secrel.d: Add expected disassembly. * scripttempl/pe.sc (R_TLS): Add .tls$AAA and .tls$ZZZ. * scripttempl/pep.sc (R_TLS): Add .tls$AAA and .tls$ZZZ. * archive.c (_bfd_delete_archive_data): New function. * libbfd-in.h (_bfd_delete_archive_data): Declare. * libbfd.h: Rebuild. * opncls.c (_bfd_delete_bfd): Call _bfd_delete_archive_data.
2012-07-31The current error message for bad imm4 operands wasn't really helpful,Jan Beulich1-1/+1
and was pointing at the wrong operand in Intel mode. Since non-constant operands are being taken care of by other means anyway, adjust it to simply state that the constant doesn't fit. 2012-07-31 Jan Beulich <jbeulich@suse.com> * config/tc-i386.c (match_template): Adjust error message for 'bad_imm4' case.
2012-07-31Since the word to byte register conversion isn't active for x86-64Jan Beulich1-13/+9
anyway, there's also no need to issue a separate, inconsistent diagnostic in some of the cases - non-matching operands will be complained about anyway. 2012-07-31 Jan Beulich <jbeulich@suse.com> * config/tc-i386.c (check_byte_reg): Check for I/O port register earlier, and just once. Drop diagnostic that got issued only for some registers.
2012-07-31At the point where check_VecOperands()/VEX_check_operands() get run,Jan Beulich1-8/+8
all other instruction attributes already matched, so any mismatch here will tell the user more precisely what is wrong than using an eventual (and very likely to occur) more generic error encountered on a subsequent iteration through the template matching loop. 2012-07-31 Jan Beulich <jbeulich@suse.com> * config/tc-i386.c (match_template): New local variable 'specific_error'. Set it from i.error after failed check_VecOperands or VEX_check_operands. Use it if set in preference to i.error when actually issuing disagnostic.
2012-07-16Implement RDRSEED, ADX and PRFCHW instructionsH.J. Lu1-0/+6
gas/ * config/tc-i386.c: Add ADX, RDSEED and PRFCHW asm directives. * doc/c-i386.texi: Document the new directives. gas/testsuite/ * gas/i386/i386.exp: Run adx, rdseed and prefetchw tests. * gas/i386/x86-64-arch-2.s: Use prefetchw as 3dnow and Prfchw tests. * gas/i386/arch-10.s: Likewise. * gas/i386/arch-10-1.l: Changed correspondingly. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10.d: Likewise. * gas/i386/arch-10-lzcnt.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-arch-2-lzcnt.d: Likewise. * gas/i386/ilp32/x86-64-arch-2.d: Likewise. * gas/i386/arch-10-prefetchw.d: New file. * gas/i386/x86-64-arch-2-prefetchw.d: Likewise. * gas/i386/rdseed.s: Likewise. * gas/i386/rdseed.d: Likewise. * gas/i386/rdseed-intel.d: Likewise. * gas/i386/adx.s: Likewise. * gas/i386/adx.d: Likewise. * gas/i386/adx-intel.d: Likewise. * gas/i386/x86-64-rdseed.s: Likewise. * gas/i386/x86-64-rdseed.d: Likewise. * gas/i386/x86-64-rdseed-intel.d: Likewise. * gas/i386/x86-64-adx.s: Likewise. * gas/i386/x86-64-adx.d: Likewise. * gas/i386/x86-64-adx-intel.d: Likewise. opcodes/ * i386-dis.c (PREFIX_0F38F6): New. (prefix_table): Add adcx, adox instructions. (three_byte_table): Use PREFIX_0F38F6. (mod_table): Add rdseed instruction. * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW. (cpu_flags): Likewise. * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW. (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw. * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend prefetchw. * i386-tbl.h: Regenerate. * i386-init.h: Likewise.
2012-06-22gas/Roland McGrath1-3/+3
* config/tc-i386.c (parse_insn): Don't complain about REP prefix when the template has opcode_modifier.repprefixok set. * NEWS: Mention the change. gas/testsuite/ * gas/i386/rep-bsf.d: New file. * gas/i386/rep-bsf.s: New file. * gas/i386/i386.exp: Add the new test. opcodes/ * i386-opc.h (RepPrefixOk): New enum constant. (i386_opcode_modifier): New bitfield 'repprefixok'. * i386-gen.c (opcode_modifiers): Add RepPrefixOk. * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all instructions that have IsString. * i386-tbl.h: Regenerate.
2012-06-13Fix .dc.a for x32H.J. Lu1-0/+11
gas/ * config/tc-i386.c (x86_address_bytes): New. * config/tc-i386.h (TC_ADDRESS_BYTES): Likewise. (x86_address_bytes): Likewise. gas/testsuite/ * gas/i386/ilp32/x86-64-dc_a.d: New. * gas/i386/ilp32/x86-64-dc_a.s: Likewise.
2012-05-12Remove x32 addend overflow for BFD_RELOC_64H.J. Lu1-19/+0
gas/ * config/tc-i386.c (tc_gen_reloc): Remove x32 addend overflow for BFD_RELOC_64. gas/testsuite/ * gas/i386/ilp32/ilp32.exp: Don't run reloc64-inval. * gas/i386/ilp32/reloc64.s: Add test for -4294967295 addend. * gas/i386/ilp32/reloc64.d: Updated. * gas/i386/ilp32/reloc64-inval.l: Removed. * gas/i386/ilp32/reloc64-inval.s: Likewise.
2012-05-11Use int and bfd_signed_vma in x32 addend overflow checkH.J. Lu1-3/+5
bfd/ * elf64-x86-64.c (elf_x86_64_relocate_section): Use int in x32 addend overflow check. gas/ * config/tc-i386.c (tc_gen_reloc): Use bfd_signed_vma in x32 addend overflow check.
2012-05-10Display signed hex number in x32 addend overflow checkH.J. Lu1-4/+11
bfd/ * elf64-x86-64.c (elf_x86_64_relocate_section): Display signed hex number in x32 addend overflow check. gas/ * config/tc-i386.c (tc_gen_reloc): Display signed hex number in x32 addend overflow check. ld/testsuite/ * ld-x86-64/ilp32-11.d: Updated.
2012-05-10Use fits_in_signed_long to check x32 addend overflowH.J. Lu1-2/+1
* config/tc-i386.c (tc_gen_reloc): Use fits_in_signed_long.
2012-05-10Check 64-bit relocation addend overflow for x32H.J. Lu1-0/+11
bfd/ * elf64-x86-64.c (elf_x86_64_relocate_section): Check addend overflow for R_X86_64_RELATIVE64. gas/ * config/tc-i386.c (tc_gen_reloc): Check x32 addend overflow for BFD_RELOC_64. gas/testsuite/ * gas/i386/ilp32/ilp32.exp: Run reloc64-inval. * gas/i386/ilp32/reloc64.s: Add tests for ".quad". * gas/i386/ilp32/reloc64.d: Updated. * gas/i386/ilp32/reloc64-inval.l: New file. * gas/i386/ilp32/reloc64-inval.s: Likewise. ld/testsuite/ * ld-x86-64/ilp32-11.d: New file. * ld-x86-64/ilp32-11.s: Likewise. * ld-x86-64/x86-64.exp: Run ilp32-11.
2012-05-04Add `instruction' to unsupported error messageH.J. Lu1-1/+1
* config/tc-i386.c (match_template): Add `instruction' to unsupported error message.
2012-05-04Reformat output_insnH.J. Lu1-1/+1
* config/tc-i386.c (output_insn): Reformat.
2012-05-04Remove the extra VEX checkH.J. Lu1-2/+1
* config/tc-i386.c (output_insn): Remove the extra VEX check.
2012-05-04Improve unsupported error messageH.J. Lu1-2/+3
* config/tc-i386.c (match_template): Improve unsupported error message.
2012-03-13gas/Roland McGrath1-0/+12
2012-03-12 Roland McGrath <mcgrathr@google.com> * config/tc-arm.c (arm_frag_max_var): New function. * config/tc-arm.h: Declare it. (md_frag_max_var): New macro. * config/tc-i386.c (i386_frag_max_var): New function. * config/tc-i386.h: Declare it. (md_frag_max_var): New macro. * doc/as.texinfo (Bundle directives): New node. (Pseudo Ops): Add it to the menu. * NEWS: Mention new feature. * read.c [md_frag_max_var] (HANDLE_BUNDLE): New macro. [HANDLE_BUNDLE] (bundle_align_p2): New variable. [HANDLE_BUNDLE] (bundle_lock_frchain, bundle_lock_frag): New variables. [HANDLE_BUNDLE] (start_bundle, pending_bundle_size, finish_bundle): New functions. (assemble_one): New function if [HANDLE_BUNDLE], #define directly to md_assembly if not. (read_a_source_file): Call assemble_one in place of md_assemble. (read_a_source_file) [HANDLE_BUNDLE]: Check for unterminated .bundle_lock at end of processing. [HANDLE_BUNDLE] (s_bundle_align_mode, s_bundle_lock, s_bundle_unlock): New functions. [HANDLE_BUNDLE] (potable): Add their entries. * read.h: Declare new functions. gas/testsuite/ 2012-03-12 Roland McGrath <mcgrathr@google.com> * gas/i386/bundle-bad.s: New file. * gas/i386/bundle-bad.d: New file. * gas/i386/bundle-bad.l: New file. * gas/i386/i386.exp: Run it. * gas/arm/bundle.s: New file. * gas/arm/bundle.d: New file. * gas/arm/bundle-lock.s: New file. * gas/arm/bundle-lock.d: New file. * gas/i386/bundle.s: New file. * gas/i386/bundle.d: New file. * gas/i386/x86-64-bundle.s: New file. * gas/i386/x86-64-bundle.d: New file. * gas/i386/bundle-lock.s: New file. * gas/i386/bundle-lock.d: New file. * gas/i386/i386.exp: Run them.
2012-02-21Add HLEPrefixNone/HLEPrefixLock/HLEPrefixAny/HLEPrefixReleaseH.J. Lu1-4/+4
gas/ 2012-02-21 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (check_hle): Use HLEPrefixNone, HLEPrefixLock, HLEPrefixAny and HLEPrefixRelease. opcodes/ 2012-02-21 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (HLEPrefixNone): New. (HLEPrefixLock): Likewise. (HLEPrefixAny): Likewise. (HLEPrefixRelease): Likewise.
2012-02-08Implement Intel Transactional Synchronization ExtensionsH.J. Lu1-4/+72
gas/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (HLE_PREFIX): New. (check_hle): Likewise. (_i386_insn): Add have_hle. (cpu_arch): Add .hle and .rtm. (md_assemble): Call check_hle if i.have_hle isn't zero. (parse_insn): Set i.have_hle to 1 for HLE prefix. (output_jump): Support up to 2 byte opcode. * doc/c-i386.texi: Document hle/.hle and rtm/.rtm. gas/testsuite/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/hle-intel.d: New. * gas/i386/hle.d: Likewise. * gas/i386/hle.s: Likewise. * gas/i386/hlebad.l: Likewise. * gas/i386/hlebad.s: Likewise. * gas/i386/rtm-intel.d: Likewise. * gas/i386/rtm.d: Likewise. * gas/i386/rtm.s: Likewise. * gas/i386/x86-64-hle-intel.d: Likewise. * gas/i386/x86-64-hle.d: Likewise. * gas/i386/x86-64-hle.s: Likewise. * gas/i386/x86-64-hlebad.l: Likewise. * gas/i386/x86-64-hlebad.s: Likewise. * gas/i386/x86-64-rtm-intel.d: Likewise. * gas/i386/x86-64-rtm.d: Likewise. * gas/i386/x86-64-rtm.s: Likewise. * gas/i386/i386.exp: Run hle, hle-intel, hlebad x86-64-hle, rtm, rtm-intel, x86-64-hle-intel, x86-64-hlebad, x86-64-rtm and x86-64-rtm-intel. include/opcode/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * i386.h (XACQUIRE_PREFIX_OPCODE): New. (XRELEASE_PREFIX_OPCODE): Likewise. opcodes/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (HLE_Fixup1): New. (HLE_Fixup2): Likewise. (HLE_Fixup3): Likewise. (Ebh1): Likewise. (Evh1): Likewise. (Ebh2): Likewise. (Evh2): Likewise. (Ebh3): Likewise. (Evh3): Likewise. (MOD_C6_REG_7): Likewise. (MOD_C7_REG_7): Likewise. (RM_C6_REG_7): Likewise. (RM_C7_REG_7): Likewise. (XACQUIRE_PREFIX): Likewise. (XRELEASE_PREFIX): Likewise. (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov. (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg, not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use MOD_C6_REG_7 and MOD_C7_REG_7. (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7. (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and xtest. (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX. (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b. * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and CPU_RTM_FLAGS. (cpu_flags): Add CpuHLE and CpuRTM. (opcode_modifiers): Add HLEPrefixOk. * i386-opc.h (CpuHLE): New. (CpuRTM): Likewise. (HLEPrefixOk): Likewise. (i386_cpu_flags): Add cpuhle and cpurtm. (i386_opcode_modifier): Add hleprefixok. * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory operand. Add xacquire, xrelease, xabort, xbegin, xend and xtest. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2012-01-23* configure.tgt (i386-*-nacl*): Match it.Roland McGrath1-5/+6
* config/te-nacl.h: New file. * config/tc-i386.h [TE_NACL] (ELF_TARGET_FORMAT): Define for this case. * config/tc-i386.c [TE_NACL] (i386_comment_chars, PREFIX_SEPARATOR): Use TE_GNU et al case for TE_NACL too.
2012-01-20Add .d8 suffix support to x86 assemblerH.J. Lu1-6/+27
gas/ 2012-01-20 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (_i386_insn): Replace disp32_encoding with disp_encoding. (md_assemble): Updated. (output_branch): Likewise. (parse_insn): Support .d8 suffix. (build_modrm_byte): Fake zero displacement for .d8 and .d32 suffixes. * doc/c-i386.texi: Document .d8 suffix. gas/testsuite/ 2012-01-20 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/disp32.s: Add tests for .d8 suffix. * gas/i386/x86-64-disp32.s: Likewise. * gas/i386/disp32.d: Updated. * gas/i386/x86-64-disp32.d: Likewise.
2012-01-13Add vmfuncH.J. Lu1-0/+2
gas/ 2012-01-13 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add ".vmfunc". * doc/c-i386.texi: Document vmfunc. gas/testsuite/ 2012-01-13 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run vmfunc and x86-64-vmfunc. * gas/i386/vmfunc.d: New. * gas/i386/vmfunc.s: Likewise. * gas/i386/x86-64-vmfunc.d: Likewise. opcodes/ 2012-01-13 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (mod_table): Add vmfunc. * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS. (cpu_flags): CpuVMFUNC. * i386-opc.h (CpuVMFUNC): New. (i386_cpu_flags): Add cpuvmfunc. * i386-opc.tbl: Add vmfunc. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2012-01-062012-01-06 Tristan Gingold <gingold@adacore.com>Tristan Gingold1-6/+18
* config/tc-i386.c: Update copyright year. (lex_got): Also defined for Mach-O. Add a guard for non-ELF configuration. (md_longopts): Also handle -64 for Mach-O. (md_parse_option): Likewise. (i386_target_format): Adjust for x86_64-darwin.
2011-08-01Check R_X86_64_32 overflow and allow R_X86_64_64 for x32.H.J. Lu1-49/+10
bfd/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * archures.c (bfd_mach_i386_intel_syntax): New. (bfd_mach_i386_i8086): Updated. (bfd_mach_i386_i386): Likewise. (bfd_mach_x86_64): Likewise. (bfd_mach_x64_32): Likewise. (bfd_mach_i386_i386_intel_syntax): Likewise. (bfd_mach_x86_64_intel_syntax): Likewise. (bfd_mach_x64_32_intel_syntax): Likewise. (bfd_mach_l1om): Likewise. (bfd_mach_l1om_intel_syntax): Likewise. (bfd_mach_k1om): Likewise. (bfd_mach_k1om_intel_syntax): Likewise. * bfd-in2.h: Regenerated. * cpu-i386.c (bfd_i386_compatible): Check mach instead of bits_per_address. (bfd_x64_32_arch_intel_syntax): Set bits_per_address to 64. (bfd_x64_32_arch): Likewise. * elf64-x86-64.c: Include "libiberty.h". (x86_64_elf_howto_table): Append x32 R_X86_64_32. (elf_x86_64_rtype_to_howto): Support x32 R_X86_64_32. (elf_x86_64_reloc_type_lookup): Likewise. (elf_x86_64_reloc_name_lookup): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_check_relocs): Allow R_X86_64_64 relocations for x32. gas/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * config/tc-i386.c (handle_quad): Removed. (md_pseudo_table): Remove "quad". (tc_gen_reloc): Don't check BFD_RELOC_64 for disallow_64bit_reloc. (x86_dwarf2_addr_size): New. * config/tc-i386.h (x86_dwarf2_addr_size): New. (DWARF2_ADDR_SIZE): Likewise. gas/testsuite/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * gas/i386/ilp32/ilp32.exp: Don't run inval. * gas/i386/ilp32/inval.l: Removed. * gas/i386/ilp32/inval.s: Likewise. * gas/i386/ilp32/quad.d: Expect R_X86_64_64 instead of R_X86_64_32. * gas/i386/ilp32/x86-64-pcrel.s: Add tests for movabs. * gas/i386/ilp32/x86-64-pcrel.d: Updated. ld/testsuite/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * ld-x86-64/ilp32-6.d: New. * ld-x86-64/ilp32-6.s: Likewise. * ld-x86-64/ilp32-7.d: Likewise. * ld-x86-64/ilp32-7.s: Likewise. * ld-x86-64/ilp32-8.d: Likewise. * ld-x86-64/ilp32-8.s: Likewise. * ld-x86-64/ilp32-9.d: Likewise. * ld-x86-64/ilp32-9.s: Likewise. * ld-x86-64/x86-64.exp: Run ilp32-6, ilp32-7, ilp32-8 and ilp32-9. opcodes/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * i386-dis.c (print_insn): Optimize info->mach check.
2011-07-22Add initial Intel K1OM support.H.J. Lu1-0/+29
bfd/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am (ALL_MACHINES): Add cpu-k1om.lo. (ALL_MACHINES_CFILES): Add cpu-k1om.c. * Makefile.in: Regenerated. * archures.c (bfd_architecture): Add bfd_arch_k1om. (bfd_k1om_arch): New. (bfd_archures_list): Add &bfd_k1om_arch. * bfd-in2.h: Regenerated. * config.bfd (targ64_selvecs): Add bfd_elf64_k1om_vec if bfd_elf64_x86_64_vec is supported. Add bfd_elf64_k1om_freebsd_vec if bfd_elf64_x86_64_freebsd_vec is supported. (targ_selvecs): Likewise. * configure.in: Support bfd_elf64_k1om_vec and bfd_elf64_k1om_freebsd_vec. * configure: Regenerated. * cpu-k1om.c: New. * elf64-x86-64.c (elf64_k1om_elf_object_p): New. (bfd_elf64_k1om_vec): Likewise. (bfd_elf64_k1om_freebsd_vec): Likewise. * targets.c (bfd_elf64_k1om_vec): New. (bfd_elf64_k1om_freebsd_vec): Likewise. (_bfd_target_vector): Add bfd_elf64_k1om_vec and bfd_elf64_k1om_freebsd_vec. binutils/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * dwarf.c (init_dwarf_regnames): Handle EM_K1OM. * elfedit.c (elf_machine): Support EM_K1OM. (elf_class): Likewise. * readelf.c (guess_is_rela): Handle EM_K1OM. (dump_relocations): Likewise. (get_machine_name): Likewise. (get_section_type_name): Likewise. (get_elf_section_flags): Likewise. (process_section_headers): Likewise. (get_symbol_index_type): Likewise. (is_32bit_abs_reloc): Likewise. (is_32bit_pcrel_reloc): Likewise. (is_64bit_abs_reloc): Likewise. (is_64bit_pcrel_reloc): Likewise. (is_none_reloc): Likewise. * doc/binutils.texi: Mention K1OM for elfedit. binutils/testsuite/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * binutils-all/elfedit.exp: Run elfedit-4. * binutils-all/elfedit-4.d: New. gas/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add k1om. (i386_align_code): Handle PROCESSOR_K1OM. (check_cpu_arch_compatible): Check EM_K1OM. (i386_arch): Handle Intel K1OM. (i386_mach): Return bfd_mach_k1om for Intel K1OM. (i386_target_format): Return ELF_TARGET_K1OM_FORMAT for Intel K1OM. * config/tc-i386.h (ELF_TARGET_K1OM_FORMAT): New. (processor_type): Add PROCESSOR_K1OM. * doc/c-i386.texi: Document k1om. gas/testsuite/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/k1om.d: New. * gas/i386/k1om-inval.l: Likewise. * gas/i386/k1om-inval.s: Likewise. * gas/i386/i386.exp: Run k1om-inval and k1om. include/elf/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * common.h (EM_K1OM): New. ld/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am (ALL_64_EMULATIONS): Add eelf_k1om.o and eelf_k1om_fbsd.o (eelf_k1om.c): New. (eelf_k1om_fbsd.c): Likewise. * Makefile.in: Regenerated. * configure.tgt (targ64_extra_emuls): Add elf_k1om if elf_x86_64 is supported. Add elf_k1om_fbsd if elf_x86_64_fbsd is supported. (targ_extra_emuls): Likewise. * emulparams/elf_k1om.sh: New. * emulparams/elf_k1om_fbsd.sh: Likewise. ld/testsuite/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * ld-x86-64/abs-k1om.d: New. * ld-x86-64/protected2-k1om.d: Likewise. * ld-x86-64/protected3-k1om.d: Likewise. * ld-x86-64/x86-64.exp: Run abs-k1om, protected2-k1om and protected3-k1om. opcodes/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * configure.in: Handle bfd_k1om_arch. * configure: Regenerated. * disassemble.c (disassembler): Handle bfd_k1om_arch. * i386-dis.c (print_insn): Handle bfd_mach_k1om and bfd_mach_k1om_intel_syntax. * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS. (cpu_flags): Add CpuK1OM. * i386-opc.h (CpuK1OM): New. (i386_cpu_flags): Add cpuk1om. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2011-06-292011-06-29 Tristan Gingold <gingold@adacore.com>Tristan Gingold1-27/+13
* config/tc-i386.c (i386_mach): Convert to ISO-C. (md_begin, pe_directive_secrel, md_estimate_size_before_relax): Ditto. (md_convert_frag, md_apply_fix, md_undefined_symbol): Ditto. (md_section_align, tc_gen_reloc): Ditto.
2011-06-10Support AVX Programming Reference (June, 2011).H.J. Lu1-5/+104
gas/ 2011-06-10 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * config/tc-i386.c (i386_error): Add invalid_vsib_address and unsupported_vector_index_register. (cpu_arch): Add .avx2, .bmi2, .lzcnt and .invpcid. (check_VecOperands): New. (match_template): Call check_VecOperands. Handle invalid_vsib_address and unsupported_vector_index_register. (build_modrm_byte): Support VecSIB. Check register-only source operand when two source operands are swapped. (i386_index_check): Allow Xmm/Ymm index registers. * doc/c-i386.texi: Document avx2/.avx2, bmi2/.bmi2, lzcnt/.lzcnt and invpcid./invpcid. gas/testsuite/ 2011-06-10 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * gas/i386/arch-10-1.l: Updated. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10.s: Add LZCNT to comments. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/arch-10-lzcnt.d: New. * gas/i386/avx-gather-intel.d: Likewise. * gas/i386/avx-gather.d: Likewise. * gas/i386/avx-gather.s: Likewise. * gas/i386/avx2-intel.d: Likewise. * gas/i386/avx2.d: Likewise. * gas/i386/avx2.s: Likewise * gas/i386/avx256int-intel.d: Likewise. * gas/i386/avx256int.d: Likewise. * gas/i386/avx256int.s: Likewise. * gas/i386/bmi2-intel.d: Likewise. * gas/i386/bmi2.d: Likewise. * gas/i386/bmi2.s: Likewise. * gas/i386/inval-invpcid.l:Likewise. * gas/i386/inval-invpcid.s: Likewise. * gas/i386/invpcid-intel.d: Likewise. * gas/i386/invpcid.d: Likewise. * gas/i386/invpcid.s: Likewise. * gas/i386/x86-64-arch-2-lzcnt.d: Likewise. * gas/i386/x86-64-avx-gather-intel.d: Likewise. * gas/i386/x86-64-avx-gather.d: Likewise. * gas/i386/x86-64-avx-gather.s: Likewise. * gas/i386/x86-64-avx2-intel.d: Likewise. * gas/i386/x86-64-avx2.d: Likewise. * gas/i386/x86-64-avx2.s: Likewise. * gas/i386/x86-64-avx256int-intel.d: Likewise. * gas/i386/x86-64-avx256int.d: Likewise. * gas/i386/x86-64-avx256int.s: Likewise. * gas/i386/x86-64-bmi2-intel.d: Likewise. * gas/i386/x86-64-bmi2.d: Likewise. * gas/i386/x86-64-bmi2.s: Likewise. * gas/i386/x86-64-inval-invpcid.l: Likewise. * gas/i386/x86-64-inval-invpcid.s: Likewise. * gas/i386/x86-64-invpcid-intel.d: Likewise. * gas/i386/x86-64-invpcid.d: Likewise. * gas/i386/x86-64-invpcid.s: Likewise. opcodes/ 2011-06-10 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * i386-dis.c (XMGatherQ): New. * i386-dis.c (EXxmm_mb): New. (EXxmm_mb): Likewise. (EXxmm_mw): Likewise. (EXxmm_md): Likewise. (EXxmm_mq): Likewise. (EXxmmdw): Likewise. (EXxmmqd): Likewise. (VexGatherQ): Likewise. (MVexVSIBDWpX): Likewise. (MVexVSIBQWpX): Likewise. (xmm_mb_mode): Likewise. (xmm_mw_mode): Likewise. (xmm_md_mode): Likewise. (xmm_mq_mode): Likewise. (xmmdw_mode): Likewise. (xmmqd_mode): Likewise. (ymmxmm_mode): Likewise. (vex_vsib_d_w_dq_mode): Likewise. (vex_vsib_q_w_dq_mode): Likewise. (MOD_VEX_0F385A_PREFIX_2): Likewise. (MOD_VEX_0F388C_PREFIX_2): Likewise. (MOD_VEX_0F388E_PREFIX_2): Likewise. (PREFIX_0F3882): Likewise. (PREFIX_VEX_0F3816): Likewise. (PREFIX_VEX_0F3836): Likewise. (PREFIX_VEX_0F3845): Likewise. (PREFIX_VEX_0F3846): Likewise. (PREFIX_VEX_0F3847): Likewise. (PREFIX_VEX_0F3858): Likewise. (PREFIX_VEX_0F3859): Likewise. (PREFIX_VEX_0F385A): Likewise. (PREFIX_VEX_0F3878): Likewise. (PREFIX_VEX_0F3879): Likewise. (PREFIX_VEX_0F388C): Likewise. (PREFIX_VEX_0F388E): Likewise. (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise. (PREFIX_VEX_0F38F5): Likewise. (PREFIX_VEX_0F38F6): Likewise. (PREFIX_VEX_0F3A00): Likewise. (PREFIX_VEX_0F3A01): Likewise. (PREFIX_VEX_0F3A02): Likewise. (PREFIX_VEX_0F3A38): Likewise. (PREFIX_VEX_0F3A39): Likewise. (PREFIX_VEX_0F3A46): Likewise. (PREFIX_VEX_0F3AF0): Likewise. (VEX_LEN_0F3816_P_2): Likewise. (VEX_LEN_0F3819_P_2): Likewise. (VEX_LEN_0F3836_P_2): Likewise. (VEX_LEN_0F385A_P_2_M_0): Likewise. (VEX_LEN_0F38F5_P_0): Likewise. (VEX_LEN_0F38F5_P_1): Likewise. (VEX_LEN_0F38F5_P_3): Likewise. (VEX_LEN_0F38F6_P_3): Likewise. (VEX_LEN_0F38F7_P_1): Likewise. (VEX_LEN_0F38F7_P_2): Likewise. (VEX_LEN_0F38F7_P_3): Likewise. (VEX_LEN_0F3A00_P_2): Likewise. (VEX_LEN_0F3A01_P_2): Likewise. (VEX_LEN_0F3A38_P_2): Likewise. (VEX_LEN_0F3A39_P_2): Likewise. (VEX_LEN_0F3A46_P_2): Likewise. (VEX_LEN_0F3AF0_P_3): Likewise. (VEX_W_0F3816_P_2): Likewise. (VEX_W_0F3818_P_2): Likewise. (VEX_W_0F3819_P_2): Likewise. (VEX_W_0F3836_P_2): Likewise. (VEX_W_0F3846_P_2): Likewise. (VEX_W_0F3858_P_2): Likewise. (VEX_W_0F3859_P_2): Likewise. (VEX_W_0F385A_P_2_M_0): Likewise. (VEX_W_0F3878_P_2): Likewise. (VEX_W_0F3879_P_2): Likewise. (VEX_W_0F3A00_P_2): Likewise. (VEX_W_0F3A01_P_2): Likewise. (VEX_W_0F3A02_P_2): Likewise. (VEX_W_0F3A38_P_2): Likewise. (VEX_W_0F3A39_P_2): Likewise. (VEX_W_0F3A46_P_2): Likewise. (MOD_VEX_0F3818_PREFIX_2): Removed. (MOD_VEX_0F3819_PREFIX_2): Likewise. (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise. (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise. (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise. (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise. (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise. (VEX_LEN_0F3A0E_P_2): Likewise. (VEX_LEN_0F3A0F_P_2): Likewise. (VEX_LEN_0F3A42_P_2): Likewise. (VEX_LEN_0F3A4C_P_2): Likewise. (VEX_W_0F3818_P_2_M_0): Likewise. (VEX_W_0F3819_P_2_M_0): Likewise. (prefix_table): Updated. (three_byte_table): Likewise. (vex_table): Likewise. (vex_len_table): Likewise. (vex_w_table): Likewise. (mod_table): Likewise. (putop): Handle "LW". (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode, xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode, vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode. (OP_EX): Likewise. (OP_E_memory): Handle vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. (OP_XMM): Handle vex_vsib_q_w_dq_mode. (OP_VEX): Likewise. * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS, CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS. (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID. (opcode_modifiers): Add VecSIB. * i386-opc.h (CpuAVX2): New. (CpuBMI2): Likewise. (CpuLZCNT): Likewise. (CpuINVPCID): Likewise. (VecSIB128): Likewise. (VecSIB256): Likewise. (VecSIB): Likewise. (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid. (i386_opcode_modifier): Add vecsib. * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2011-05-122011-05-12 Quentin Neill <quentin.neill@amd.com>Quentin Neill1-5/+5
* config/tc-i386.c (cpu_arch): Rename PROCESSOR_BDVER1 to PROCESSOR_BD. (i386_align_code): Ditto
2011-05-102011-05-10 Quentin Neill <quentin.neill@amd.com>Quentin Neill1-4/+6
gas/ * config/tc-i386.c (cpu_arch): Add bdver2 and rename PROCESSOR_BDVER1 to PROCESSOR_BDVER. (i386_align_code): Rename PROCESSOR_BDVER1. (processor_type): Ditto. * doc/c-i386.texi: Add bdver2. opcodes/ * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS. * i386-init.h: Regenerated. gas/testsuite/ * gas/i386/i386.exp: Add new bdver2 test cases. * gas/i386/nops-1-bdver2.d: New. * gas/i386/x86-64-nops-1-bdver2.d: New.
2011-04-12Start error message with lower case.H.J. Lu1-19/+19
2011-04-12 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (i386_mach): Start error message with lower case. (md_begin): Likewise. (md_parse_option): Likewise. (i386_target_format): Likewise. (check_byte_reg): Likewise. (check_long_reg): Likewise. (check_qword_reg): Likewise. (check_word_reg): Likewise.
2011-04-112011-04-11 Kai Tietz <ktietz@redhat.com>Kai Tietz1-1/+1
* config/tc-i386.c (x86_cons): Initialize adjust with zero.
2011-04-11 * config/tc-i386.c (x86_cons): Define even for non-ELF targets.Nick Clifton1-1/+1
* config/tc-i386.h (x86_cons): Always prototype.
2011-03-29Properly handle multiple operands for x32 quad.H.J. Lu1-8/+8
gas/ 2011-03-29 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (handle_quad): Properly handle multiple operands. gas/testsuite/ 2011-03-29 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/ilp32/quad.d: Add tests for multiple operands. * gas/i386/ilp32/quad.s: Likewise.
2011-03-28Support .quad for x32.H.J. Lu1-0/+48
gas/ 2011-03-28 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (handle_quad): New. (md_pseudo_table): Add "quad". gas/testsuite/ 2011-03-28 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/ilp32/inval.s: Remove .quad. * gas/i386/ilp32/inval.l: Updated. * gas/i386/ilp32/quad.d: New. * gas/i386/ilp32/quad.s: Likewise.
generated by cgit v1.1 at 2024-08-31 14:18:24 +0000