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2018-01-12Fix compile time warning building aout targeted architectures.Gunther Nikl1-0/+6
Occasionally I build an out-of-tree a.out target (m68k-amigaos). After a system upgrade which included a newer compiler (clang 4) the build produces warnings like this: warning: macro expansion producing 'defined' has undefined behavior [-Wexpansion-to-defined] This is caused by the macro gas/config/aout_gnu.h:USE_EXTENDED_RELOC. Since it is in a header file, the warning triggers for several files. I am unsure what solution is preferable, thus I am suggesting two patches: a) keep the offending macro but define it explicitly to 0 and 1 b) replace the macro usage with its value where it is used. Either patch removes the warning for clang. I did not check with a recent GCC. * gas/config/aout_gnu.h (USE_EXTENDED_RELOC): Explicitly define to 0 and 1. Remove a dangling reference to "AMD 29000" in a comment.
2018-01-11Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist1-0/+20
AVX512_4FMAPS and AVX512_4VNNIW insns are marked as having AVX512VL variants. That is wrong as SDM doesn't define such instructions. The patch removes these VL variants. gas/ * testsuite/gas/i386/avx512_4fmaps-warn.l: Change xmm to zmm. * testsuite/gas/i386/avx512_4fmaps-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Delete _vl tests for 4fmaps an 4vnniw tests. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s: Likewise. opcodes/ * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns. * i386-tbl.h: Regenerate.
2018-01-11gas tc-arm.c warning fixAlan Modra1-0/+5
* config/tc-arm.c (aeabi_set_public_attributes): Avoid false positive "‘profile’ may be used uninitialized".
2018-01-10x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich1-0/+18
Just like their packed counterparts the memory operand is always 16 bytes wide, and the Disp8 scaling is the same for all of them. (As a side note: I'm also surprised by there being AVX512VL variants of these as well as the AVX512_4VNNIW ones - the SDM doesn't define any such.) Adjust the test cases also for the packed forms to actually live up to their promise of testing correct Disp8 encoding.
2018-01-10x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich1-0/+10
In commit 2645e1d079 ("x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops") I screwed up the Disp8MemShift values of the AVX512VL variants.
2018-01-09RISC-V: Disassemble x0 based addresses as 0.Jim Wilson1-0/+5
gas/ * testsuite/gas/riscv/auipc-x0.d: New. * testsuite/gas/riscv/auipc-x0.s: New. opcodes/ * riscv-dis.c (maybe_print_address): If base_reg is zero, then the hi_addr value is zero.
2018-01-09[Arm] Add CSDB instructionJames Greenhalgh1-0/+10
CSDB is a new instruction which Arm has defined. As it shares the encoding space with NOP instructions, it is available from Armv3 in Arm mode, and Armv6T2 in Thumb mode. OK? If so, please commit on my behalf as I don't have commit rights over here. Thanks, James --- opcodes/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * arm-dis.c (arm_opcodes): Add csdb. (thumb32_opcodes): Add csdb. gas/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * config/tc-arm.c (insns): Add csdb, enable for Armv3 and above in Arm execution state, and Armv6T2 and above in Thumb execution state. * testsuite/gas/arm/csdb.s: New. * testsuite/gas/arm/csdb.d: New. * testsuite/gas/arm/thumb2_it_bad.l: Add csdb. * testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh1-0/+5
CSDB is a new instruction which Arm has defined. It has the same encoding as HINT #0x14 and is available at all architecture levels. opcodes * aarch64-tbl.h (aarch64_opcode_table): Add "csdb". * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * testsuite/gas/aarch64/system.d: Update expected results to expect CSDB.
2018-01-08x86: Properly encode vmovd with 64-bit memeoryH.J. Lu1-0/+9
For historical reason, we allow movd/vmovd with 64-bit register and memeory operands. But for vmovd, we failed to handle 64-bit memeory operand. This has been gone unnoticed since AT&T syntax always treats memory operand as 32-bit memory. This patch properly encodes vmovd with 64-bit memeory operands. It also removes AVX512 vmovd with 64-bit operands since GCC has case TYPE_SSEMOV: switch (get_attr_mode (insn)) { case MODE_DI: /* Handle broken assemblers that require movd instead of movq. */ if (!HAVE_AS_IX86_INTERUNIT_MOVQ && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) return "%vmovd\t{%1, %0|%0, %1}"; return "%vmovq\t{%1, %0|%0, %1}"; and all AVX512 GNU assemblers set HAVE_AS_IX86_INTERUNIT_MOVQ, GCC won't generate AVX512 vmovd with 64-bit operand. gas/ PR gas/22681 * testsuite/gas/i386/i386.exp: Run x86-64-movd and x86-64-movd-intel. * testsuite/gas/i386/x86-64-movd-intel.d: New file. * testsuite/gas/i386/x86-64-movd.d: Likewise. * testsuite/gas/i386/x86-64-movd.s: Likewise. opcodes/ PR gas/22681 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand. Remove AVX512 vmovd with 64-bit operands. * i386-tbl.h: Regenerated.
2018-01-08Add a description of the X86_64 assembler's .largcomm pseudo-op.Nick Clifton1-0/+6
PR 22553 * doc/c-i386.texi (i386-Directives): Document the .largecomm directive.
2018-01-04RISC-V: Add 2 missing privileged registers.Jim Wilson1-0/+5
gas/ * testsuite/gas/riscv/priv-reg.s: Add missing stval and mtval. * testsuite/gas/riscv/priv-reg.d: Likewise. include/ * opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL. Rename DECLARE_CSR entry. Add alias to map sbadaddr to CSR_STVAL. (CSR_MBADADDR): Rename to CSR_MTVAL. Rename DECLARE_CSR entry. Add alias to map mbadaddr to CSR_MTVAL.
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-0/+4
2018-01-03ChangeLog rotationAlan Modra1-4407/+2
2018-01-02Fix typo in do_mrs function in ARM assembler.Nick Clifton1-0/+6
PR 18119 * config/tc-arm.c (do_mrs): Fix test of bits 16-19 in non-banked version of ARM MRS instruction.
2017-12-28RISC-V: Add missing privileged spec registers.Jim Wilson1-0/+4
gas/ * testsuite/gas/riscv/priv-reg.d, testsuite/gas/riscv/priv-reg.s: New. include/ * opcode/riscv-opc.h (DECLARE_CSR): Add missing privileged registers. Sort to match privileged spec documentation order. (DECLARE_CSR_ALIAS): Add ubadaddr, and comments.
2017-12-20RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson1-0/+15
gas/ * config/tc-riscv.c (risc_ip) <o>: Add comment. * testsuite/gas/riscv/c-nonzero-imm.d, * testsuite/gas/riscv/c-nonzero-imm.l, * testsuite/gas/riscv/c-nonzero-imm.s, * testsuite/gas/riscv/c-nonzero-reg.d, * testsuite/gas/riscv/c-nonzero-reg.l, * testsuite/gas/riscv/c-nonzero-reg.s, * testsuite/gas/riscv/c-zero-imm-64.d, * testsuite/gas/riscv/c-zero-imm-64.s, * testsuite/gas/riscv/c-zero-imm.d, testsuite/gas/riscv/c-zero-imm.s, * testsuite/gas/riscv/c-zero-reg.d, * testsuite/gas/riscv/c-zero-reg.s: New. opcodes/ * riscv-opc.c (match_c_add_with_hint, match_c_lui_with_hint): New. (riscv_opcodes) <li>: Delete "d,0" line. Change Cj to Co. <andi, and, add, addiw, addw, c.addi>: Change Cj to Co. <add>: Add explanatory comment for 4-operand add instruction. <c.nop>: Add support for immediate operand. <c.mv, c.add>: Use match_c_add_with_hint instead of match_c_add. <c.lui>: Use match_c_lui_with_hint instead of match_c_lui. <c.li, c.slli>: Use match_opcode instead of match_rd_nonzero.
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-0/+6
Dot products deviate from the normal disassembly rules for lane indexed instruction. Their canonical representation is in the form of: v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote that these instructions select 4x 1 byte elements instead of a single 1 byte element. Previously we were disassembling them following the normal rules, this patch corrects the disassembly. gas/ PR gas/22559 * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B. * gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly. include/ PR gas/22559 * aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B. opcodes/ PR gas/22559 * aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant. * aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina1-0/+8
Previously parse_vector_type_for_operand was changed to allow the use of 4b register size for indexed lane instructions. However this had the unintended side effect of also allowing 4b for normal vector registers. Because this support was only partial the rest of the tool silently treated 4b as 8b and continued. This patch adds full support for 4b so it can be properly distinguished from 8b and the correct errors are generated. With this patch you still can't encode any instruction which actually requires v<num>.4b but such instructions don't exist so to prevent needing a workaround in get_vreg_qualifier_from_value this was just omitted. gas/ PR gas/22529 * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_V_4B. * gas/testsuite/gas/aarch64/pr22529.s: New. * gas/testsuite/gas/aarch64/pr22529.d: New. * gas/testsuite/gas/aarch64/pr22529.l: New. include/ PR gas/22529 * opcode/aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_4B. opcodes/ PR gas/22529 * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
2017-12-18Resolve PR 22493 - the encoding to be used when pushing the stack pointer ↵Nick Clifton1-0/+6
onto the stack. PR 22493 * config/tc-arm.c (encode_ldmstm): Do not use A2 encoding of the PUSH insn when pushing the stack pointer.
2017-12-18x86: fold certain AVX and AVX2 templatesJan Beulich1-0/+9
Just like for instructions in GPRs, there's no need to have separate templates for otherwise identical insns acting on XMM or YMM registers (or memory of the same size).
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich1-0/+18
... qualified by their respective sizes, allowing to drop FirstXmm0 at the same time.
2017-12-18x86: drop FloatReg and FloatAccJan Beulich1-0/+10
Express them as Reg|Tbyte and Acc|Tbyte respectively.
2017-12-18x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich1-0/+20
Use a combination of a single new Reg bit and Byte, Word, Dword, or Qword instead. Besides shrinking the number of operand type bits this has the benefit of making register handling more similar to accumulator handling (a generic flag is being accompanied by a "size qualifier"). It requires, however, to split a few insn templates, as it is no longer correct to have combinations like Reg32|Reg64|Byte. This slight growth in size will hopefully be outweighed by this change paving the road for folding a presumably much larger number of templates later on.
2017-12-17x86: Check pseudo prefix without instructionH.J. Lu1-0/+9
Pseudo prefixes must be used on an instruction. Issue an error when pseudo prefix is used without instruction. PR gas/22623 * gas/config/tc-i386.c (output_insn): Check pseudo prefix without instruction. * testsuite/gas/i386/i386.exp: Run inval-pseudo. * testsuite/gas/i386/inval-pseudo.l: New file. * testsuite/gas/i386/inval-pseudo.s: Likewise.
2017-12-15x86: correct operand type checksJan Beulich1-0/+5
Again these look to be typos: No template currently allows for any two (or all three) of RegXMM, RegYMM, and RegZMM in a single operand. Quite clearly ! are missing, after the addition of which the checks for the first and (if present) second operands also fully match up.
2017-12-15x86: correct abort checkJan Beulich1-0/+5
I'm rather certain the missing ! was just a typo, the more with the similar check in mind that's in the same function a few hundred lines down (in the body of "if (vex_reg != (unsigned int) ~0)"). Of course this can't be demonstrated by a test case - internal data structure consistency is being checked here, and neither form of the check triggers with any current template. It is also not really clear to me why operand_type_equal() is being used in the {X,Y,Z}MM register check here, rather than just testing the respective bits: Just like Reg32|Reg64 is legal in an operand template, I don't see why e.g. RegXMM|RegYMM wouldn't be. For example it ought to be possible to combine vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } into a single template (with setting of VEX.L suitably handled elsewhere if that's not already happening anyway). Additionally I don't understand why this uses abort() instead of gas_assert(). Both of these latter considerations then also apply to the aforementioned other check in the same function.
2017-12-14Update the address of the FSF in the copyright notice of files which were ↵Nick Clifton1-0/+10
using the old address. top * COPYING.LIBGLOSS: Update address of FSF in copyright notice. bfd * cpu-mt.c: Update address of FSF in copyright notice. * elf32-m32c.c: Likewise. * elf32-mt.c: Likewise. * elf32-rl78.c: Likewise. * elf32-rx.c: Likewise. * elf32-rx.h: Likewise. * elf32-spu.h: Likewise. * hosts/x86-64linux.h: Likewise. etc * add-log.el: Update address of FSF in copyright notice. gas * config/tc-m32c.c: Update address of FSF in copyright notice. * config/tc-m32c.h: Likewise. * config/tc-mt.c: Likewise. * config/tc-mt.h: Likewise. * config/tc-visium.c: Likewise. * config/tc-visium.h: Likewise. * testsuite/gas/rx/explode: Likewise. ld * testsuite/ld-mn10300/mn10300.exp: Update address of FSF in copyright notice.
2017-12-13Add missing RISC-V fsrmi and fsflagsi instructions.Jim Wilson1-0/+5
PR 22599 gas/ * testsuite/gas/riscv/fsxxi.d, testsuite/gas/riscv/fsxxi.s: New. opcodes/ * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
2017-12-13This patch enables disassembler_needs_relocs for PRU. It is needed to print ↵Dimitar Dimitrov1-0/+6
correct symbols when disassembling arguments of "call" instructions with a relocation. opcodes * disassemble.c: Enable disassembler_needs_relocs for PRU. gas * testsuite/gas/pru/extern.s: New test for print of U16_PMEMM relocation. * testsuite/gas/pru/extern.d: New test driver.
2017-12-12Don't mask X_add_number containing a register numberAlan Modra1-0/+5
It's obviously wrong to mask SPRs to 8 bits. PR 21118 * config/tc-ppc.c (md_assemble): Don't mask register number.
2017-12-08gas: xtensa: fix comparison of trampoline chain symbolsMax Filippov1-0/+6
Don't use address where symbol gets resolved, as during section relaxation symbols will slide, instead canonicalize symbols and check that they are are the same. This fixes a bug when a relaxed jump goes into the wrong trampoline. gas/ 2017-12-07 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (xg_order_trampoline_chain): Replace xg_order_trampoline_chain_entry call with check for canonicalized symbol equality and offset equality.
2017-12-04Documentation fixAlan Modra1-0/+5
PR 22544 * doc/as.texinfo (8byte): Correct.
2017-12-04Run powerpc vle gas tests for all powerpc ELF targetsAlan Modra1-0/+21
* testsuite/gas/ppc/ppc.exp: Don't exclude VLE tests when little-endian. * testsuite/gas/ppc/efs.d: Add -mbig to assembler options. * testsuite/gas/ppc/efs2.d: Likewise. * testsuite/gas/ppc/lsp-checks.d: Likewise. * testsuite/gas/ppc/lsp.d: Likewise. * testsuite/gas/ppc/spe.d: Likewise. * testsuite/gas/ppc/spe2-checks.d: Likewise. * testsuite/gas/ppc/spe2.d: Likewise. * testsuite/gas/ppc/spe_ambiguous.d: Likewise. * testsuite/gas/ppc/vle-mult-ld-st-insns.d: Likewise. * testsuite/gas/ppc/vle-reloc.d: Likewise. * testsuite/gas/ppc/vle-simple-1.d: Likewise. * testsuite/gas/ppc/vle-simple-2.d: Likewise. * testsuite/gas/ppc/vle-simple-3.d: Likewise. * testsuite/gas/ppc/vle-simple-4.d: Likewise. * testsuite/gas/ppc/vle-simple-5.d: Likewise. * testsuite/gas/ppc/vle-simple-6.d: Likewise. * testsuite/gas/ppc/vle.d: Likewise.
2017-12-03Fix for texinfo 4.8.Jim Wilson1-0/+5
gas/ * doc/c-riscv.texi (RISC-V-Directives): Move @section immediately after @node.
2017-12-01Update and clean up RISC-V gas documentation.Jim Wilson1-0/+11
gas/ * doc/as.texinfo (RISC-V): Alphabetize RISC-V entries. Change RISC-V-Opts to RISC-V-Options. Delete redundant space. Add -fpic and related options to option list. * doc/c-riscv.texi: (RISC-V-Options): Renamed from RISC-V-Opts. (RISC-V Options): Renamed from Options. Add missing period. (-fpic): Also mention -fPIC. (RISC-V Directives): New node.
2017-12-01Use consistent types for holding instructions, instruction masks, etc.Peter Bergner1-0/+12
include/ * opcode/ppc.h (PPC_INT_FMT): Define. (struct powerpc_opcode) <opcode>: Update type. (struct powerpc_opcode) <mask>: Likewise. (struct powerpc_opcode) <bitm>: Likewise. (struct powerpc_opcode) <insert>: Likewise. (struct powerpc_opcode) <extract>: Likewise. (ppc_optional_operand_value): Likewise. gas/ * config/tc-ppc.c (last_insn): Update type. (insn_validate) <omask, mask>: Likewise. (ppc_setup_opcodes) <mask, right_bit>: Likewise. <PRINT_OPCODE_TABLE>: Update types and printf format specifiers. (ppc_insert_operand): Update return and argument types and remove unneeded type casts. <min, max, right, tmp>: Update type. (md_assemble): Remove unneeded type casts. <insn, val, tmp_insn>: Update type. opcodes/ * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space. (operand_value_powerpc): Update return and argument type. <value, top>: Update type. (skip_optional_operands): Update argument type. (lookup_powerpc): Likewise. (lookup_vle): Likewise. <table_opcd, table_mask, insn2>: Update type. (lookup_spe2): Update argument type. <table_opcd, table_mask, insn2>: Update type. (print_insn_powerpc) <insn, value>: Update type. Use PPC_INT_FMT for printing instructions and operands. * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary, insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat, insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp, extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo, extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm, extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls, insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6, extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi, insert_ral, extract_ral, insert_ram, extract_ram, insert_raq, extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs, insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n, extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w, insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr, extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr, insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6, extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s, insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi, extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui, extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0, extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0, insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0, extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8, insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even, extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2, extract_off_spe2, insert_Ddd, extract_Ddd): Update types. (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15, BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX, DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK, SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST, VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET, VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA, VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK, XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK, XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK, XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB, XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
2017-11-30x86: drop Vec_Disp8Jan Beulich1-0/+12
This is fully redundant with Disp8MemShift being non-zero, and hence can be folded with normal Disp8 handling.
2017-11-30x86/Intel: issue diagnostics for redundant segment override prefixesJan Beulich1-0/+12
While we shouldn't outright reject such (as was wrongly done by commit 4d36230d59 ("x86: Update segment register check in Intel syntax"), as MASM accepts them even silently, issue (by default) a warning for such questionable constructs.
2017-11-30Revert "x86: Update segment register check in Intel syntax"Jan Beulich1-13/+0
This reverts commit 4d36230d59903b92fbe2b53b31ed64a884860f0e. I was committed without maintainer ack and regresses intended functionality. A replacement will be committed shortly.
2017-11-29Give Palmer co-credit for last patch.Jim Wilson1-0/+1
2017-11-29Fix riscv malloc error on small alignment after norvc.Jim Wilson1-0/+7
gas/ * config/tc-riscv.c (riscv_frag_align_code): New local insn_alignment. Early return if bytes less than or equal to insn_alignment. * testsuite/gas/riscv/align-1.l: New. * testsuite/gas/riscv/align-1.s: New. * testsuite/gas/riscv/riscv.exp: Use run_dump_tests. Use run_list_test for align-1.
2017-11-29In x86 -n docs, mention that you need an explicit nop fill byte.Jim Wilson1-0/+5
gas/ PR gas/22464 * doc/c-i386.texi (-n): Clarify docs.
2017-11-29[GAS][AARCH64]Fix a typo for IP1 register alias.Renlin Li1-0/+6
This should be an obvious fix. It corrects the register number for IP1 to 17. gas/ 2017-11-29 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reg_names): Fix IP1 register alias error. * testsuite/gas/aarch64/register_aliases.s: Add IP0 and IP1 tests. * testsuite/gas/aarch64/register_aliases.d: Update.
2017-11-29Support --localedir, --datarootdir and --datadirStefan Stroe1-0/+6
bfd/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. binutils/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. gas/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. gold/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. gprof/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. ld/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. opcodes/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@.
2017-11-29Use the record_alignment function when creating a .note section, in case the ↵Nick Clifton1-1/+6
user has already created the section. PR 22492 * config/obj-elf.c (obj_elf_version): Use record_alignment rather than bfd_set_section_alignment.
2017-11-27Compress loads/stores with implicit 0 offset.Jim Wilson1-0/+13
gas/ * config/tc-riscv.c (riscv_handle_implicit_zero_offset): New. (riscv_ip): Cases 'k', 'l', 'm', 'n', 'M', 'N', add call to riscv_handle_implicit_zero_offset. At label load_store, replace existing code with call to riscv_handle_implicit_zero_offset. * testsuite/gas/riscv/c-ld.d, testsuite/gas/riscv/c-ld.s: New. * testsuite/gas/riscv/c-lw.d, testsuite/gas/riscv/c-lw.s: New. * testsuite/gas/riscv/riscv.exp: Run new tests.
2017-11-27gas: xtensa: speed up find_trampoline_segMax Filippov1-0/+5
find_trampoline_seg takes noticeable time when assembling source with many sections. Cache the result of the most recent search and check it first. No functional changes. gas/ 2017-11-27 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (find_trampoline_seg): Add static variable that caches the result of the most recent search.
2017-11-27gas: xtensa: implement trampoline coalescingMax Filippov1-0/+29
There is a recurring pattern in assembly files generated by a compiler where a lot of jumps in a function are going to the same place. When these jumps are relaxed with trampolines the assembler generates a separate jump thread from each source. Create an index of trampoline jump targets for each segment and see if a jump being relaxed goes to a location from that index, in which case replace its target with a location of existing trampoline jump that results in the shortest path to the original target. gas/ 2017-11-27 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (trampoline_chain_entry, trampoline_chain) (trampoline_chain_index): New structures. (trampoline_index): Add chain_index field. (xg_order_trampoline_chain_entry, xg_sort_trampoline_chain) (xg_find_chain_entry, xg_get_best_chain_entry) (xg_order_trampoline_chain, xg_get_trampoline_chain) (xg_find_best_eq_target, xg_add_location_to_chain) (xg_create_trampoline_chain, xg_get_single_symbol_slot): New functions. (xg_relax_fixups): Call xg_find_best_eq_target to adjust jump target to point to an existing jump. Call xg_create_trampoline_chain to create new jump target. Call xg_add_location_to_chain to add newly created trampoline jump to the corresponding chain. (add_jump_to_trampoline): Extract loop searching for a single slot with a symbol into a separate function, replace that code with a call to that function. (relax_frag_immed): Call xg_find_best_eq_target to adjust jump target to point to an existing jump. * testsuite/gas/xtensa/all.exp: Add trampoline-2 test. * testsuite/gas/xtensa/trampoline.d: Adjust absolute addresses as many duplicate trampoline chains are now coalesced. * testsuite/gas/xtensa/trampoline.s: Add _nop so that objdump stays in sync with instruction stream. * testsuite/gas/xtensa/trampoline-2.l: New test result file. * testsuite/gas/xtensa/trampoline-2.s: New test source file.
2017-11-27gas: xtensa: reuse trampoline placement codeMax Filippov1-0/+11
There's almost exact copy of the trampoline placement code in the search_trampolines function that is used for jumps generated for relaxed branch instructions. Get rid of the duplication and reuse xg_find_best_trampoline function for that. gas/ 2017-11-27 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (search_trampolines, get_best_trampoline): Remove definitions. (xg_find_best_trampoline_for_tinsn): New function. (relax_frag_immed): Replace call to get_best_trampoline with a call to xg_find_best_trampoline_for_tinsn. * testsuite/gas/xtensa/trampoline.d: Adjust absolute addresses as the placement of trampolines for relaxed branches has been changed.
2017-11-27gas: xtensa: rewrite xg_relax_trampolineMax Filippov1-0/+33
Replace linked list of trampoline frags with an ordered array, so that instead of indexing fixups trampolines could be indexed. Keep each array in the trampoline_seg structure, so there's no need to rebuild it for every new processed segment. Don't run relaxation for each trampoline frag, instead run it for each fixup in the current segment that needs relaxation at the beginning of each relaxation pass. This way the complexity of this process drops from about O(n^2 * m) to about O(log n * m), where n is the number of trampoline frags and m is the number of fixups that need relaxation in the segment. gas/ 2017-11-27 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (trampoline_index): New structure. (trampoline_seg): Replace trampoline list with trampoline index. (xg_find_trampoline, xg_add_trampoline_to_index) (xg_remove_trampoline_from_index, xg_add_trampoline_to_seg) (xg_is_trampoline_frag_full, xg_get_fulcrum) (xg_find_best_trampoline, xg_relax_fixup, xg_relax_fixups) (xg_is_relaxable_fixup): New functions. (J_MARGIN): New macro. (xtensa_create_trampoline_frag): Use xg_add_trampoline_to_seg instead of open-coded addition to the linked list. (dump_trampolines): Iterate through the trampoline_seg::index. (cached_fixupS, cached_fixup, fixup_cacheS, fixup_cache) (fixup_order, xtensa_make_cached_fixup) (xtensa_realloc_fixup_cache, xtensa_cache_relaxable_fixups) (xtensa_find_first_cached_fixup, xtensa_delete_cached_fixup) (xtensa_add_cached_fixup, check_and_update_trampolines): Remove definitions. (xg_relax_trampoline): Extract logic into separate functions, replace body with a call to xg_relax_fixups. (search_trampolines): Replace search in linked list with search in index. Change data type of address-tracking variables from int to offsetT. Replace abs with labs. (xg_append_jump): Finish the trampoline frag if it's full. (add_jump_to_trampoline): Remove trampoline frag from the index if the frag is full. * config/tc-xtensa.h (xtensa_frag_type): Remove next_trampoline. * testsuite/gas/xtensa/trampoline.d: Adjust absolute addresses as the placement of trampolines has slightly changed. * testsuite/gas/xtensa/trampoline.s: Add _nop so that objdump stays in sync with instruction stream.
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