Age | Commit message (Collapse) | Author | Files | Lines |
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For
add %reg1, name@gottpoff(%rip), %reg2
and
add name@gottpoff(%rip), %reg1, %reg2
add
#define R_X86_64_CODE_6_GOTTPOFF 50
if the instruction starts at 6 bytes before the relocation offset.
They are similar to R_X86_64_GOTTPOFF. Linker can covert GOTTPOFF to
add $name@tpoff, %reg1, %reg2
Rewrite fx_tcbit, fx_tcbit2 and fx_tcbit3 usage to generate
R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX, R_X86_64_CODE_4_GOTPCRELX,
R_X86_64_CODE_4_GOTTPOFF, R_X86_64_CODE_4_GOTPC32_TLSDESC and
R_X86_64_CODE_6_GOTTPOFF.
NB: There is no need to check BFD_RELOC_X86_64_CODE_4_GOTTPOFF in
md_assemble since there is only BFD_RELOC_X86_64_GOTTPOFF at this
stage, which will be converted to BFD_RELOC_X86_64_CODE_4_GOTTPOFF
or BFD_RELOC_X86_64_CODE_6_GOTTPOFF in i386_validate_fix.
5 relocations:
#define R_X86_64_CODE_5_GOTPCRELX 46
#define R_X86_64_CODE_5_GOTTPOFF 47
#define R_X86_64_CODE_5_GOTPC32_TLSDESC 48
#define R_X86_64_CODE_6_GOTPCRELX 49
#define R_X86_64_CODE_6_GOTPC32_TLSDESC 51
are added for completeness and they are unused.
bfd/
* elf64-x86-64.c (x86_64_elf_howto_table): Add
R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF,
R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX,
R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC.
(R_X86_64_standard): Updated.
(x86_64_reloc_map): Add R_X86_64_CODE_5_GOTPCRELX,
R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC,
R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and
R_X86_64_CODE_6_GOTPC32_TLSDESC.
(elf_x86_64_check_tls_transition): Handle
R_X86_64_CODE_6_GOTTPOFF.
(elf_x86_64_tls_transition): Likewise.
(elf_x86_64_scan_relocs): Handle R_X86_64_CODE_6_GOTTPOFF.
Issue an error for R_X86_64_CODE_5_GOTPCRELX,
R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC,
R_X86_64_CODE_6_GOTPCRELX and R_X86_64_CODE_6_GOTPC32_TLSDESC.
(elf_x86_64_relocate_section): Handle R_X86_64_CODE_6_GOTTPOFF.
* reloc.c (bfd_reloc_code_real): Add
BFD_RELOC_X86_64_CODE_5_GOTPCRELX,
BFD_RELOC_X86_64_CODE_5_GOTTPOFF,
BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC,
BFD_RELOC_X86_64_CODE_6_GOTPCRELX,
BFD_RELOC_X86_64_CODE_6_GOTTPOFF and
BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
elfcpp/
* x86_64.h (R_X86_64_CODE_5_GOTPCRELX): New.
(R_X86_64_CODE_5_GOTTPOFF): Likewise.
(R_X86_64_CODE_5_GOTPC32_TLSDESC): Likewise.
(R_X86_64_CODE_6_GOTPCRELX): Likewise.
(R_X86_64_CODE_6_GOTTPOFF): Likewise.
(R_X86_64_CODE_6_GOTPC32_TLSDESC): Likewise.
gas/
* config/tc-i386.c (tc_i386_fix_adjustable): Handle
BFD_RELOC_X86_64_CODE_6_GOTTPOFF.
(md_assemble): Don't check BFD_RELOC_X86_64_CODE_4_GOTTPOFF.
Allow "add %reg1, foo@gottpoff(%rip), %reg2".
(output_disp): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. Rewrite
setting fx_tcbitX bits for BFD_RELOC_X86_64_GOTTPOFF,
BFD_RELOC_X86_64_GOTPC32_TLSDESC and BFD_RELOC_32_PCREL.
(md_apply_fix): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF.
(i386_validate_fix): Rewrite fx_tcbitX bit checking for
BFD_RELOC_X86_64_GOTTPOFF, BFD_RELOC_X86_64_GOTPC32_TLSDESC and
BFD_RELOC_32_PCREL.
(tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF.
* testsuite/gas/i386/x86-64-gottpoff.d: Updated.
* testsuite/gas/i386/x86-64-gottpoff.s: Add tests for
"add %reg1, foo@gottpoff(%rip), %reg2" and
"add foo@gottpoff(%rip), %reg, %reg2".
gold/
* x86_64.cc (Target_x86_64::optimize_tls_reloc): Handle
R_X86_64_CODE_6_GOTTPOFF.
(Target_x86_64::Scan::get_reference_flags): Likewise.
(Target_x86_64::Scan::local): Likewise.
(Target_x86_64::Scan::global): Likewise.
(Target_x86_64::Relocate::relocate): Likewise.
(Target_x86_64::Relocate::relocate_tls): Likewise.
(Target_x86_64::Relocate::tls_ie_to_le): Handle.
R_X86_64_CODE_6_GOTTPOFF.
* testsuite/x86_64_ie_to_le.s: Add tests for
"add %reg1, foo@gottpoff(%rip), %reg2" and
"add foo@gottpoff(%rip), %reg, %reg2".
* testsuite/x86_64_ie_to_le.sh: Updated.
include/
* elf/x86-64.h (elf_x86_64_reloc_type): Add
R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF,
R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX,
R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC.
ld/
* testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_6_GOTTPOFF
tests.
* testsuite/ld-x86-64/tlsbindesc.d: Updated.
* testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
(cherry picked from commit 5bc71c2a6b8efb27089baa1fecded82be4f550a7)
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Adds two new external authors to etc/update-copyright.py to cover
bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then
updates copyright messages as follows:
1) Update cgen/utils.scm emitted copyrights.
2) Run "etc/update-copyright.py --this-year" with an extra external
author I haven't committed, 'Kalray SA.', to cover gas testsuite
files (which should have their copyright message removed).
3) Build with --enable-maintainer-mode --enable-cgen-maint=yes.
4) Check out */po/*.pot which we don't update frequently.
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Handle R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC.
Convert
add name@gottpoff(%rip), %reg
mov name@gottpoff(%rip), %reg
to
add $name@tpoff, %reg
mov $name@tpoff, %reg
and
lea name@tlsdesc(%rip), %reg
to
mov $name@tpoff, %reg
mov name@gottpoff(%rip), %reg
if the instruction is encoded with the REX2 prefix when possible.
elfcpp/
* x86_64.h (R_X86_64_CODE_4_GOTTPOFF): New.
(R_X86_64_CODE_4_GOTPC32_TLSDESC): Likewise.
gold/
* x86_64.cc (Target_x86_64::optimize_tls_reloc): Handle
R_X86_64_CODE_4_GOTPC32_TLSDESC and R_X86_64_CODE_4_GOTTPOFF.
(Target_x86_64::Scan::get_reference_flags): Likewise.
(Target_x86_64::Scan::local): Likewise.
(Target_x86_64::Scan::global): Likewise.
(Target_x86_64::Relocate::relocate): Likewise.
(Target_x86_64::Relocate::relocate_tls): Likewise.
(Target_x86_64::Relocate::tls_desc_gd_to_ie): Handle
R_X86_64_CODE_4_GOTPC32_TLSDESC.
(Target_x86_64::Relocate::tls_desc_gd_to_le): Likewise.
(Target_x86_64::Relocate::tls_ie_to_le): Handle.
R_X86_64_CODE_4_GOTTPOFF.
* testsuite/Makefile.am: Add x86_64_ie_to_le test.
* testsuite/Makefile.in: Regenerated.
* testsuite/x86_64_gd_to_le.s: Add R_X86_64_CODE_4_GOTPC32_TLSDESC
test.
* testsuite/x86_64_gd_to_le.sh: Check GDesc to LE conversion.
* testsuite/x86_64_ie_to_le.s: New file.
* testsuite/x86_64_ie_to_le.sh: Likewise.
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Handle R_X86_64_CODE_4_GOTPCRELX and convert
mov name@GOTPCREL(%rip), %r31
to
lea name@GOTPCREL(%rip), %r31
if the instruction is encoded with the REX2 prefix when possible.
elfcpp/
* x86_64.h (R_X86_64_CODE_4_GOTPCRELX): New.
gold/
* x86_64.cc (Target_x86_64::can_convert_mov_to_lea): Handle
R_X86_64_CODE_4_GOTPCRELX.
(Target_x86_64::Scan::get_reference_flags): Likewise.
(Target_x86_64::Scan::local): Likewise.
(Target_x86_64::Scan::possible_function_pointer_reloc): Likewise.
(Target_x86_64::Scan::global): Likewise.
(Target_x86_64::Relocate::relocate): Likewise.
* testsuite/x86_64_mov_to_lea1.s: Add a test for
R_X86_64_CODE_4_GOTPCRELX.
* testsuite/x86_64_mov_to_lea2.s: Likewise.
* testsuite/x86_64_mov_to_lea3.s: Likewise.
* testsuite/x86_64_mov_to_lea4.s: Likewise.
* testsuite/x86_64_mov_to_lea5.s: Likewise.
* testsuite/x86_64_mov_to_lea.sh: Updated.
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The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
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This feature is enabled if config/zstd.m4 uses zstd.
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Following the same format as the implementation in ld:
9e2bb0cb5e74aed4158f08495534922d7108f928
Generate a .note.package FDO package metadata ELF note, following
the spec: https://systemd.io/ELF_PACKAGE_METADATA/
If the jansson library is available at build time (and it is explicitly
enabled), link ld to it, and use it to validate that the input is
correct JSON, to avoid writing garbage to the file. The
configure option --enable-jansson has to be used to explicitly enable
it (error out when not found). This allows bootstrappers (or others who
are not interested) to seamlessly skip it without issues.
elfcpp/
* elfcpp.h: Add FDO_PACKAGING_METADATA note type.
gold/
* Makefile.am: Add jansson flags and libraries.
* configure.ac: Check for jansson library.
* layout.cc (Layout::create_notes): Call create_package_metadata().
(Layout::create_package_metadata): New function.
* layout.h (Layout::create_package_metadata): New function.
(Layout::package_metadata_note_): New data member.
* options.h (class General_options): Add --package-metadata option.
* testsuite/Makefile.am (object_unittest): Add jansson libraries.
(binary_unittest): Likewise.
(leb128_unittest): Likewise.
(overflow_unittest): Likewise.
(package_metadata_test): New test.
* testsuite/package_metadata_main.c: New test source.
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The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.
The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
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Gold version of commit 7aba54da42.
elfcpp/
* powerpc.h (R_PPC64_REL24_P9NOTOC): Define.
gold/
* powerpc.cc (Target_powerpc::maybe_skip_tls_get_addr_call,
is_branch_reloc, max_branch_delta): Handle R_PPC64_REL24_P9NOTOC.
(Target_powerpc::Branch_info::make_stub): Likewise.
(struct Plt_stub_ent): Add p9notoc_, p9off_, tsize_.
(struct Branch_stub_ent): Add p9notoc_, p9off_.
(Stub_table::add_plt_call_entry): Handle R_PPC64_REL24_P9NOTOC.
(Stub_table::add_long_branch_entry): Likewise.
(Stub_table::add_eh_frame): Likewise.
(Stub_table::plt_call_size): Return aligned size. Adjust callers.
Handle p9notoc_ sizing.
(Stub_table::do_write): Write out p9notoc_ stubs.
(Target_powerpc::Scan::get_reference_flags, local, global):
Handle R_PPC64_REL24_P9NOTOC.
(Target_powerpc::Relocate::relocate): Likewise.
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Update also include:
+ New value of Tag_CPU_arch EABI attribute (22) is added.
+ Updated missing Tag_CPU_arch EABI attributes.
+ Updated how we combine archs 'v4t_plus_v6_m' as this mechanism
have to handle new Armv9 as well.
Regression tested on `arm-none-eabi` cross Binutils and no issues.
bfd/
* archures.c: Define bfd_mach_arm_9.
* bfd-in2.h (bfd_mach_arm_9): Define bfd_mach_arm_9.
* cpu-arm.c: Add 'armv9-a' option to -march.
* elf32-arm.c (using_thumb2_bl): Update assert check.
(arch_has_arm_nop): Add TAG_CPU_ARCH_V9.
(bfd_arm_get_mach_from_attributes): Add case for TAG_CPU_ARCH_V9.
Update assert.
(tag_cpu_arch_combine): Updated table.
(v9): New table..
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Update with
elfcpp/
* arm.h: Update TAG_CPU_ARCH_ enums with correct values.
gas/
* NEWS: Update docs.
* config/tc-arm.c (get_aeabi_cpu_arch_from_fset): Return Armv9-a
for -amarch=all.
(aeabi_set_public_attributes): Update assert.
* doc/c-arm.texi: Update docs.
* testsuite/gas/arm/armv9-a_arch.d: New test.
* testsuite/gas/arm/attr-march-all.d: Update test with v9.
include/
* elf/arm.h Update TAG_CPU_ARCH_ defines with correct values.
* opcode/arm.h (ARM_EXT3_V9A): New macro.
(ARM_ARCH_NONE): Updated with arm_feature_set.core size.
(FPU_NONE): Updated.
(ARM_ANY): Updated.
(ARM_ARCH_UNKNOWN): New macro.
(ARM_FEATURE_LOW): Updated.
(ARM_FEATURE_CORE): Updated.
(ARM_FEATURE_CORE_LOW): Updated.
(ARM_FEATURE_CORE_HIGH): Updated.
(ARM_FEATURE_COPROC): Updated.
(ARM_FEATURE): Updated.
(ARM_FEATURE_ALL): New macro.
opcodes/
* arm-dis.c (select_arm_features): Support bfd_mach_arm_9.
Also Update bfd_mach_arm_unknown to use new macro ARM_ARCH_UNKNOWN.
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bfd/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add
'Tag_PACRET_use' case.
binutils/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* readelf.c (arm_attr_tag_PAC_extension): Declare.
(arm_attr_public_tags): Add 'PAC_extension' lookup.
elfcpp/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* arm.h: Define 'Tag_PACRET_use' enum.
gas/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (arm_convert_symbolic_attribute): Add
'Tag_PACRET_use' to the attribute_table.
include/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf/arm.h (elf_arm_reloc_type): Add 'Tag_PACRET_use'.
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bfd/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add
'Tag_BTI_use' case.
binutils/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* readelf.c (arm_attr_tag_PAC_extension): Declare.
(arm_attr_public_tags): Add 'PAC_extension' lookup.
elfcpp/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* arm.h: Define 'Tag_BTI_use' enum.
gas/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (arm_convert_symbolic_attribute): Add
'Tag_BTI_use' to the attribute_table.
include/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf/arm.h (elf_arm_reloc_type): Add 'Tag_BTI_use'.
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bfd/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add
'Tag_BTI_extension' case.
binutils/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* readelf.c (arm_attr_tag_PAC_extension): Declare.
(arm_attr_public_tags): Add 'PAC_extension' lookup.
elfcpp/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* arm.h: Define 'Tag_BTI_extension' enum.
gas/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (arm_convert_symbolic_attribute): Add
'Tag_BTI_extension' to the attribute_table.
include/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf/arm.h (elf_arm_reloc_type): Add 'Tag_BTI_extension'.
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bfd/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add
'Tag_PAC_extension' case.
binutils/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* readelf.c (arm_attr_tag_PAC_extension): Declare.
(arm_attr_public_tags): Add 'PAC_extension' lookup.
elfcpp/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* arm.h: Define 'Tag_PAC_extension' enum.
gas/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (arm_convert_symbolic_attribute): Add
'Tag_PAC_extension' to the attribute_table.
include/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf/arm.h (elf_arm_reloc_type): Add 'Tag_PAC_extension'.
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elfcpp/
PR gold/27246
* dwarf.h (enum DW_LNCT): Add line number table content type codes.
(enum DW_LINE_OPS): Reformat.
(enum DW_LINE_EXTENDED_OPS): Reformat.
(enum DW_CHILDREN): Reformat.
(enum DW_RLE): Add range list entry types.
(enum DW_SECT): Update values for DWARF 5.
gold/
PR gold/27246
* dwarf_reader.cc (Dwarf_abbrev_table::do_get_abbrev): Handle
DW_FORM_implicit_const.
(Dwarf_ranges_table::read_ranges_table): Add version parameter;
Adjust all callers. Look for .debug_rnglists section if DWARF 5.
(Dwarf_ranges_table::read_range_list_v5): New method.
(Dwarf_die::read_attributes): Handle new DWARF 5 DW_FORM codes.
(Dwarf_die::skip_attributes): Likewise.
(Dwarf_info_reader::do_parse): Support DWARF 5 unit header format.
(Dwarf_info_reader::read_3bytes_from_pointer): New method.
(Sized_dwarf_line_info::Sized_dwarf_line_info): Initialize
str_buffer_, str_buffer_start, reloc_map_, line_number_map_.
Look for .debug_line_str section.
(Sized_dwarf_line_info::read_header_prolog): Support DWARF 5 prolog.
(Sized_dwarf_line_info::read_header_tables): Rename to...
(Sized_dwarf_line_info::read_header_tables_v2): ... this.
(Sized_dwarf_line_info::read_header_tables_v5): New method.
(Sized_dwarf_line_info::process_one_opcode): Insert missing "this->".
Change advance_line to signed int64_t.
(Sized_dwarf_line_info::read_lines): Add endptr parameter; adjust
callers. Insert missing "this->".
(Sized_dwarf_line_info::read_line_mappings): Support DWARF 5.
(Sized_dwarf_line_info::do_addr2line): Add debug code.
* dwarf_reader.h (Dwarf_abbrev_table::Attribute): Add implicit_const
field. Adjust constructor.
(Dwarf_abbrev_table::add_sttribute): Add implicit_const parameter.
(Dwarf_ranges_table::read_ranges_table): Add version parameter.
(Dwarf_ranges_table::read_range_list_v5): New method.
(Dwarf_die): Remove unused attr_off field.
(Dwarf_info_reader::Dwarf_info_reader): Initialize unit_type_ field.
(Dwarf_info_reader::is_type_unit): New method.
(Dwarf_info_reader::read_3bytes_from_pointer): New method.
(Dwarf_info_reader::read_range_list): Call read_range_list_v5 for
DWARF 5 range lists.
(Dwarf_info_reader::is_type_unit_): Remove.
(Dwarf_info_reader::unit_type_): New field.
(Sized_dwarf_line_info::~Sized_dwarf_line_info): Delete
str_buffer_start_.
(Sized_dwarf_line_info::read_header_tables): Rename to...
(Sized_dwarf_line_info::read_header_tables_v2): ... this.
(Sized_dwarf_line_info::read_header_tables_v5): New method.
(Sized_dwarf_line_info::read_lines): Add endptr parameter.
(Sized_dwarf_line_info::Dwarf_line_infoHeader): Add address_size field.
(Sized_dwarf_line_info::str_buffer_): New field.
(Sized_dwarf_line_info::str_buffer_end_): New field.
(Sized_dwarf_line_info::str_buffer_start_): New field.
(Sized_dwarf_line_info::end_of_header_length_): New field.
(Sized_dwarf_line_info::end_of_unit_): New field.
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Add accessor methods to elfcpp::Ehdr class for EI_OSABI and EI_ABIVERSION;
use those to simplify initialization of Osabi class and eliminate the need
to template the class.
elfcpp/
* elfcpp.h (class Ehdr): Add get_ei_osabi and get_ei_abiversion methods.
gold/
* dwp.cc (class Dwo_file): Use new Ehdr::get_ei_osabi and
get_ei_abiversion methods.
* incremental.cc (make_sized_incremental_binary): Likewise.
* object.cc (Sized_relobj_file::Sized_relobj_file): Likewise.
(make_elf_sized_object): Likewise.
* object.h (class Osabi): Make the class untemplated.
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* elfcpp.h (enum DT): New enum member DT_GNU_FLAGS_1.
(enum DF_GNU_1): New enum DF_GNU_1 containing DF_GNU_1_UNIQUE.
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GNU/FreBSD ELFOSABIs.
2020-12-14 H.J. Lu <hjl.tools@gmail.com>
Cary Coutant <ccoutant@gmail.com>
elfcpp/
PR gold/27039
* elfcpp.h (SHF): Add SHF_GNU_RETAIN.
gold/
PR gold/27039
* layout.cc (Layout::layout): Strip SHF_GNU_RETAIN.
* object.cc (Sized_relobj_file::Sized_relobj_file): Initialize osabi_.
(Sized_relobj_file::do_layout): Keep SHF_GNU_RETAIN sections for
GNU/FreBSD ELFOSABIs.
* object.h (Osabi) New class.
(Sized_relobj_file): Add osabi() and osabi_.
* testsuite/Makefile.am (check_SCRIPTS): Add retain.sh.
(check_DATA): Add retain_1.out retain_2.out.
(MOSTLYCLEANFILES): Add retain_1 retain_2.
(retain_1.out): New target.
(retain_1): Likewise.
(retain_1.o): Likewise.
(retain_2.out): Likewise.
(retain_2): Likewise.
(retain_2.o): Likewise.
* testsuite/Makefile.in: Regenerate.
* testsuite/retain.sh: New file.
* testsuite/retain_1.s: Likewise.
* testsuite/retain_2.s: Likewise.
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This patch updates GNU_PROPERTY_X86_XXX macros for gold:
1. GNU_PROPERTY_X86_UINT32_AND_XXX: A 4-byte unsigned integer property.
A bit is set if it is set in all relocatable inputs:
#define GNU_PROPERTY_X86_UINT32_AND_LO 0xc0000002
#define GNU_PROPERTY_X86_UINT32_AND_HI 0xc0007fff
2. GNU_PROPERTY_X86_UINT32_OR_XXX: A 4-byte unsigned integer property.
A bit is set if it is set in any relocatable inputs:
#define GNU_PROPERTY_X86_UINT32_OR_LO 0xc0008000
#define GNU_PROPERTY_X86_UINT32_OR_HI 0xc000ffff
3. GNU_PROPERTY_X86_UINT32_OR_AND_XXX: A 4-byte unsigned integer property.
A bit is set if it is set in any relocatable inputs and the property is
present in all relocatable inputs:
#define GNU_PROPERTY_X86_UINT32_OR_AND_LO 0xc0010000
#define GNU_PROPERTY_X86_UINT32_OR_AND_HI 0xc0017fff
4. GNU_PROPERTY_X86_FEATURE_2_NEEDED, GNU_PROPERTY_X86_FEATURE_2_USED
and GNU_PROPERTY_X86_FEATURE_2_XXX bits.
GNU_PROPERTY_X86_FEATURE_1_AND is unchanged. GNU_PROPERTY_X86_ISA_1_USED
and GNU_PROPERTY_X86_ISA_1_NEEDED are updated to better support targeted
processors since GNU_PROPERTY_X86_ISA_1_?86 aren't isn't very useful.
A new set of GNU_PROPERTY_X86_ISA_1_XXX bits are defined. The previous
GNU_PROPERTY_X86_ISA_1_XXX macros are deprecated and renamed to
GNU_PROPERTY_X86_COMPAT_ISA_1_XXX and GNU_PROPERTY_X86_COMPAT_2_ISA_1_XXX.
elfcpp/
* elfcpp.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ...
(GNU_PROPERTY_X86_COMPAT_ISA_1_USED): This.
(GNU_PROPERTY_X86_ISA_1_NEEDED): Renamed to ...
(GNU_PROPERTY_X86_COMPAT_ISA_1_NEEDED): This.
(GNU_PROPERTY_X86_UINT32_AND_LO): New.
(GNU_PROPERTY_X86_UINT32_AND_HI): Likewise.
(GNU_PROPERTY_X86_UINT32_OR_LO): Likewise.
(GNU_PROPERTY_X86_UINT32_OR_HI): Likewise.
(GNU_PROPERTY_X86_UINT32_OR_AND_LO): Likewise.
(GNU_PROPERTY_X86_UINT32_OR_AND_HI): Likewise.
(GNU_PROPERTY_X86_COMPAT_2_ISA_1_NEEDED): New.
(GNU_PROPERTY_X86_COMPAT_2_ISA_1_NEEDED): Likewise.
(GNU_PROPERTY_X86_FEATURE_1_AND): Updated to
(GNU_PROPERTY_X86_UINT32_AND_LO + 0).
(GNU_PROPERTY_X86_ISA_1_NEEDED): New. Defined to
GNU_PROPERTY_X86_UINT32_OR_LO + 2.
(GNU_PROPERTY_X86_FEATURE_2_NEEDED): New. Defined to
(GNU_PROPERTY_X86_UINT32_OR_LO + 1).
(GNU_PROPERTY_X86_ISA_1_USED): New. Defined to
GNU_PROPERTY_X86_UINT32_OR_AND_LO + 2.
(GNU_PROPERTY_X86_FEATURE_2_USED): New. Defined to
(GNU_PROPERTY_X86_UINT32_OR_AND_LO + 1).
gold/
* x86_64.cc (Target_x86_64::Target_x86_64): Initialize
feature_2_used_, feature_2_needed_ and object_feature_2_used_.
(Target_x86_64::feature_2_used_): New data member.
(Target_x86_64::feature_2_needed_): Likewise.
(Target_x86_64::object_isa_1_used_): Likewise.
(Target_x86_64::record_gnu_property): Support
GNU_PROPERTY_X86_COMPAT_ISA_1_USED,
GNU_PROPERTY_X86_COMPAT_ISA_1_NEEDED,
GNU_PROPERTY_X86_COMPAT_2_ISA_1_USED,
GNU_PROPERTY_X86_COMPAT_2_ISA_1_NEEDED,
GNU_PROPERTY_X86_FEATURE_2_USED and
GNU_PROPERTY_X86_FEATURE_2_NEEDED.
(Target_x86_64::merge_gnu_properties): Merge FEATURE_2_USED bits.
Initialize object_feature_2_used_.
(Target_x86_64::do_finalize_gnu_properties): Support
GNU_PROPERTY_X86_FEATURE_2_USED and
GNU_PROPERTY_X86_FEATURE_2_NEEDED.
* testsuite/gnu_property_a.S (GNU_PROPERTY_X86_ISA_1_USED): Set
to 0xc0010002.
(GNU_PROPERTY_X86_ISA_1_NEEDED): Set to 0xc0008002.
* testsuite/gnu_property_b.S (GNU_PROPERTY_X86_ISA_1_USED): Set
to 0xc0010002.
(GNU_PROPERTY_X86_ISA_1_NEEDED): Set to 0xc0008002.
* testsuite/gnu_property_c.S (GNU_PROPERTY_X86_ISA_1_USED): Set
to 0xc0010002.
(GNU_PROPERTY_X86_ISA_1_NEEDED): Set to 0xc0008002.
* testsuite/gnu_property_test.sh: Updated.
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* dwarf.h (DW_FIRST_UT, DW_UT, DW_END_UT): Define.
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bfd
* elf32-csky.c (csky_archs): Fix arch names.
(csky_find_arch_with_name): New.
(elf32_csky_merge_attributes): New.
(csky_elf_merge_private_bfd_data): Add process of merge
attribute section.
(elf32_csky_obj_attrs_arg_type): New.
(elf32_csky_obj_attrs_handle_unknown): New.
(elf_backend_obj_attrs_vendor): Define.
(elf_backend_obj_attrs_section): Define.
(elf_backend_obj_attrs_arg_type): Define.
(elf_backend_obj_attrs_section_type): Define.
binutils/
* readelf.c (get_csky_section_type_name): New.
(get_section_type_name): Add handler for CSKY.
(display_csky_attribute): New.
(process_arch_specific): Add handler for CSKY.
* testsuite/binutils-all/strip-3.d: Remove .csky.attributes
section.
elfcpp/
* elfcpp.h (enum SHT): New enum SHT_CSKY_ATTRIBUTES.
gas/
* gas/config/tc-csky.c (md_begin): Set attributes.
(isa_flag): Change type to unsigned 64 bits.
(struct csky_cpu_info): Likewise.
(struct csky_macro_info): Likewise.
(set_csky_attribute): New.
* testsuite/gas/csky/802j.d: Ignore .csky.attributes section.
* testsuite/gas/csky/all.d: Likewise.
* testsuite/gas/csky/bsr1.d: Likewise.
* testsuite/gas/csky/csky_vdsp.d: Likewise.
* testsuite/gas/csky/cskyv2_all.d: Likewise.
* testsuite/gas/csky/cskyv2_ck803r2.d: Likewise.
* testsuite/gas/csky/cskyv2_ck860.d: Likewise.
* testsuite/gas/csky/cskyv2_dsp.d: Likewise.
* testsuite/gas/csky/cskyv2_elrw.d: Likewise.
* testsuite/gas/csky/cskyv2_float.d: Likewise.
* testsuite/gas/csky/enhance_dsp.d: Likewise.
* testsuite/gas/csky/java.d: Likewise.
* testsuite/gas/csky/v1_float.d: Likewise.
* testsuite/gas/csky/v2_float_part1.d: Likewise.
* testsuite/gas/csky/v2_float_part2.d: Likewise.
* testsuite/gas/csky/v2_tls_gd.d: Likewise.
* testsuite/gas/csky/v2_tls_ie.d: Likewise.
* testsuite/gas/csky/v2_tls_ld.d: Likewise.
* testsuite/gas/csky/v2_tls_le.d: Likewise.
* testsuite/gas/elf/elf.exp: Add handler for CSKY.
* testsuite/gas/elf/section2.e-csky: New.
include/
* elf/csky.h (SHT_CSKY_ATTRIBUTES): Define.
(Tag_CSKY_ARCH_NAME): New enum constant.
(Tag_CSKY_CPU_NAME): Likewise.
(Tag_CSKY_ISA_FLAGS): Likewise.
(Tag_CSKY_DSP_VERSION): Likewise.
(Tag_CSKY_VDSP_VERSION): Likewise.
(Tag_CSKY_FPU_VERSION): Likewise.
(Tag_CSKY_FPU_ABI): Likewise.
(Tag_CSKY_FPU_ROUNDING): Likewise.
(Tag_CSKY_FPU_DENORMAL): Likewise.
(Tag_CSKY_FPU_Exception): Likewise.
(Tag_CSKY_FPU_NUMBER_MODULE): Likewise.
(Tag_CSKY_FPU_HARDFP): Likewise.
(Tag_CSKY_MAX): Likewise.
(VAL_CSKY_DSP_VERSION_EXTENSION): Likewise.
(VAL_CSKY_DSP_VERSION_2): Likewise.
(VAL_CSKY_VDSP_VERSION_1): Likewise.
(VAL_CSKY_VDSP_VERSION_2): Likewise.
(VAL_CSKY_FPU_ABI_SOFT): Likewise.
(VAL_CSKY_FPU_ABI_SOFTFP): Likewise.
(VAL_CSKY_FPU_ABI_HARD): Likewise.
(VAL_CSKY_FPU_HARDFP_HALF): Likewise.
(VAL_CSKY_FPU_HARDFP_SINGLE): Likewise.
(VAL_CSKY_FPU_HARDFP_DOUBLE): Likewise.
* opcode/csky.h (CSKY_ISA_VDSP_V2): Define.
CSKYV1_ISA_E1: Change to long constant type.
CSKYV2_ISA_E1: Likewise.
CSKYV2_ISA_1E2: Likewise.
CSKYV2_ISA_2E3: Likewise.
CSKYV2_ISA_3E7: Likewise.
CSKYV2_ISA_7E10: Likewise.
CSKYV2_ISA_3E3R1: Likewise.
CSKYV2_ISA_3E3R2: Likewise.
CSKYV2_ISA_10E60: Likewise.
CSKY_ISA_TRUST: Likewise.
CSKY_ISA_CACHE: Likewise.
CSKY_ISA_NVIC: Likewise.
CSKY_ISA_CP: Likewise.
CSKY_ISA_MP: Likewise.
CSKY_ISA_MP_1E2: Likewise.
CSKY_ISA_JAVA: Likewise.
CSKY_ISA_MAC: Likewise.
CSKY_ISA_MAC_DSP: Likewise.
CSKY_ISA_DSP: Likewise.
CSKY_ISA_DSP_1E2: Likewise.
CSKY_ISA_DSP_ENHANCE: Likewise.
CSKY_ISA_FLOAT_E1: Likewise.
CSKY_ISA_FLOAT_1E2: Likewise.
CSKY_ISA_FLOAT_1E3: Likewise.
CSKY_ISA_FLOAT_3E4: Likewise.
CSKY_ISA_VDSP: Likewise.
ld/
* emulparams/cskyelf.sh: Support attribute section.
* testsuite/ld-csky/tls-le-v1.d: Match .csky.attributes section.
* ld/testsuite/ld-csky/tls-le.d: Likewise.
* testsuite/ld-elf/non-contiguous.ld: Ignore .csky.attributes
section.
opcodes/
* csky-dis.c (CSKY_DEFAULT_ISA): Define.
(csky_dis_info): Add member isa.
(csky_find_inst_info): Skip instructions that do not belong to
current CPU.
(csky_get_disassembler): Get infomation from attribute section.
(print_insn_csky): Set defualt ISA flag.
* csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
* csky-opc.h (struct csky_opcode): Change isa_flag16 and
isa_flag32'type to unsigned 64 bits.
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At least one C library (uclibc-ng) defines some of these only when
the compiler is GCC. We might as well test for all three cases and
handle any of them being missing.
Very similar code exists in libctf and split between elfcpp and gold:
fix both.
(Also sync up elfcpp with a change made to libctf swap.h a few months
ago: since there is no out-of-line definition of the bswap replacements,
they should be declared static inline, not just inline, to prevent the
linker generating out-of-line references to them.)
PR libctf/25120
libctf/
* configure.ac: Check for bswap_16, bswap_32, and bswap_64 decls.
* swap.h (bswap_16): Do not assume that presence of <byteswap.h>
means this is declared.
(bswap_32): Likewise.
(bswap_64): Likewise.
(bswap_identity_64): Remove, unused.
* configure: Regenerated.
* config.h.in: Likewise.
gold/
* configure.ac: Check for bswap_16, bswap_32, and bswap_64 decls.
* configure: Regenerated.
* config.h.in: Likewise.
elfcpp/
* elfcpp_swap.h (bswap_16): Do not assume that presence of
<byteswap.h> means this is declared. Make static inline, matching
recent change to libctf, since there is no non-inline definition
of these functions.
(bswap_32): Likewise.
(bswap_64): Likewise.
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PR gold/26039
* layout.cc (Layout::finish_dynamic_section): Set DF_1_PIE.
elfcpp/
* elfcpp.h (enum DF_1): New enum member DF_1_PIE.
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These relocations should have had REL in their names, to reflect the
fact that they are pc-relative. Fix that now by adding _PCREL.
I've added some back-compatibility code to support anyone using
.reloc with the old relocations.
include/
* elf/ppc64.h (elf_ppc64_reloc_type): Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
bfd/
* reloc.c: Rename
BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34,
BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34,
BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34,
BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34.
* elf64-ppc.c: Update throughout for reloc renaming.
(ppc64_elf_reloc_name_lookup): Handle old reloc names.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c: Update throughout for reloc renaming.
elfcpp/
* powerpc.h: Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
gold/
* powerpc.cc: Update throughout for reloc renaming.
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Add the ChangeLog entry.
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Gold version of git commit c213164ad2.
elfcpp/
* powerpc.h (R_PPC64_TPREL34, R_PPC64_DTPREL34),
(R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34),
(R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define.
gold/
* powerpc.cc (Target_powerpc::Scan::get_reference_flags): Set
flags for new relocations, and some missing older relocs.
(Target_powerpc::Scan::local): Handle new pcrel tls relocs.
Call set_has_static_tls for tprel relocs.
(Target_powerpc::Scan::global): Likewise.
(Target_powerpc::Relocate::relocate): Handle new pcrel tls relocs.
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Also use pc-relative instructions for notoc stubs.
elfcpp/
* powerpc.h (R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO),
(R_PPC64_D34_HI30, R_PPC64_D34_HA30, R_PPC64_PCREL34),
(R_PPC64_GOT_PCREL34, R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC),
(R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34),
(R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34),
(R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34),
(R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34),
(R_PPC64_D28, R_PPC64_PCREL28): Define.
gold/
* powerpc.cc (Target_powerpc): Add powerxx_stubs_ and accessor
functions.
(Target_powerpc::maybe_skip_tls_get_addr_call): Handle PLT_PCREL34
and PLT_PCREL34_NOTOC relocs.
(Powerpc_relocate_functions): Add addr34, addr34_hi, addr34_ha,
addr28, addr16_higher34, addr16_highera34, addr16_highest34,
addr16_highest34a functions.
(li_11_0, ori_11_11_0, sldi_11_11_34): Define.
(paddi_12_pc, pld_12_pc, pnop): Define.
(d34, ha34): New inline functions.
(Stub_table::add_plt_call_entry): Handle powerxx_stubs.
(Stub_table::add_eh_frame): Likewise.
(build_powerxx_offset): New function.
(Stub_table::plt_call_size): Handle powerxx_stubs.
(Stub_table::branch_stub_size): Likewise.
(Stub_table::do_write): Likewise.
(Target_powerpc::Scan::get_reference_flags): Handle new relocs.
(Target_powerpc::Scan::reloc_needs_plt_for_ifunc: Likewise.
(Target_powerpc::Scan::local, global, relocate): Likewise.
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Calls from notoc functions via the PLT need different stubs. Even
calls to local functions requiring a valid toc pointer must go via a
stub. This patch provides the support in gold.
elfcpp/
* powerpc.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC): Define.
gold/
* powerpc.cc (Target_powerpc::maybe_skip_tls_get_addr_call): Handle
notoc calls.
(is_branch_reloc): Template on size. Return true for REL24_NOTOC.
Update all callers.
(max_branch_delta): Likewise.
(Target_powerpc::Branch_info::make_stub): Add a stub for notoc
calls to functions needing a valid toc pointer.
(Target_powerpc::do_relax): Layout stubs again if any need resize.
(add_12_11_12, addi_12_11, addis_12_11, ldx_12_11_12, ori_12_12_0),
(oris_12_12_0, sldi_12_12_32): Define.
(Stub_table::Plt_stub_ent): Add notoc_ and iter_ fields.
(Stub_table::Branch_stub_key, Branch_stub_key_hash): Rename from
Branch_stub_ent and Branch_stub_ent hash. Remove save_res_ from key.
(Stub_table::Branch_stub_ent): New struct.
(class Stub_table): Add need_resize and resizing vars.
(Stub_table::need_resize, branch_size): New accessors.
(Stub_table::set_resizing): New function.
(Stub_table::add_plt_call_entry): Handle notoc calls and resizing
on seeing such or a tocsave stubs after a normal stub using the
same sym.
(Stub_table::add_long_branch_entry): Similarly.
(Stub_table::find_long_branch_entry): Return a Branch_stub_ent*.
(Stub_table::define_stub_syms): Adjust
(Stub_table::build_tls_opt_head, build_tls_opt_tail): New functions.
(build_notoc_offset): New function.
(Stub_table::plt_call_size): Move out of line. Handle notoc calls.
(Stub_table::branch_stub_size): Similarly.
(Stub_table::do_write): Separate loop for ELFv2 stubs, handling
notoc calls. Simplify ELFv1 loop. Output notoc branch stubs.
Use build_tls_opt_head and build_tls_opt_tail.
(Target_powerpc::Scan::get_reference_flags): Handle REL24_NOTOC.
(Target_powerpc::Scan::reloc_needs_plt_for_ifunc): Likewise,
and PLTSEQ_NOTOC and PLTCALL_NOTOC.
(Target_powerpc::Scan::local, global, relocate): Likewise.
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These relocs have been around for quite a while. It's past time gold
supported them.
elfcpp/
* powerpc.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
(R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
(R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
gold/
* powerpc.cc (Target_powerpc::Scan::get_reference_flags): Handle
REL16_HIGH* relocs.
(Target_powerpc::Scan::local): Likewise.
(Target_powerpc::Scan::global): Likewise.
(Target_powerpc::Relocate::relocate): Likewise.
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bfd/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add case for Tag_MVE_arch.
binutils/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* readelf.c (arm_attr_tag_MVE_arch): New array for Tag_MVE_arch values.
(arm_attr_public_tag arm_attr_public_tags): Add case for Tag_MVE_arch.
elfcpp/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* arm.h (Tag_MVE_arch): Define new enum value.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (mve_ext, mve_fp_ext): New features.
(armv8_1m_main_ext_table): Add new extensions.
(aeabi_set_public_attributes): Translate new features to new build attributes.
(arm_convert_symbolic_attribute): Add Tag_MVE_arch.
* doc/c-arm.texi: Document new extensions and new build attribute.
include/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* elf/arm.h (Tag_MVE_arch): Define new enum value.
* opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features.
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R_ARM_THM_BF12
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the BFCSEL instructions which is one of the first
instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF12.
The inconsistency between external R_ARM_THM_BF12 and internal
BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the
immediate and we don't externally.
ChangeLog entries are as follows :
ChangeLog entries are as follows :
*** bfd/ChnageLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF13): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13
and R_ARM_THM_BF12 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13.
*** elfcpp/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF12): New relocation code.
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF13.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
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This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF18.
The inconsistency between external R_ARM_THM_BF18 and internal
BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF19): New
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19
and R_ARM_THM_BF18 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF18): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF19.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
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R_ARM_THM_BF16
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them.
This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16.
The inconsistency between external R_ARM_THM_BF16 and internal
BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17
and R_ARM_THM_BF16 together.
(get_value_helper): New reloc helper.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF16): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF17.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
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