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2014-03-17mach-o: handle lasz load dylib command.Tristan Gingold2-0/+7
bfd/ * mach-o.c (bfd_mach_o_read_dylib): Handle lazy load dylib. (bfd_mach_o_read_command): Ditto. binutils/ * od-macho.c (dump_load_command): Handle lazy load dylib.
2014-03-17daily updateAlan Modra1-1/+1
2014-03-16daily updateAlan Modra1-1/+1
2014-03-15daily updateAlan Modra1-1/+1
2014-03-14Fix build time problem with MingGW hosts, which do not have a strnlen() ↵Nick Clifton5-0/+27
function. 2014-03-13 Meador Inge <meadori@codesourcery.com> * configure.in: Add strnlen to AC_CHECK_DECLS. * config.in: Regenerate. * configure: Regenerate. * sysdep.h (strnlen): Add prototype. * dwarf.c (strnlen): Move prototype ... * sysdep.h (strnlen): ... to here.
2014-03-14Fix overflow handling of VLE_SDA21Alan Modra2-5/+12
bfd/ * elf32-ppc.c (ppc_elf_relocate_section): Correct overflow handling for VLE_SDA21 relocs. ld/testsuite/ * ld-powerpc/vle.ld: Place .PPC.EMB.sdata0 within 32k of 0. * ld-powerpc/vle-reloc-3.d: Update.
2014-03-14daily updateAlan Modra1-1/+1
2014-03-13Add pe/x86_64 bigobj file format.Tristan Gingold14-15/+368
bfd/ * peicode.h (pe_ILF_object_p): Adjust, as the version number has been read. (pe_bfd_object_p): Also read version number to detect ILF. * pe-x86_64.c (COFF_WITH_PE_BIGOBJ): Define. (x86_64pe_bigobj_vec): Define * coffcode.h (bfd_coff_backend_data): Add _bfd_coff_max_nscns field. (bfd_coff_max_nscns): New macro. (coff_compute_section_file_positions): Use unsigned int for target_index. Compare with bfd_coff_max_nscns. (bfd_coff_std_swap_table, ticoff0_swap_table, ticoff1_swap_table): Set a value for _bfd_coff_max_nscns. (header_bigobj_classid): New constant. (coff_bigobj_swap_filehdr_in, coff_bigobj_swap_filehdr_out) (coff_bigobj_swap_sym_in, coff_bigobj_swap_sym_out) (coff_bigobj_swap_aux_in, coff_bigobj_swap_aux_out): New functions. (bigobj_swap_table): New table. * libcoff.h: Regenerate. * coff-sh.c (bfd_coff_small_swap_table): Likewise. * coff-alpha.c (alpha_ecoff_backend_data): Add value for _bfd_coff_max_nscns. * coff-mips.c (mips_ecoff_backend_data): Likewise. * coff-rs6000.c (bfd_xcoff_backend_data) (bfd_pmac_xcoff_backend_data): Likewise. * coff64-rs6000.c (bfd_xcoff_backend_data) (bfd_xcoff_aix5_backend_data): Likewise. * targets.c (x86_64pe_bigobj_vec): Declare. * configure.in (x86_64pe_bigobj_vec): New vector. * configure: Regenerate. * config.bfd: Add bigobj object format for Windows targets. gas/ * config/tc-i386.c (use_big_obj): Declare. (OPTION_MBIG_OBJ): Define. (md_longopts): Add -mbig-obj option. (md_parse_option): Handle it. (md_show_usage): Display help for this option. (i386_target_format): Use bigobj for x86-64 if -mbig-obj. * doc/c-i386.texi: Document the option. gas/testsuite/ * gas/pe/big-obj.d, gas/pe/big-obj.s: Add test. * gas/pe/pe.exp: Add test. include/coff/ * pe.h (struct external_ANON_OBJECT_HEADER_BIGOBJ): Declare. (FILHSZ_BIGOBJ): Define. (struct external_SYMBOL_EX): Declare. (SYMENT_BIGOBJ, SYMESZ_BIGOBJ): Define. (union external_AUX_SYMBOL_EX): Declare. (AUXENT_BIGOBJ, AUXESZ_BIGOBJ): Define. * internal.h (struct internal_filehdr): Change type of f_nscns.
2014-03-13daily updateAlan Modra1-1/+1
2014-03-12Prevent the linker from generaing a seg-fault when the user attempts to linkNick Clifton2-0/+9
an ARM ELF binary into an AARCH64 ELF executable. PR ld/16671 * elf32-arm.c (elf32_arm_add_symbol_hook): Check for ARM format before testing for vxworks.
2014-03-12Mention PR gdb/16696 in corresponding ChangeLog entry.Pedro Alves1-0/+1
2014-03-12autoreconfAlan Modra4-2/+10
Regenerate Makefile.in in bfd, binutils, gas, gold, gprof, ld, opcodes. Regenerate gas/config.in.
2014-03-12objcopy/strip ELF program header p_vaddr confusionAlan Modra2-2/+9
copy_elf_program_header has logic to reject non-alloc sections when calculating p_vaddr offset for padding, but blithely assumed the first section in a segment was allocated. PR 16690 * elf.c (copy_elf_program_header): Ignore first section lma if non-alloc.
2014-03-12daily updateAlan Modra1-1/+1
2014-03-11intptr_t type definition neededAlan Modra3-0/+8
coffcode.h uses an intptr_t cast inside an #ifdef RS6000COFF_C, so ensure that intptr_t is defined. We don't see this when cross-compiling from linux due to intptr_t being provided by unistd.h. PR 16686 * coff-rs6000.c: Include stdint.h. * coff64-rs6000.c: Likewise.
2014-03-11daily updateAlan Modra1-1/+1
2014-03-10Remove bfd/ticoff.h (unused)Tristan Gingold2-121/+4
2013-12-03 Tristan Gingold <gingold@adacore.com> * ticoff.h: Remove.
2014-03-10daily updateAlan Modra1-1/+1
2014-03-09daily updateAlan Modra1-1/+1
2014-03-08Better overflow checking for powerpc32 relocationsAlan Modra2-159/+189
Similar to the powerpc64 patch, this improves overflow checking in elf32-ppc.c. Many reloc "howto" entries needed fixes, some just cosmetic. The patch also fixes the R_PPC_VLE_SDA21 reloc application code, which was horribly broken. In fact, it may still be broken since Power ISA 2.07 says e_li behaves as RT <- EXTS(li20 1:4 || li20 5:8 || li20 0 || li20 9:19) where li20 is a field taken from bits 17..20, 11..15, 21..31 of the instruction. Freescale VLEPEM says differently, and I assume correctly, that RT <- EXTS(li20 0:3 || li20 4:8 || li20 9:19) The VLE_SDA21 relocation description matches this too. Now the VLE_SDA21 relocation specifies in the case where e_addi16 is converted to e_li for symbols in .PPC.EMB.sdata0 or .PPC.EMB.sbss0 (no base register), that the field is restricted to 16 bits, with the sign bit being propagated to the top 4 bits. I don't see the sense in restricting the value like this, so have allowed the full 20 bit signed value. This of course is compatible with the reloc description in that values in the 16 bit signed range will result in exactly the same insn field as when the reloc description is followed to the letter. * elf32-ppc.c (ppc_elf_howto_raw): Correct overflow check for many relocations. Correct bitsize and rightshift too for a number of VLE relocs. Describe R_PPC_VLE_SDA21 and R_PPC_VLE_SDA21_LO. Correct dst_mask on R_PPC_VLE_SDA21_LO. (ppc_elf_vle_split16): Tidy, delete unnecessary prototype. (ppc_elf_relocate_section): Modify overflow test for 16-bit fields in instructions to signed/unsigned according to whether the field takes a signed or unsigned value. Tidy vle split16 code. Correct R_PPC_VLE_SDA21 and R_PPC_VLE_SDA21_LO handling.
2014-03-08Better overflow checking for powerpc64 relocationsAlan Modra2-20/+54
R_PPC64_ADDR16 is used in three contexts: - .short data relocation - 16-bit signed insn fields, eg. addi - 16-bit unsigned insn fields, eg. ori In the first case we want to allow both signed and unsigned 16-bit values, the latter two ought to error if the field exceeds the range of values allowed for 16-bit signed and unsigned integers respectively. These conflicting requirements meant that ld had to choose the least restrictive overflow checks, and thus it is possible to construct testcases where an addi field overflows but is not reported by ld. Many relocations dealing with 16-bit insn fields have this problem. What's more, some relocations that are only ever used for signed fields of instructions woodenly copied the lax overflow checking of R_PPC64_ADDR16. bfd/ * elf64-ppc.c (ppc64_elf_howto_raw): Use complain_overflow_signed for R_PPC64_ADDR14, R_PPC64_ADDR14_BRTAKEN, R_PPC64_ADDR14_BRNTAKEN, R_PPC64_SECTOFF, R_PPC64_ADDR16_DS, R_PPC64_SECTOFF_DS, R_PPC64_REL16 entries. Use complain_overflow_dont for R_PPC64_TOC. (ppc64_elf_relocate_section): Modify overflow test for 16-bit fields in instructions to signed/unsigned according to whether the field takes a signed or unsigned value. gold/ * powerpc.cc (Powerpc_relocate_functions::Overflow_check): Add CHECK_UNSIGNED, CHECK_LOW_INSN, CHECK_HIGH_INSN. (Powerpc_relocate_functions::has_overflow_unsigned): New function. (Powerpc_relocate_functions::has_overflow_bitfield, overflowed): Use the above. (Target_powerpc::Relocate::relocate): Correct overflow checking for a number of relocations. Modify overflow test for 16-bit fields in instructions to signed/unsigned according to whether the field takes a signed or unsigned value.
2014-03-08daily updateAlan Modra1-1/+1
2014-03-07AIX 32-bit core loading, high section addresses.Pedro Alves2-2/+7
I noticed GDB was failing to enable threading support for 32-bit AIX cores. I traced it to failure to read variables from libpthreads.a. The issue is that data for that library is loaded at a high address, and bfd is sign extending the section addresses: (gdb) info files Symbols from "/home/palves/crash". Local core dump file: `/home/palves/core', file type aixcoff-rs6000. 0x2ff22000 - 0x2ff23000 is .stack 0x20000000 - 0x200316e0 is .data 0x20000e90 - 0x200016c0 is .data 0xfffffffff0254000 - 0xfffffffff0297920 is .data 0xfffffffff07b46a8 - 0xfffffffff07b47c8 is .data 0xfffffffff0298000 - 0xfffffffff029bfcc is .data 0xfffffffff06dafe0 - 0xfffffffff07b3838 is .data Local exec file: `/home/palves/crash', file type aixcoff-rs6000. Entry point: 0x20001394 0x10000150 - 0x10000e90 is .text 0x20000e90 - 0x2000149c is .data 0x2000149c - 0x200016c0 is .bss 0xd053b124 - 0xd053e15f is .text in /usr/lib/libpthreads.a(shr_comm.o) 0xf0254000 - 0xf0297920 is .data in /usr/lib/libpthreads.a(shr_comm.o) 0xf0254450 - 0xf0297920 is .bss in /usr/lib/libpthreads.a(shr_comm.o) 0xd053a280 - 0xd053aabe is .text in /usr/lib/libcrypt.a(shr.o) 0xf07b46a8 - 0xf07b47c8 is .data in /usr/lib/libcrypt.a(shr.o) 0xf07b47c8 - 0xf07b47c8 is .bss in /usr/lib/libcrypt.a(shr.o) 0xd04fb180 - 0xd053917e is .text in /usr/lib/libpthreads.a(shr_xpg5.o) 0xf0298000 - 0xf029bfcc is .data in /usr/lib/libpthreads.a(shr_xpg5.o) 0xf029bf64 - 0xf029bfcc is .bss in /usr/lib/libpthreads.a(shr_xpg5.o) 0xd0100900 - 0xd04fa39c is .text in /usr/lib/libc.a(shr.o) 0xf06dafe0 - 0xf07b3838 is .data in /usr/lib/libc.a(shr.o) 0xf0751e94 - 0xf07b3838 is .bss in /usr/lib/libc.a(shr.o) Notice: ... 0xfffffffff0298000 - 0xfffffffff029bfcc is .data ... Those are the bfd section start/end addresses. It't not visible here: ... 0xf0298000 - 0xf029bfcc is .data in /usr/lib/libpthreads.a(shr_xpg5.o) ... ... just because GDB trims that number to 32-bit when printing. GDB then fails to find the memory for libpthreads.a variables in the core, and falls back to reading it directly from the executable (which yields the values as originally initialized in the code). E.g.: (gdb) p &__n_pthreads $2 = (<data variable, no debug info> *) 0xf074fda8 <__n_pthreads> (gdb) p __n_pthreads $1 = -1 That should have returned 2 instead of -1. bfd/ 2014-03-07 Pedro Alves <palves@redhat.com> * rs6000-core.c (rs6000coff_core_p): Cast pointers to bfd_vma through ptr_to_uint instead of through long.
2014-03-07daily updateAlan Modra1-1/+1
2014-03-06Patch for PR binutils/16664 which triggers a seg-fault when attempting toNick Clifton2-3/+12
display the contents of a corrupt attribute section. * readelf.c (process_attributes): Add checks for corrupt attribute section names. * elf-attrs.c (_bfd_elf_parse_attributes): Add checks for corrupt attribute section names.
2014-03-06daily updateAlan Modra1-1/+1
2014-03-05Update copyright yearsAlan Modra477-819/+484
2014-03-05Support R_PPC64_ADDR64_LOCALAlan Modra5-0/+52
This adds support for "func@localentry", an expression that returns the ELFv2 local entry point address of function "func". I've excluded dynamic relocation support because that obviously would require glibc changes. include/elf/ * ppc64.h (R_PPC64_REL24_NOTOC, R_PPC64_ADDR64_LOCAL): Define. bfd/ * elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_ADDR64_LOCAL entry. (ppc64_elf_reloc_type_lookup): Support R_PPC64_ADDR64_LOCAL. (ppc64_elf_check_relocs): Likewise. (ppc64_elf_relocate_section): Likewise. * Add BFD_RELOC_PPC64_ADDR64_LOCAL. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): Support @localentry. (md_apply_fix): Support R_PPC64_ADDR64_LOCAL. ld/testsuite/ * ld-powerpc/elfv2-2a.s, ld-powerpc/elfv2-2b.s: New files. * ld-powerpc/elfv2-2exe.d, ld-powerpc/elfv2-2so.d: New files. * ld-powerpc/powerpc.exp: Run new test. elfcpp/ * powerpc.h (R_PPC64_REL24_NOTOC, R_PPC64_ADDR64_LOCAL): Define. gold/ * powerpc.cc (Target_powerpc::Scan::local, global): Support R_PPC64_ADDR64_LOCAL. (Target_powerpc::Relocate::relocate): Likewise.
2014-03-05daily updateAlan Modra1-1/+1
2014-03-04Fix changelog formatting in last commit -- sorryRichard Sandiford1-1/+1
2014-03-04bfd/Richard Sandiford2-2/+9
2014-02-04 Heiher <r@hev.cc> * elfxx-mips.c (mips_set_isa_flags): Use E_MIPS_ARCH_64R2 for Loongson-3A. (mips_mach_extensions): Make bfd_mach_mips_loongson_3a an extension of bfd_mach_mipsisa64r2. opcodes/ 2014-02-04 Heiher <r@hev.cc> * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A. gas/ 2014-02-04 Heiher <r@hev.cc> * config/tc-mips.c (mips_cpu_info_table): Use ISA_MIPS64R2 for Loongson-3A.
2014-03-04Install patch for PR ld/16017. This adds support for generating PLT entriesNick Clifton2-42/+164
using Thumb2 instructions for those cores which do not support the ARM ISA. * elf32-arm.c (elf32_thumb2_plt0_entry): New array. (elf32_thumb2_plt_entry): New array. (elf32_arm_create_dynamic_sections): Set PLT entry sizes when using thumb2 based PLT. (elf32_arm_populate_plt_entry): Handle generating Thumb2 based PLT entries. (elf32_arm_final_link_relocate): Do not bias jumps to Thumb based PLT entries. (elf32_arm_finish_dynamic_sections): Handle creation of Thumb2 based PLT 0-entry. (elf32_arm_output_plt_map_1): Handle creation of local symbols for Thumb2 based PLT 0-entry. (elf32_arm_output_arch_local_syms): Handle creation of local symbols for Thumb2 based PLT entries.
2014-03-04daily updateAlan Modra1-1/+1
2014-03-03daily updateAlan Modra1-1/+1
2014-03-02daily updateAlan Modra1-1/+1
2014-03-01daily updateAlan Modra1-1/+1
2014-02-28Fix check_relocs/gc_sweep_hook mismatchAlan Modra2-1/+9
PR ld/16643 * elflink.c (elf_gc_sweep): Call gc_sweep_hook for exactly the same conditions we called check_relocs.
2014-02-28daily updateAlan Modra1-1/+1
2014-02-27This patch adds support for ARM PLT entries that support a full 32-bit ↵Yuri Gribov4-28/+89
offset range. Enabled via the use of a new linker command line option: --long-plt. * bfd-in.h: Add export of bfd_elf32_arm_use_long_plt. * bfd-in2.h: Regenerate. * elf32-arm.c (elf32_arm_plt_entry_long): New array. (elf32_arm_link_hash_table_create): Set plt_entry_size to 16 if using long PLT entries. (bfd_elf32_arm_use_long_plt): New function. (elf32_arm_populate_plt_entry): Add support for long PLT entries. * emultempl/armelf.em (OPTION_LONG_PLT): Define. (PARSE_AND_LIST_LONGOPTS): Add long-plt. (PARSE_AND_LIST_OPTIONS): Likewise. (PARSE_AND_LIST_ARGS_CASES): Handle long-plt. * ld.texinfo: Document --long-plt. * ld-arm/long-plt-format.s: New test case. * ld-arm/long-plt-format.d: Expected disassembly. * ld-arm/arm-elf.exp: Run the new test.
2014-02-27Fix ELF ppc32 targets that don't use ppc32elf.emAlan Modra2-3/+9
5446cbdf82892a800ed7eef563a795e75223ec52 broke powerpc-lynxos, powerpc-netware, powerpc-windiss and powerpc-vxworks. bfd/ * elf32-ppc.c (ppc_elf_link_hash_table_create): Provide default params for targets that don't use ppc32elf.em. ld/ * emulparams/elf32ppcvxworks.sh: Source plt_unwind.sh and use ppc32elf.em. * emultempl/ppc32elf.em (ppc_after_open): Don't compile for vxworks. (LDEMUL_AFTER_OPEN): Don't set for vxworks. (PARSE_AND_LIST_LONGOPTS, PARSE_AND_LIST_OPTIONS): Exclude -secure-plt, -bss-plt and -sdata-got when vxworks.
2014-02-27daily updateAlan Modra1-1/+1
2014-02-26daily updateAlan Modra1-1/+1
2014-02-25daily updateAlan Modra1-1/+1
2014-02-24daily updateAlan Modra1-1/+1
2014-02-23daily updateAlan Modra1-1/+1
2014-02-22daily updateAlan Modra1-1/+1
2014-02-21daily updateAlan Modra1-1/+1
2014-02-192014-02-20 Chung-Lin Tang <cltang@codesourcery.com>Chung-Lin Tang2-3/+12
* elf32-nios2.c (nios2_elf32_relocate_section): Fix calculation of GOTOFF relocations.
2014-02-20daily updateAlan Modra1-1/+1
2014-02-19Create the second PLT for BND relocationsH.J. Lu2-37/+444
Intel MPX introduces 4 bound registers, which will be used for parameter passing in x86-64. Bound registers are cleared by branch instructions. Branch instructions with BND prefix will keep bound register contents. This leads to 2 requirements to 64-bit MPX run-time: 1. Dynamic linker (ld.so) should save and restore bound registers during symbol lookup. 2. Change the current 16-byte PLT0: ff 35 08 00 00 00 pushq GOT+8(%rip) ff 25 00 10 00 jmpq *GOT+16(%rip) 0f 1f 40 00 nopl 0x0(%rax) and 16-byte PLT1: ff 25 00 00 00 00 jmpq *name@GOTPCREL(%rip) 68 00 00 00 00 pushq $index e9 00 00 00 00 jmpq PLT0 which clear bound registers, to preserve bound registers. We use 2 new relocations: to mark branch instructions with BND prefix. When linker sees any R_X86_64_PC32_BND or R_X86_64_PLT32_BND relocations, it switches to a different PLT0: ff 35 08 00 00 00 pushq GOT+8(%rip) f2 ff 25 00 10 00 bnd jmpq *GOT+16(%rip) 0f 1f 00 nopl (%rax) to preserve bound registers for symbol lookup and it also creates an external PLT section, .pl.bnd. Linker will create a BND PLT1 entry in .plt: 68 00 00 00 00 pushq $index f2 e9 00 00 00 00 bnd jmpq PLT0 0f 1f 44 00 00 nopl 0(%rax,%rax,1) and a 8-byte BND PLT entry in .plt.bnd: f2 ff 25 00 00 00 00 bnd jmpq *name@GOTPCREL(%rip) 90 nop Otherwise, linker will create a legacy PLT1 entry in .plt: 68 00 00 00 00 pushq $index e9 00 00 00 00 jmpq PLT0 66 0f 1f 44 00 00 nopw 0(%rax,%rax,1) and a 8-byte legacy PLT in .plt.bnd: ff 25 00 00 00 00 jmpq *name@GOTPCREL(%rip) 66 90 xchg %ax,%ax The initial value of the GOT entry for "name" will be set to the the "pushq" instruction in the corresponding entry in .plt. Linker will resolve reference of symbol "name" to the entry in the second PLT, .plt.bnd. Prelink stores the offset of pushq of PLT1 (plt_base + 0x10) in GOT[1] and GOT[1] is stored in GOT[3]. We can undo prelink in GOT by computing the corresponding the pushq offset with GOT[1] + (GOT offset - &GOT[3]) * 2 Since for each entry in .plt except for PLT0 we create a 8-byte entry in .plt.bnd, there is extra 8-byte per PLT symbol. We also investigated the 16-byte entry for .plt.bnd. We compared the 8-byte entry vs the the 16-byte entry for .plt.bnd on Sandy Bridge. There are no performance differences in SPEC CPU 2000/2006 as well as micro benchmarks. Pros: No change to undo prelink in dynamic linker. Only 8-byte memory overhead for each PLT symbol. Cons: Extra .plt.bnd section is needed. Extra 8 byte for legacy branches to PLT. GDB is unware of the new layout of .plt and .plt.bnd. bfd/ * elf64-x86-64.c (elf_x86_64_bnd_plt0_entry): New. (elf_x86_64_legacy_plt_entry): Likewise. (elf_x86_64_bnd_plt_entry): Likewise. (elf_x86_64_legacy_plt2_entry): Likewise. (elf_x86_64_bnd_plt2_entry): Likewise. (elf_x86_64_bnd_arch_bed): Likewise. (elf_x86_64_link_hash_entry): Add has_bnd_reloc and plt_bnd. (elf_x86_64_link_hash_table): Add plt_bnd. (elf_x86_64_link_hash_newfunc): Initialize has_bnd_reloc and plt_bnd. (elf_x86_64_copy_indirect_symbol): Also copy has_bnd_reloc. (elf_x86_64_check_relocs): Create the second PLT for Intel MPX in 64-bit mode. (elf_x86_64_allocate_dynrelocs): Handle the second PLT for IFUNC symbols. Resolve call to the second PLT if it is created. (elf_x86_64_size_dynamic_sections): Keep the second PLT section. (elf_x86_64_relocate_section): Resolve PLT references to the second PLT if it is created. (elf_x86_64_finish_dynamic_symbol): Use BND PLT0 and fill the second PLT entry for BND relocation. (elf_x86_64_finish_dynamic_sections): Use MPX backend data if the second PLT is created. (elf_x86_64_get_synthetic_symtab): New. (bfd_elf64_get_synthetic_symtab): Likewise. Undefine for NaCl. ld/ * emulparams/elf_x86_64.sh (TINY_READONLY_SECTION): New. ld/testsuite/ * ld-x86-64/mpx.exp: Run bnd-ifunc-1 and bnd-plt-1. * ld-x86-64/bnd-ifunc-1.d: New file. * ld-x86-64/bnd-ifunc-1.s: Likewise. * ld-x86-64/bnd-plt-1.d: Likewise.
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