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2019-05-16Automatic date update in version.inGDB Administrator1-1/+1
2019-05-15ARM STM32L4XX erratum test failureAlan Modra2-3/+12
Fixes a failure seen with MALLOC_PERTURB_=1. * elf32-arm.c (elf32_arm_write_section): Don't leave error case of STM32L4XX_ERRATUM_BRANCH_TO_VENEER with unitialised section contents.
2019-05-15Automatic date update in version.inGDB Administrator1-1/+1
2019-05-14Add new option to objcopy: --verilog-data-width. Use this option to set the ↵Jamey Hicks2-10/+76
size of byte bundles generated in verilog format files. PR 19921 binutils* objcopy.c: Add new option --verilog-data-width. Use it to set the value of VerilogDataWidth. * doc/binutils.texi: Document the new option. * testsuite/binutils-all/objcopy.exp: Run tests of new option. * testsuite/binutils-all/verilog-1.hex: New file. * testsuite/binutils-all/verilog-2.hex: New file. * testsuite/binutils-all/verilog-4.hex: New file. * testsuite/binutils-all/verilog-8.hex: New file. * NEWS: Mention the new feature. bfd * verilog.c: (VerilogDataWidth): New variable. (verilog_write_record): Emit bytes in VerilogDataWidth bundles.
2019-05-14Automatic date update in version.inGDB Administrator1-1/+1
2019-05-13Automatic date update in version.inGDB Administrator1-1/+1
2019-05-12Automatic date update in version.inGDB Administrator1-1/+1
2019-05-11Automatic date update in version.inGDB Administrator1-1/+1
2019-05-10Automatic date update in version.inGDB Administrator1-1/+1
2019-05-09Automatic date update in version.inGDB Administrator1-1/+1
2019-05-08Do not force the m68k-elf linker to fail if it encoutners a non-ELF format file.Nick Clifton2-2/+10
PR 24523 * elf32-m68k.c (elf32_m68k_merge_private_bfd_data): Return TRUE rather than FALSE if encountering a non-ELF file.
2019-05-08Automatic date update in version.inGDB Administrator1-1/+1
2019-05-07Automatic date update in version.inGDB Administrator1-1/+1
2019-05-06PicoJava weak undefined symbolsAlan Modra2-0/+5
This fixes the recently added ld-elf/pr24511 test failure on pj-elf. Incidentally, pj-elf has failed its gas "pj" test since 2005-12-22 (git commit 54758c3e39). I think that makes the target ripe for obsolescence. bfd/ * elf32-pj.c (pj_elf_reloc): Don't report undefined weak as an error. ld/ * testsuite/ld-undefined/weak-undef.exp: Don't xfail pj.
2019-05-06PowerPC reloc symbols that shouldn't be adjustedAlan Modra4-16/+24
GOT and PLT relocs shouldn't have their symbols replaced with a section symbol plus added. Nor should the HIGHA TLS relocations, which failed to be caught by the range test in ppc_fix_adjustable. bfd/ * reloc.c (BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA), (BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA): Sort before BFD_RELOC_PPC64_DTPREL16_HIGHESTA entry. gas/ * config/tc-ppc.c (ppc_fix_adjustable): Exclude all GOT and PLT relocs, and VLE sdarel relocs. * testsuite/gas/ppc/power4.d: Adjust.
2019-05-06Automatic date update in version.inGDB Administrator1-1/+1
2019-05-05Automatic date update in version.inGDB Administrator1-1/+1
2019-05-04PR24511, nm should not mark symbols in .init_array as "t"Alan Modra3-11/+28
This patch restricts the section names matched in coff_section_type, a function that translates section names to symbol type, and arranges to translate section flags to symbol type before looking at names. The latter change resulted in various test failures due to improper section flags being used in tests, and by the plugin support, so fix that too. The new test fails on many ELF targets that lack .init/fini_array in their scripts. I've just xfailed those. pru-elf oddly defines __init_array_begin rather than __init_array_start. I've left that target as a FAIL, and pj-elf too which reports an error for undefined weak symbols. bfd/ PR 24511 * syms.c (coff_section_type): Only allow '.', '$' and numeric following the standard section names. (bfd_decode_symclass): Prioritize section flag tests in decode_section_type before name tests in coff_section_type. * plugin.c (bfd_plugin_canonicalize_symtab): Init fake_section and fake_common_section using BFD_FAKE_SECTION. Use "fake" as their names and choose standard .text section flags for fake_section. ld/ PR 24511 * testsuite/ld-elf/pr14156a.d: Allow for .init/.fini being a data section on hppa64. * testsuite/ld-elf/pr14156b.d: Likewise. * testsuite/ld-scripts/pr18963.t: Map standard sections to set output section flags. * testsuite/ld-scripts/sane1.t: Likewise. * testsuite/ld-elf/init-fini-arrays.s: Reference __init_array_start and __fini_array_start. Define __start et al. * testsuite/ld-elf/pr24511.d: New test.
2019-05-04Automatic date update in version.inGDB Administrator1-1/+1
2019-05-03Automatic date update in version.inGDB Administrator1-1/+1
2019-05-02Treat the .gnu.debuglink and .gnu.debugaltlink sections as debug sections ↵Nick Clifton2-0/+11
when reading them in from COFF/PE format files. PR 24493 * coffcode.h (styp_to_sec_flags): Treat .gnu.debuglink and .gnu.debugaltlink sections as debugging sections.
2019-05-02Automatic date update in version.inGDB Administrator1-1/+1
2019-05-01Automatic date update in version.inGDB Administrator1-1/+1
2019-04-30PowerPC64 GOT indirect to GOT relative optimisationAlan Modra2-3/+216
This implements an optimisation that converts sequences like addis r9,r2,sym@got@ha ld r3,sym@got@l(r9) to addis r9,r2,sym@toc@ha addi r3,r9,sym@toc@l when "sym" is locally defined and can't be overridden. bfd/ * elf64-ppc.c (struct ppc64_elf_obj_tdata): Add has_gotrel. (struct _ppc64_elf_section_data): Likewise. (ppc64_elf_check_relocs): Set above fields. (ppc64_elf_edit_toc): Add a pass over GOT relocs. (ppc64_elf_relocate_section): Edit GOT indirect to GOT relative when possible. ld/ * testsuite/ld-powerpc/elfv2exe.d: Update. * testsuite/ld-powerpc/elfv2so.d: Update. * testsuite/ld-powerpc/tocopt.d: Update. * testsuite/ld-powerpc/tocopt.s: Update. * testsuite/ld-powerpc/tocopt5.d: Update. * testsuite/ld-powerpc/tocopt5.s: Update. * testsuite/ld-powerpc/tocopt7.d: Update. * testsuite/ld-powerpc/tocopt7.s: Update. * testsuite/ld-powerpc/tocopt8.d: Update. * testsuite/ld-powerpc/tocopt8.s: Update.
2019-04-30Automatic date update in version.inGDB Administrator1-1/+1
2019-04-29Automatic date update in version.inGDB Administrator1-1/+1
2019-04-28Automatic date update in version.inGDB Administrator1-1/+1
2019-04-27Automatic date update in version.inGDB Administrator1-1/+1
2019-04-26Don't complain undefined weak dynamic referenceH.J. Lu2-1/+7
When undefined non-weak references in IR objects are optimized out by LTO, we can have weak dynamic referencs to symbols marked with bfd_link_hash_undefined. We shouldn't complain such undefined weak dynamic references. bfd/ PR ld/24486 * elflink.c (elf_link_output_extsym): Don't complain undefined weak dynamic reference. ld/ PR ld/24486 * testsuite/ld-plugin/lto.exp: Run PR ld/24486 tests. * testsuite/ld-plugin/pr24486a.c: New file. * testsuite/ld-plugin/pr24486b.c: Likewise. * testsuite/ld-plugin/pr24486c.c: Likewise.
2019-04-26Automatic date update in version.inGDB Administrator1-1/+1
2019-04-25[BFD, AArch64] Improve bti/pac plts.Sudakshina Das2-60/+23
This patch aims to improve the definitions of BTI and PAC based PLTs. The following changes are made: * PLT0 does not need PAC instructions since the PLTGOT[2] (and PLTGOT[1]) are readonly so they cannot be corrupted at runtime. Thus both PAC plt0 and BTI+PAC plt0 are removed and we can use basic plt0 and BTI plt0 instead, respectively. * We can remove the extra padding nops when we add the new bti instructions. BTI plt0 and BTI TLSDESC plt are updated. * For better performance PLTn could be padded to 24bytes. Both BTI pltn and PAC pltn are updated. *** bfd/ChangeLog *** 2019-04-25 Sudakshina Das <sudi.das@arm.com> * elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): Remove. (PLT_BTI_TLSDESC_ENTRY_SIZE): Remove. (PLT_PAC_ENTRY_SIZE, PLT_BTI_PAC_ENTRY_SIZE): Remove. (PLT_BTI_SMALL_ENTRY_SIZE, PLT_PAC_SMALL_ENTRY_SIZE): Update. (elfNN_aarch64_small_plt0_pac_entry): Remove. (elfNN_aarch64_small_plt0_bti_pac_entry): Remove. (elfNN_aarch64_small_plt0_bti_entry): Update. (elfNN_aarch64_small_plt_bti_entry): Update. (elfNN_aarch64_small_plt_pac_entry): Update. (elfNN_aarch64_tlsdesc_small_plt_bti_entry): Update. (setup_plt_values): Setup new entries. (elfNN_aarch64_finish_dynamic_sections): Remove size change. (elfNN_aarch64_plt_sym_val): Likewise. *** ld/ChangeLog *** 2019-04-25 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-aarch64/bti-pac-plt-1.d: Update. * testsuite/ld-aarch64/bti-pac-plt-2.d: Update. * testsuite/ld-aarch64/bti-plt-1.d: Update. * testsuite/ld-aarch64/bti-plt-3.d: Update. * testsuite/ld-aarch64/bti-plt-5.d: Update. * testsuite/ld-aarch64/pac-plt-1.d: Update. * testsuite/ld-aarch64/pac-plt-2.d: Update.
2019-04-25Automatic date update in version.inGDB Administrator1-1/+1
2019-04-24Automatic date update in version.inGDB Administrator1-1/+1
2019-04-23Automatic date update in version.inGDB Administrator1-1/+1
2019-04-22RISC-V: Enable 32-bit linux gdb core file support.Jim Wilson2-1/+5
bfd/ * elfnn-riscv.c (PRSTATUS_SIZE) [ARCH_SIZE==32]: Change from 0 to 204.
2019-04-22Automatic date update in version.inGDB Administrator1-1/+1
2019-04-21Automatic date update in version.inGDB Administrator1-1/+1
2019-04-20Automatic date update in version.inGDB Administrator1-1/+1
2019-04-19s12z and h8300 no-print-map-discarded failsAlan Modra2-1/+4
This tidies the remaining --no-print-map-discarded fails. h8300-elf warns on a section without flags, and s12z doesn't support --gc-sections. bfd/ * elf32-s12z.c (elf_backend_can_gc_sections): Don't define ld/ * testsuite/ld-gc/skip-map-discarded.s: Add section attributes. * testsuite/lib/ld-lib.exp (check_gc_sections_available): Add s12z to list of targets not supporting --gc-sections.
2019-04-19Automatic date update in version.inGDB Administrator1-1/+1
2019-04-18Automatic date update in version.inGDB Administrator1-1/+1
2019-04-17x86: Suggest -fPIE when not building shared objectH.J. Lu3-7/+23
When PIC is needed, linker should suggest -fPIE, instead of -fPIC, when not building shared object. bfd/ * elf64-x86-64.c (elf_x86_64_need_pic): Suggest -fPIE when not building shared object. * elfxx-x86.c (_bfd_x86_elf_size_dynamic_sections): Likewise. ld/ * testsuite/ld-i386/i386.exp: Run pr18801a and pr18801b instead of pr18801. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/pr18801.d: Removed. * testsuite/ld-x86-64/pr18801.d: Likewise. * testsuite/ld-i386/pr18801a.d: New file. * testsuite/ld-i386/pr18801b.d: Likewise. * testsuite/ld-x86-64/pr18801a.d: Likewise. * testsuite/ld-x86-64/pr18801b.d: Likewise. * testsuite/ld-x86-64/pie2.d: Suggest -fPIE instead of -fPIC. * testsuite/ld-x86-64/pie2.d: Likewise. * testsuite/ld-x86-64/pr19719.d: Likewise. * testsuite/ld-x86-64/pr19807-2a.d: Likewise. * testsuite/ld-x86-64/pr19969.d: Likewise. * testsuite/ld-x86-64/pr21997-1a.err: Likewise. * testsuite/ld-x86-64/pr21997-1b.err: Likewise. * testsuite/ld-x86-64/pr22001-1a.err: Likewise. * testsuite/ld-x86-64/pr22001-1b.err: Likewise. * testsuite/ld-x86-64/pr22791-1.err: Likewise.
2019-04-17x86: Also check x86 linker_def for non-shared definitionH.J. Lu2-0/+7
Since elf_x86_linker_defined sets linker_def in elf_x86_link_hash_entry for linker defined symbols, SYMBOL_DEFINED_NON_SHARED_P should also check linker_def in elf_x86_link_hash_entry. bfd/ PR ld/24458 * elfxx-x86.h (SYMBOL_DEFINED_NON_SHARED_P): Also check x86 linker_def. ld/ PR ld/24458 * testsuite/ld-x86-64/x86-64.exp: Run PR ld/24458 tests. * testsuite/ld-x86-64/pr24458.s: New file. * testsuite/ld-x86-64/pr24458a-x32.d: Likewise. * testsuite/ld-x86-64/pr24458a.d: Likewise. * testsuite/ld-x86-64/pr24458b-x32.d: Likewise. * testsuite/ld-x86-64/pr24458b.d: Likewise. * testsuite/ld-x86-64/pr24458c-x32.d: Likewise. * testsuite/ld-x86-64/pr24458c.d: Likewise.
2019-04-17Automatic date update in version.inGDB Administrator1-1/+1
2019-04-16Automatic date update in version.inGDB Administrator1-1/+1
2019-04-15[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registersAndre Vieira4-0/+11
GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case. Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg (). A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match. ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal relocation. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (parse_sys_vldr_vstr): New function. (OP_VLDR): New enum operand_parse_code enumerator. (parse_operands): Add logic for OP_VLDR. (do_t_vldr_vstr_sysreg): New function. (do_vldr_vstr): Likewise. (insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode. (md_apply_fix): Add bound check for VLDR and VSTR co-processor offset. Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad uses of VLDR and VSTR. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for above bad uses. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and VSTR valid uses. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the above examples. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (coprocessor_opcodes): Document new %J and %K format specifier. Add entries for VLDR and VSTR of system registers. (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in coprocessor instructions on Armv8.1-M Mainline targets. Add handling of %J and %K format specifier.
2019-04-15[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M ↵Andre Vieira4-0/+15
Mainline s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds support to the Scalar low overhead loop instructions: LE WLS DLS We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions. ChangeLog entries are as follows: *** bfd/ChnageLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. *** gas/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR for the LR operand and optional LR operand. (parse_operands): Add switch cases for OP_LR and OP_oLR for both type checking and value checking. (encode_thumb32_addr_mode): New entries for DLS, WLS and LE. (v8_1_loop_reloc): New helper function for handling labels for the low overhead loop instructions. (do_t_loloop): New function to encode DLS, WLS and LE. (insns): New entries for WLS, DLS and LE. (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_LOOP12. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-tloop.s: New. * testsuite/gas/arm/armv8_1-m-tloop.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New. *** opcodes/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %P and %Q patterns.
2019-04-15[binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M MainlineAndre Vieira4-0/+15
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFCSEL instruction. It also adds a local relocation with a new bfd_reloc_code_real enum. ChangeLog entries are as follows: 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entriy for bfcsel. (do_t_v8_1_branch): New switch case for bfcsel. (toU): Define. (insns): New instruction for bfcsel. (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BFCSEL. (md_appdy_fix): Likewise (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-bfcsel.d: New. * testsuite/gas/arm/armv8_1-m-bfcsel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bfcsel.s: New. * testsuite/ld-arm/bfcsel.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instruction bfcsel. (print_insn_thumb32): Edit the switch case for %Z.
2019-04-15[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc ↵Andre Vieira5-1/+78
R_ARM_THM_BF12 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFCSEL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF12. The inconsistency between external R_ARM_THM_BF12 and internal BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : ChangeLog entries are as follows : *** bfd/ChnageLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF13): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13 and R_ARM_THM_BF12 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13. *** elfcpp/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF12): New relocation code. *** gas/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF13. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12. *** opcodes/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2019-04-15[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18Andre Vieira5-1/+80
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF18. The inconsistency between external R_ARM_THM_BF18 and internal BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF19): New * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19 and R_ARM_THM_BF18 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF18): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF19. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
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