rocket-tools/fsf-binutils-gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-11-25	riscv: Add AIA extension support (Smaia, Ssaia)	Christoph Müllner	1	-0/+4
2022-11-23	RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard	Xiao Zeng	1	-0/+4
2022-11-19	RISC-V: Add 'Ssstateen' extension and its CSRs	Tsukasa OI	1	-1/+3
2022-11-17	RISC-V: Add T-Head Int vendor extension	Christoph Müllner	1	-0/+5
2022-11-17	RISC-V: Add T-Head Fmv vendor extension	Christoph Müllner	1	-0/+5
2022-11-07	RISC-V: Remove RV32EF conflict	Tsukasa OI	1	-7/+0
2022-10-28	RISC-V: Output mapping symbols with ISA string.	Nelson Chu	1	-0/+7
2022-10-14	RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()	Jan Beulich	1	-0/+6
2022-10-14	RISC-V: Imply 'Zicsr' from privileged extensions with CSRs	Tsukasa OI	1	-0/+5
2022-10-04	RISC-V: Renamed INSN_CLASS for floating point in integer extensions.	Nelson Chu	1	-15/+14
2022-09-30	RISC-V: Add privileged extensions without instructions/CSRs	Tsukasa OI	1	-0/+3
2022-09-23	RISC-V: Add Zawrs ISA extension support	Christoph Müllner	1	-0/+5
2022-09-22	RISC-V: Add T-Head MemPair vendor extension	Christoph Müllner	1	-0/+5
2022-09-22	RISC-V: Add T-Head MemIdx vendor extension	Christoph Müllner	1	-0/+5
2022-09-22	RISC-V: Add T-Head FMemIdx vendor extension	Christoph Müllner	1	-0/+5
2022-09-22	RISC-V: Add T-Head MAC vendor extension	Christoph Müllner	1	-0/+5
2022-09-22	RISC-V: Add T-Head CondMov vendor extension	Christoph Müllner	1	-0/+5
2022-09-22	RISC-V: Add T-Head Bitmanip vendor extension	Christoph Müllner	1	-0/+15
2022-09-22	RISC-V: Add T-Head SYNC vendor extension	Christoph Müllner	1	-0/+5
2022-09-22	RISC-V: Add T-Head CMO vendor extension	Christoph Müllner	1	-0/+5
2022-09-22	RISC-V: Add generic support for vendor extensions	Christoph Müllner	1	-2/+7
2022-09-21	RISC-V: Implement Ztso extension	Shihua	1	-0/+1
2022-09-16	RISC-V: Make g imply zmmul extension.	Nelson Chu	1	-1/+1
2022-08-30	RISC-V: Add 'Zmmul' extension in assembler.	Tsukasa OI	1	-0/+6
2022-08-10	RISC-V: Remove R_RISCV_GNU_VTINHERIT/R_RISCV_GNU_VTENTRY	Fangrui Song	1	-29/+3
2022-07-07	RISC-V: Added Zfhmin and Zhinxmin.	Tsukasa OI	1	-45/+52
2022-07-07	RISC-V: Fix requirement handling on Zhinx+{D,Q}	Tsukasa OI	1	-5/+25
2022-07-04	RISC-V: Update Zihintpause extension version	Tsukasa OI	1	-1/+1
2022-06-28	RISC-V: Add 'Sstc' extension and its CSRs	Tsukasa OI	1	-0/+1
2022-06-28	RISC-V: Add 'Sscofpmf' extension with its CSRs	Tsukasa OI	1	-0/+1
2022-06-28	RISC-V: Add 'Smstateen' extension and its CSRs	Tsukasa OI	1	-0/+1
2022-06-22	RISC-V: Reorder the prefixed extensions which are out of order.	Nelson Chu	1	-23/+0
2022-06-22	RISC-V: Use single h extension to control hypervisor CSRs and instructions.	Nelson Chu	1	-11/+5
2022-06-22	RISC-V: Add 'H' to canonical extension ordering	Tsukasa OI	1	-1/+1
2022-06-22	RISC-V: Prepare i18n for required ISA extensions	Tsukasa OI	1	-13/+14
2022-06-08	Revert reloc howto nits	Alan Modra	1	-1/+1
2022-06-08	HOWTO size encoding	Alan Modra	1	-55/+55
2022-05-30	RISC-V: Add zhinx extension supports.	jiawei	1	-4/+20
2022-05-25	RISC-V: Fix RV32Q conflict	Tsukasa OI	1	-2/+3
2022-05-20	RISC-V: Update zfinx implement with zicsr.	Jia-Wei Chen	1	-0/+1
2022-05-19	RISC-V: Fix canonical extension order (K and J)	Tsukasa OI	1	-1/+1
2022-05-17	RISC-V: Added half-precision floating-point v1.0 instructions.	Nelson Chu	1	-0/+11
2022-03-18	RISC-V: Cache management instructions	Tsukasa OI	1	-0/+6
2022-03-18	RISC-V: Prefetch hint instructions and operand set	Tsukasa OI	1	-0/+3
2022-02-25	RISC-V: Remove a loop in the ISA parser	Tsukasa OI	1	-7/+4
2022-02-23	RISC-V: PR28733, add missing extension info to 'unrecognized opcode' error	Patrick O'Neill	1	-0/+94
2022-02-22	RISC-V: Maintain a string to hold the canonical order	Kito Cheng	1	-17/+5
2022-01-07	RISC-V: Updated the default ISA spec to 20191213.	Nelson Chu	1	-1/+3
2022-01-02	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2021-12-16	RISC-V: Support svinval extension with frozen version 1.0.	Nelson Chu	1	-0/+3