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2019-04-17MSP430 Assembler: Leave placement of .lower and .upper sections to generic ↵Jozef Lawrynowicz1-0/+13
linker code. * config/tc-msp430.c (msp430_make_init_symbols): Define __crt0_init_bss symbol when .lower.bss or .either.bss sections exist. Define __crt0_movedata when .lower.data or .either.data sections exist. * testsuite/gas/msp430/either-data-bss-sym.d: New test. * testsuite/gas/msp430/low-data-bss-sym.d: New test. * testsuite/gas/msp430/either-data-bss-sym.s: New test source. * testsuite/gas/msp430/low-data-bss-sym.s: New test source. * testsuite/gas/msp430/msp430.exp: Run new tests. Enable large code model when running -mdata-region={upper,either} tests.
2019-04-17MSP420 assembler: Add -m{u,U} options to enable/disable NOP warnings for ↵Jozef Lawrynowicz13-10/+198
unknown interrupt state changes gas * config/tc-msp430.c (options): New OPTION_UNKNOWN_INTR_NOPS, OPTION_NO_UNKNOWN_INTR_NOPS and do_unknown_interrupt_nops. (md_parse_option): Handle OPTION_UNKNOWN_INTR_NOPS and OPTION_NO_UNKNOWN_INTR_NOPS by setting do_unknown_interrupt_nops accordingly. (md_show_usage): Likewise. (md_shortopts): Add "mu" for OPTION_UNKNOWN_INTR_NOPS and "mU" for OPTION_NO_UNKNOWN_INTR_NOPS. (md_longopts): Likewise. (warn_eint_nop): Update comment. (warn_unsure_interrupt): Don't warn if prev_insn_is_nop or prev_insn_is_dint or we are assembling for 430 ISA. (msp430_operands): Only call warn_unsure_interrupt if do_unknown_interrupt_nops == TRUE. * testsuite/gas/msp430/nop-unknown-intr.s: New test source file. * testsuite/gas/msp430/nop-unknown-intr-430.d: New test. * testsuite/gas/msp430/nop-unknown-intr-430x.d: New test. * testsuite/gas/msp430/nop-unknown-intr-430x-ignore.d: New test. * testsuite/gas/msp430/nop-unknown-intr-430.l: Warning output for new test. * testsuite/gas/msp430/nop-unknown-intr-430x.l: Likewise. * testsuite/gas/msp430/msp430.exp: Add new tests to driver.
2019-04-17Avoid crash in dwarf2_init_complex_target_typeTom Tromey2-1/+6
After commit 35add35 ("gdb: Fix failure in gdb.base/complex-parts.exp for x86-32"), dwarf2_init_complex_target_type can crash if "tt" is nullptr. This patch avoids the problem by checking for this case. No test case because I don't know a good way to write one; it was found by an internal AdaCore test case that apparently uses a 16 bit floating point type. gdb/ChangeLog: * dwarf2read.c (dwarf2_init_complex_target_type): Check "tt" against nullptr before use. gdb/ChangeLog 2019-04-17 Tom Tromey <tromey@adacore.com> * dwarf2read.c (dwarf2_init_complex_target_type): Check "tt" against nullptr before use.
2019-04-17gdbserver: Ensure all debug output uses debug functionsAlan Hayward7-5/+31
All debug output needs to go via debug functions to ensure it writes to the correct output stream. gdb/ChangeLog: * nat/linux-waitpid.c (linux_debug): Call debug_vprintf. gdb/gdbserver/ChangeLog: * ax.c (ax_vdebug): Call debug_printf. * debug.c (debug_write): New function. * debug.h (debug_write): New declaration. * linux-low.c (sigchld_handler): Call debug_write.
2019-04-17gdbserver: Add debug-file optionAlan Hayward6-5/+79
Add command line option to send all debug output to a given file. Always default back to stderr. Add matching monitor command. Add documentation. gdb/doc/ChangeLog: * gdb.texinfo (Other Command-Line Arguments for gdbserver): Add debug-file option. (Monitor Commands for gdbserver): Likewise. (gdbserver man): Likewise. gdb/gdbserver/ChangeLog: * debug.c (debug_set_output): New function. (debug_vprintf): Send output to debug_file. (debug_flush): Likewise. * debug.h (debug_set_output): New declaration. * server.c (handle_monitor_command): Add debug-file option. (captured_main): Likewise.
2019-04-17gdbserver: Move remote_debug to a single placeAlan Hayward7-16/+18
A comment in debug.h (written in 2014) states: "We declare debug format variables here, and debug_threads but no other debug content variables (e.g., not remote_debug) because while this file is not currently used by IPA it may be some day, and IPA may have its own set of debug content variables". This has resulted in remote_debug being declared in many .c/.h files throughout gdbserver. It would be much simplier to define it one place. The most logical place to define it is in debug.h, surrounded by #define guards. If IPA is changed, then at that point the variable can be moved elsewhere. gdb/gdbserver/ChangeLog: * debug.c (remote_debug): Add definition. * debug.h (remote_debug): Add declaration. * hostio.c (remote_debug): Remove declaration. * remote-utils.c (struct ui_file): Likewise. (remote_debug): Likewise. * remote-utils.h (remote_debug): Likewise, * server.c (remote_debug): Remove definition.
2019-04-17Automatic date update in version.inGDB Administrator1-1/+1
2019-04-17gdb/riscv: Allow breakpoints to be created at invalid addressesAndrew Burgess2-1/+15
Some testsuite cases (gdb.cp/nsalias.exp for example) construct dwarf2 debug info for fake functions to test that this debug info is handled correctly. We currently get an error trying to read from an invalid address while creating breakpoints for these fake functions. Other targets allow creating breakpoints on invalid addresses, and only error when GDB actually tries to insert the breakpoints. In order to make RISC-V behave in the same way as other targets, this commit makes the failure to read memory during breakpoint creation non-fatal, we then expect to see a failure when GDB tries to insert the breakpoint, just like other targets. Tested with a riscv64-linux native testsuite run. gdb/ChangeLog: * riscv-tdep.c (riscv_breakpoint_kind_from_pc): Hanndle case where code read might fail, assume 4-byte breakpoint in that case.
2019-04-16xfail gas weakref1 test for nds32Alan Modra2-0/+5
Oops, I removed the wrong xfail from gas.exp in last commit, fix it here. * testsuite/gas/all/weakref1.d: xfail nds32.
2019-04-16ns32k testsuite tidyAlan Modra10-10/+24
Some of these tests were excluded for ns32k-netbsd, exclude for all ns32k instead. binutils/ * testsuite/binutils-all/copy-2.d: Don't run for ns32k-*-*. * testsuite/binutils-all/copy-3.d: Likewise. gas/ * testsuite/gas/all/gas.exp: Remove ns32k xfails. * testsuite/gas/all/weakref1u.d: Don't run for ns32k-*-*. ld/ * testsuite/ld-scripts/pr20302.d: Don't run for ns32k-*-*. * testsuite/ld-scripts/section-match-1.d: Likewise. * testsuite/ld-undefined/require-defined.exp: Likewise.
2019-04-16Move fixup fx_bit_fixP and fx_im_disp fields to TC_FIX_TYPEAlan Modra8-68/+66
These are only used by dlx and ns32k. * write.h: Don't include bit_fix.h. (struct fix): Rearrange some fields. Delete fx_im_disp and fx_bit_fixP. Use bitfields for fx_size and fx_pcrel_adjust. * write.c (fix_new_internal): Don't init fx_im_disp and fx_bit_fixP. (fixup_segment): Don't exclude overflow checks on fx_bit_fixP. (print_fixup): Don't print im_disp. * config/tc-cris.c (md_apply_fix): Remove tests of fx_bit_fixP and fx_im_disp. * config/tc-dlx.c (md_apply_fix): Remove wrong debug code. Set fx_no_overflow when fx_bit_fixP. * config/tc-dlx.h: Include bit_fix.h. (TC_FIX_TYPE, tc_fix_data, TC_INIT_FIX_DATA): Define. * config/tc-ns32k.c (fix_new_ns32k, fix_new_ns32k_exp): Set fx_no_overflow when bit_fixP. * config/tc-ns32k.h (TC_FIX_TYPE): Add fx_bit_fixP and fx_im_disp. (fix_im_disp, fix_bit_fixP): Adjust to suit. (TC_INIT_FIX_DATA, TC_FIX_DATA_PRINT): Likewise.
2019-04-16Make fixup fx_where unsignedAlan Modra7-27/+36
Another field that only stores unsigned values. * write.h (struct fix <fx_where>): Make unsigned. (fix_new, fix_at_start, fix_new_exp): Adjust prototypes. * write.c (fix_new, fix_new_exp, fix_at_start): Make "where" and "size" parameters unsigned long. (fix_new_internal): Likewise. Adjust error format string to suit. * config/tc-mips.c (md_convert_frag): Remove cast of fx_where. * config/tc-sparc.c (md_apply_fix): Likewise. * config/tc-score.c (s3_convert_frag): Adjust for unsigned fx_where. * config/tc-score7.c (s7_convert_frag): Likewise.
2019-04-16Make frag fr_fix unsignedAlan Modra13-23/+40
The field only stores unsigned values, so let's make it unsigned to stop people worrying about the possibility of negative values. * frags.h (struct frag <fr_fix>): Use unsigned type. * frags.c (frag_new): Assert that current size exceeds old_frags_var_max_size. * ehopt.c (get_cie_info): Adjust for unsigned fr_fix. * listing.c (calc_hex): Likewise. * write.c (cvt_frag_to_fill, write_relocs): Likewise. * config/tc-arc.c (md_convert_frag): Likewise. * config/tc-avr.c (avr_patch_gccisr_frag): Likewise. * config/tc-mips.c (md_convert_frag): Likewise. * config/tc-rl78.c (md_convert_frag): Likewise. * config/tc-rx.c (md_convert_frag): Likewise. * config/tc-sparc.c (md_apply_fix): Likewise. * config/tc-xtensa.c (next_instrs_are_b_retw): Likewise. (unrelaxed_frag_min_insn_count, unrelaxed_frag_has_b_j): Likewise.
2019-04-16Automatic date update in version.inGDB Administrator1-1/+1
2019-04-15Fix AMD64 return value ABI in expression evaluationLeszek Swirski5-11/+207
The AMD64 System V ABI specifies that when a function has a return type classified as MEMORY, the caller provides space for the value and passes the address to this space as the first argument to the function (before even the "this" pointer). The classification of MEMORY is applied to struct that are sufficiently large, or ones with unaligned fields. The expression evaluator uses call_function_by_hand to call functions, and the hand-built frame has to push arguments in a way that matches the ABI of the called function. call_function_by_hand supports ABI-based struct returns, based on the value of gdbarch_return_value, however on AMD64 the implementation of the classifier incorrectly assumed that all non-POD types (implemented as "all types with a base class") should be classified as MEMORY and use the struct return. This ABI mismatch resulted in issues when calling a function that returns a class of size <16 bytes which has a base class, including issues such as the "this" pointer being incorrect (as it was passed as the second argument rather than the first). This is now fixed by checking for field alignment rather than POD-ness, and a testsuite is added to test expression evaluation for AMD64. gdb/ChangeLog: * amd64-tdep.c (amd64_classify_aggregate): Use cp_pass_by_reference rather than a hand-rolled POD check when checking for forced MEMORY classification. gdb/testsuite/ChangeLog: * gdb.arch/amd64-eval.cc: New file. * gdb.arch/amd64-eval.exp: New file.
2019-04-15Skip print-map-discarded test for non-ELF targetsFaraz Shahbazker2-1/+8
ld/ * testsuite/ld-gc/gc.exp: Skip print-map-discarded test for non-ELF targets.
2019-04-15AArch64 SVE: Support changing vector lengths for ptraceAlan Hayward4-46/+73
When writing registers to the kernel, check if regcache VG has been changed. If so then update the thread's vector length, then write back the registers. When reading registers from the kernel, ensure regcache VG register is updated. The regcache registers should already be of the correct length. Remove all the checks that error if the vector length has changed. gdb/ChangeLog: * aarch64-linux-nat.c (store_sveregs_to_thread): Set vector length. * nat/aarch64-sve-linux-ptrace.c (aarch64_sve_set_vq): New function. (aarch64_sve_regs_copy_to_reg_buf): Remove VG checks. (aarch64_sve_regs_copy_from_reg_buf): Likewise. * nat/aarch64-sve-linux-ptrace.h (aarch64_sve_set_vq): New declaration.
2019-04-15AArch64 SVE: Check for vector length change when getting gdbarchAlan Hayward3-5/+59
Override the thread_architecture method, similar to SPU. If the vector length has changed, then find the arch using info, making sure the vector length is passed down to the init routine. In the init routine, ensure the arch has the correct vector length. Example output. Program is stopped in thread 2, just before it calls prctl to change the vector length (gdb) info threads Id Target Id Frame 1 Thread 0xffffbf6f4000 (LWP 3188) "sve_change" 0x0000ffffbf6ae130 in pthread_join () * 2 Thread 0xffffbf55e200 (LWP 3189) "sve_change" thread1 (arg=0xfeedface) at sve_change_size.c:28 (gdb) print $vg $1 = 8 (gdb) print $z0.s.u $2 = {623191333, 623191333, 623191333, 623191333, 0 <repeats 12 times>} (gdb) n 29 int ret = prctl(PR_SVE_SET_VL, vl/2); (gdb) n 30 printf ("Changed: ret\n", ret); (gdb) print $vg $4 = 4 (gdb) print $z0.s.u $5 = {623191333, 623191333, 623191333, 623191333, 0, 0, 0, 0} (gdb) thr 1 [Switching to thread 1 (Thread 0xffffbf6f4000 (LWP 3181))] (gdb) print $vg $6 = 8 (gdb) print $z0.s.u $7 = {623191333, 623191333, 623191333, 623191333, 0 <repeats 12 times>} gdb/ChangeLog: * aarch64-linux-nat.c (aarch64_linux_nat_target::thread_architecture): Add override. * aarch64-tdep.c (aarch64_gdbarch_init): Ensure different tdesc for each VQ.
2019-04-15AArch64: Tidy up aarch64_gdbarch_initAlan Hayward2-42/+30
Move the lookup_by_info to the top of the function to avoid unnecessarily creating a new feature when the gdbarch already exists. Add some additional cleanups that have no functional effect. gdb/ChangeLog: * aarch64-tdep.c (aarch64_gdbarch_init): Move gdbarch lookup.
2019-04-15[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registersAndre Vieira12-5/+295
GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case. Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg (). A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match. ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal relocation. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (parse_sys_vldr_vstr): New function. (OP_VLDR): New enum operand_parse_code enumerator. (parse_operands): Add logic for OP_VLDR. (do_t_vldr_vstr_sysreg): New function. (do_vldr_vstr): Likewise. (insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode. (md_apply_fix): Add bound check for VLDR and VSTR co-processor offset. Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad uses of VLDR and VSTR. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for above bad uses. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and VSTR valid uses. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the above examples. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (coprocessor_opcodes): Document new %J and %K format specifier. Add entries for VLDR and VSTR of system registers. (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in coprocessor instructions on Armv8.1-M Mainline targets. Add handling of %J and %K format specifier.
2019-04-15[binutils, ARM, 15/16] Add support for VSCCLRMAndre Vieira8-14/+196
Like for CLRM, this patch aims to share as much logic with the similar looking VLDM/VSTM. This is achieved by adding 2 new enumerator values in enum reg_list_els for the single-precision and double-precision variants of VSCCLRM and extending parse_vfp_reg_list () to deal with these types. These behave like the existing REGLIST_VFP_S and REGLIST_VFP_D types with extra logic to expect VPR as the last element in the register list. The function is algo augmented with a new partial_match parameter to indicate if any register other than VPR had already been parsed in the register list so as to not try parsing the second variant if that's the case and return the right error message. The rest of the patch is the usual encoding function, new disassembler table entries and format specifier and parsing, encoding and disassembling tests. It is worth mentioning that the new entry in the disassembler table was added in the coprocessor-related table despite VSCCLRM always being available even in FPU-less configurations. The main reason for this is that VSCCLRM also match VLDMIA entry and must thus be tried first but coprocessor entries are tried before T32 entries. It also makes sense because it is in the same encoding space as coprocessor and VFP instructions and is thus the natural place for someone to look for this instruction. Note: Both variants of VSCCLRM support D16-D31 registers but Armv8.1-M Mainline overall does not. I have thus decided not to implement support for these registers in order to keep the code simpler. It can always be added later if needed. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment. (enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR enumerators. (parse_vfp_reg_list): Add new partial_match parameter. Set *partial_match to TRUE if at least one element in the register list has matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR register lists which expect VPR as last element in the list. (s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new prototype. (s_arm_unwind_save_vfp): Likewise. (enum operand_parse_code): New OP_VRSDVLST enumerator. (parse_operands): Adapt call to parse_vfp_reg_list to new prototype. Handle new OP_VRSDVLST case. (do_t_vscclrm): New function. (insns): New entry for VSCCLRM instruction. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM instructions. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations for above instructions. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM instruction. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly for above instructions. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (coprocessor_opcodes): Document new %C format control code. Add new entries for VSCCLRM instruction. (print_insn_coprocessor): Handle new %C format control code.
2019-04-15[opcodes, ARM, 14/16] Add mode availability to coprocessor table entriesAndre Vieira2-413/+443
The coprocessor_opcodes table is used both to share commonalities in coprocessor-related instructions and to avoid duplication between Arm and Thumb mode. However, some instructions do have differences between Arm and Thumb. For instance, vldmia allows PC as base register in Arm mode but not in Thumb mode. In that very case the distinction becomes necessary because the encoding with PC as base register is used in Thumb mode to denote a VSCCLRM. It is thus necessary to distinguish what is Arm or Thumb only from what is shared. This patch adds an extra field to the coprocessor_opcodes table entries to indicate what mode is a given instruction available in. The print_insn_coprocessor then uses that field to determine if an entry that matched the mark and value checked should be allowed to match or not given the current mode. ChangeLog entry is as follows: *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (enum isa): New enum. (struct sopcode32): New structure. (coprocessor_opcodes): change type of entries to struct sopcode32 and set isa field of all current entries to ANY. (print_insn_coprocessor): Change type of insn to struct sopcode32. Only match an entry if its isa field allows the current mode.
2019-04-15[binutils, ARM, 13/16] Add support for CLRMAndre Vieira9-31/+171
Given the similarity between LDM/STM and CLRM register lists, most of the changes in this patch aim at sharing code between those two sets of instruction. Sharing is achieved both in parsing and encoding of those instructions. In terms of parsing, parse_reg_list () is extended to take a type that describe what type of instruction is being parsed. The reg_list_els used for parse_vfp_reg_list () is reused for the type and that function is added an assert for the new REGLIST_CLRM and REGLIST_RN enumerators. parse_reg_list () is then taught to accept APSR and reject SP and PC when parsing for a CLRM instruction. At last, caller of parse_reg_list () is updated accordingly and logic is added for the new OP_CLRMLST operand. Encoding-wise, encode_thumb2_ldmstm () is reused to encode the variable bits of CLRM and is thus renamed encode_thumb2_multi (). A new do_io parameter is added to distinguish between LDM/STM and CLRM which guard all the LDM/STM specific code of the function. Finally objdump is told how to disassemble CLRM, again reusing the logic to print the LDM/STM register list (format specifier 'm'). Tests are also added in the form of negative tests to check parsing and encoding/disassembling tests. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (enum reg_list_els): Define earlier and add REGLIST_RN and REGLIST_CLRM enumerators. (parse_reg_list): Add etype parameter to distinguish between regular core register list and CLRM register list. Add logic to recognize CLRM register list. (parse_vfp_reg_list): Assert type is not for core register list. (s_arm_unwind_save_core): Update call to parse_reg_list to new prototype. (enum operand_parse_code): Declare OP_CLRMLST enumerator. (parse_operands): Update call to parse_reg_list to new prototype. Add logic for OP_CLRMLST. (encode_thumb2_ldmstm): Rename into ... (encode_thumb2_multi): This. Add do_io parameter. Add logic to encode CLRM and guard LDM/STM only code by do_io. (do_t_ldmstm): Adapt to use encode_thumb2_multi. (do_t_push_pop): Likewise. (do_t_clrm): New function. (insns): Define CLRM. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for CLRM. (print_insn_thumb32): Add logic to print %n CLRM register list.
2019-04-15[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M ↵Andre Vieira13-0/+246
Mainline s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds support to the Scalar low overhead loop instructions: LE WLS DLS We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions. ChangeLog entries are as follows: *** bfd/ChnageLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. *** gas/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR for the LR operand and optional LR operand. (parse_operands): Add switch cases for OP_LR and OP_oLR for both type checking and value checking. (encode_thumb32_addr_mode): New entries for DLS, WLS and LE. (v8_1_loop_reloc): New helper function for handling labels for the low overhead loop instructions. (do_t_loloop): New function to encode DLS, WLS and LE. (insns): New entries for WLS, DLS and LE. (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_LOOP12. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-tloop.s: New. * testsuite/gas/arm/armv8_1-m-tloop.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New. *** opcodes/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %P and %Q patterns.
2019-04-15[binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M MainlineAndre Vieira14-0/+201
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFCSEL instruction. It also adds a local relocation with a new bfd_reloc_code_real enum. ChangeLog entries are as follows: 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entriy for bfcsel. (do_t_v8_1_branch): New switch case for bfcsel. (toU): Define. (insns): New instruction for bfcsel. (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BFCSEL. (md_appdy_fix): Likewise (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-bfcsel.d: New. * testsuite/gas/arm/armv8_1-m-bfcsel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bfcsel.s: New. * testsuite/ld-arm/bfcsel.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instruction bfcsel. (print_insn_thumb32): Edit the switch case for %Z.
2019-04-15[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc ↵Andre Vieira13-1/+152
R_ARM_THM_BF12 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFCSEL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF12. The inconsistency between external R_ARM_THM_BF12 and internal BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : ChangeLog entries are as follows : *** bfd/ChnageLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF13): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13 and R_ARM_THM_BF12 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13. *** elfcpp/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF12): New relocation code. *** gas/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF13. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12. *** opcodes/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2019-04-15[binutils, ARM, 9/16] New BFL instruction for Armv8.1-M MainlineAndre Vieira15-0/+150
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFL instruction. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entrie for bfl. (do_t_v8_1_branch): New switch case for bfl. (insns): New instruction for bfl. * testsuite/gas/arm/armv8_1-m-bfl.d: New. * testsuite/gas/arm/armv8_1-m-bfl.s: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.s: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.d: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.l: New. * testsuite/gas/arm/armv8_1-m-bfl-rel.d: New. * testsuite/gas/arm/armv8_1-m-bfl-rel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bfl.s: New. * testsuite/ld-arm/bfl.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instruction bfl.
2019-04-15[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18Andre Vieira13-1/+154
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF18. The inconsistency between external R_ARM_THM_BF18 and internal BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF19): New * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19 and R_ARM_THM_BF18 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF18): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF19. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2019-04-15[binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M MainlineAndre Vieira9-0/+84
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFX and BFLX instructions. ChangeLog entries are as follows : *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx. (do_t_v8_1_branch): New switch cases for bfx and bflx. (insns): New instruction for bfx and bflx. * testsuite/gas/arm/armv8_1-m-bf-exchange.d: New. * testsuite/gas/arm/armv8_1-m-bf-exchange.s: New. * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an Arm register with r13 and r15 unpredictable. (thumb32_opcodes): New instructions for bfx and bflx.
2019-04-15[binutils, ARM, 6/16] New BF instruction for Armv8.1-M MainlineAndre Vieira15-0/+194
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BF instruction. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entries for bf. (do_t_branch_future): New. (insns): New instruction for bf. * testsuite/gas/arm/armv8_1-m-bf.d: New. * testsuite/gas/arm/armv8_1-m-bf.s: New. * testsuite/gas/arm/armv8_1-m-bf-bad.s: New. * testsuite/gas/arm/armv8_1-m-bf-bad.l: New. * testsuite/gas/arm/armv8_1-m-bf-bad.d: New. * testsuite/gas/arm/armv8_1-m-bf-rel.d: New. * testsuite/gas/arm/armv8_1-m-bf-rel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bf.s: New. * testsuite/ld-arm/bf.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instructions for bf.
2019-04-15[binutils, ARM, 5/16] BF insns infrastructure with new global reloc ↵Andre Vieira13-2/+211
R_ARM_THM_BF16 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them. This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16. The inconsistency between external R_ARM_THM_BF16 and internal BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17 and R_ARM_THM_BF16 together. (get_value_helper): New reloc helper. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF16): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF17. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2019-04-15[binutils, ARM, 4/16] BF insns infrastructure with array of relocs in struct ↵Andre Vieira2-271/+310
arm_it This patch is part of a series of patches to add support for ARMv8.1-M Mainline instructions to binutils. This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX, BFCSEL). These are the first instructions in ARM that have more than one relocations in them. Their external relocations can be found in the 'ELF for the Arm Architecture - ABI 2019Q1' document on developer.arm.com This is the second infrastructure patch that adds support to allow up to 3 relocations in an instruction. This is done by changing the reloc member of struct arm_it to an array instead (relocs[3]). All the previous occurrences of reloc can now to referring to relocs[0]. ChangeLog entries are as follows : *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (ARM_IT_MAX_RELOCS): New macro. (arm_it): Member reloc renamed relocs and updated to an array. Rest: Replace all occurrences of reloc to relocs[0].
2019-04-15[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real ↵Andre Vieira8-0/+91
for fallback branch This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX, BFCSEL). These are the first instructions in ARM that have more than one relocations in them. This is the first infrastructure patch that adds a new bfd_reloc_code_real enum for the fallback branch offset. This is common for all such instructions and needs to be resolvable by the assembler. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (v8_1_branch_value_check): New function to check branch offsets. (md_appdy_fix): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (tc_gen_reloc): Likewise. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2019-04-15[GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M MainlineAndre Vieira6-4/+585
This patch implements the dsp, fp and fp.dp extensions for Armv8.1-M Mainline. This patch also removes the fp-armv8 check from the half-precision move instructions 'do_neon_movhf', as checking that the FP16 instructions extension feature bit is enabled 'ARM_EXT2_FP16_INST' is enough. gas/ChangeLog: 2019-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_movhf): Remove fp-armv8 check. (armv8_1m_main_ext_table): New extension table. (arm_archs): Use the new extension table. * doc/c-arm.texi: Add missing arch and document new extensions. * testsuite/gas/arm/armv8.1-m.main-fp.d: New. * testsuite/gas/arm/armv8.1-m.main-fp-dp.d: New. * testsuite/gas/arm/armv8.1-m.main-hp.d: New.
2019-04-15[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLIAndre Vieira19-53/+176
The patch is straightforward, it does the following: - support the new Tag_CPU_arch build attribute value, ie.: + declare the new value + update all the asserts forcing logic to be reviewed for new architectures + create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and add mapping from Tag_CPU_arch to it + teach readelf about new Tag_CPU_arch value - declare armv8.1-m.main as a supported architecture value - define Armv8.1-M Mainline in terms of feature bits available - tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature bits available - update architecture-specific logic in gas and bfd guarded by the asserts mentioned above. - tests for all the above ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * archures.c (bfd_mach_arm_8_1M_MAIN): Define. * bfd-in2.h: Regenerate. * cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline. * elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline and update assert. (using_thumb2): Likewise. (using_thumb2_bl): Update assert. (arch_has_arm_nop): Likewise. (bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline. (tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging. *** binutils/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline Tag_CPU_arch build attribute value. Reindent. (get_aeabi_cpu_arch_from_fset): Update assert. (aeabi_set_public_attributes): Update assert for Tag_DIV_use logic. * testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test. *** include/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro. (MAX_TAG_CPU_ARCH): Set value to above macro. * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro. (ARM_AEXT_V8_1M_MAIN): Likewise. (ARM_AEXT2_V8_1M_MAIN): Likewise. (ARM_ARCH_V8_1M_MAIN): Likewise. *** ld/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * testsuite/ld-arm/attr-merge-13.attr: New test. * testsuite/ld-arm/attr-merge-13a.s: New test. * testsuite/ld-arm/attr-merge-13b.s: New test. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2019-04-15Automatic date update in version.inGDB Administrator1-1/+1
2019-04-14Automatic date update in version.inGDB Administrator1-1/+1
2019-04-13sim: Use host not target byte order for merging and splitting valuesAndrew Burgess2-5/+14
When using writes to memory through a struct to merge and extract multi-word value, it is the endianness of the host, not the target that affects which order the component words need to be written into the structure. Of the 5 functions adjusted here 4 of them are unused. The 5th, JOINSIDF will soon be used by the or1k target. For or1k, simulated on x86-64, this change fixes this function so that the correct bytes are now returned. sim/common/ChangeLog: * cgen-ops.h (SUBWORDXFSI): Compare HOST_BYTE_ORDER not CURRENT_TARGET_BYTE_ORDER. (SUBWORDTFSI): Likewise. (JOINSIDF): Likewise. (JOINSIXF): Likewise. (JOINSITF): Likewise.
2019-04-13[MIPS] Add i6500 CPU and fix i6400 default ASEsMatthew Fortune6-1/+63
gas/ * config/tc-mips.c (mips_cpu_info_table): Add i6500. Update default ASEs for i6400. * doc/c-mips.texi (-march): Document i6500. * testsuite/gas/mips/elf_mach_i6400.d: New test. * testsuite/gas/mips/elf_mach_i6500.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests.
2019-04-13[MIPS] Apply ASE information for the selected processorMatthew Fortune4-7/+51
GAS does not enable implicit ASEs for most MIPS processors. The rework of option handling done as part of .module implementation left the implicit ASE logic broken and default enabled ASEs for most processors did not get applied. This patch ensures the ASE information is carried forward to the point where it is required. gas/ * config/tc-mips.c (mips_set_options) <init_ase>: New field. (file_mips_opts, mips_opts) <init_ase>: Initialize new field. (file_mips_check_options): Propagate initial ASE settings. (mips_after_parse_args, parse_code_option): Track the initial ASE settings for a CPU. (s_mipsset): Restore the initial ASE settings when reverting to the default arch. * testsuite/gas/mips/elf_mach_p6600.d: New test. * testsuite/gas/mips/mips.exp: Run the new test.
2019-04-13Automatic makefile dependencies for generated ld/e*.cAlan Modra155-2808/+1050
This patch modifies genscripts.sh to emit dependency info along with the generated emulation e*.c files. This is done by a new source_sh function that records its arg to a file (.deps/e*.Tc), using the function whenever a shell script is sourced. Entries in the file are made unique and written to .deps/e*.Pc. These files are then included by the Makefile. * Makefile.am (GENSCRIPTS): Pass LIB_PATH as a parameter. Add DEPDIR parameter. (ELF_DEPS, ELF_GEN_DEPS, ELF_X86_DEPS): Delete. (ALL_EMULATION_SOURCES, ALL_64_EMULATION_SOURCES): Depend on $GEN_DEPENDS. (e*.c): Delete all dependencies, instead include dependencies from $DEPDIR/*.Pc. * Makefile.in: Regenerate. * configure.ac (source_sh): Define and use function. * configure: Regenerate. * emulparams/aarch64cloudabib.sh, * emulparams/aarch64elf32b.sh, * emulparams/aarch64elfb.sh, * emulparams/aarch64fbsdb.sh, * emulparams/aarch64linux32b.sh, * emulparams/aarch64linuxb.sh, * emulparams/arcelf.sh, * emulparams/arcelf_prof.sh, * emulparams/arclinux.sh, * emulparams/arclinux_nps.sh, * emulparams/arclinux_prof.sh, * emulparams/arcv2elf.sh, * emulparams/arcv2elfx.sh, * emulparams/armelf_fbsd.sh, * emulparams/armelf_linux_eabi.sh, * emulparams/armelf_linux_fdpiceabi.sh, * emulparams/armelf_nacl.sh, * emulparams/armelf_nbsd.sh, * emulparams/armelf_vxworks.sh, * emulparams/armelfb.sh, * emulparams/armelfb_fbsd.sh, * emulparams/armelfb_fuchsia.sh, * emulparams/armelfb_linux.sh, * emulparams/armelfb_linux_eabi.sh, * emulparams/armelfb_linux_fdpiceabi.sh, * emulparams/armelfb_nacl.sh, * emulparams/armelfb_nbsd.sh, * emulparams/armsymbian.sh, * emulparams/cskyelf_linux.sh, * emulparams/elf32_sparc_sol2.sh, * emulparams/elf32_sparc_vxworks.sh, * emulparams/elf32_tic6x_be.sh, * emulparams/elf32_tic6x_elf_be.sh, * emulparams/elf32_tic6x_elf_le.sh, * emulparams/elf32_tic6x_linux_be.sh, * emulparams/elf32_tic6x_linux_le.sh, * emulparams/elf32_x86_64.sh, * emulparams/elf32_x86_64_nacl.sh, * emulparams/elf32b4300.sh, * emulparams/elf32bfinfd.sh, * emulparams/elf32bmipn32.sh, * emulparams/elf32bsmip.sh, * emulparams/elf32btsmip.sh, * emulparams/elf32btsmip_fbsd.sh, * emulparams/elf32btsmipn32.sh, * emulparams/elf32btsmipn32_fbsd.sh, * emulparams/elf32ebmip.sh, * emulparams/elf32ebmipvxworks.sh, * emulparams/elf32elmip.sh, * emulparams/elf32elmipvxworks.sh, * emulparams/elf32frvfd.sh, * emulparams/elf32l4300.sh, * emulparams/elf32lm32fd.sh, * emulparams/elf32lmip.sh, * emulparams/elf32lppc.sh, * emulparams/elf32lppclinux.sh, * emulparams/elf32lppcnto.sh, * emulparams/elf32lppcsim.sh, * emulparams/elf32lr5900.sh, * emulparams/elf32lr5900n32.sh, * emulparams/elf32lriscv.sh, * emulparams/elf32lriscv_ilp32.sh, * emulparams/elf32lriscv_ilp32f.sh, * emulparams/elf32lsmip.sh, * emulparams/elf32ltsmip.sh, * emulparams/elf32ltsmip_fbsd.sh, * emulparams/elf32ltsmipn32.sh, * emulparams/elf32ltsmipn32_fbsd.sh, * emulparams/elf32microblazeel.sh, * emulparams/elf32or1k_linux.sh, * emulparams/elf32ppc.sh, * emulparams/elf32ppc_fbsd.sh, * emulparams/elf32ppccommon.sh, * emulparams/elf32ppclinux.sh, * emulparams/elf32ppcnto.sh, * emulparams/elf32ppcsim.sh, * emulparams/elf32ppcvxworks.sh, * emulparams/elf32ppcwindiss.sh, * emulparams/elf32tilegx_be.sh, * emulparams/elf64_ia64_fbsd.sh, * emulparams/elf64_sparc_fbsd.sh, * emulparams/elf64_sparc_sol2.sh, * emulparams/elf64alpha_fbsd.sh, * emulparams/elf64alpha_nbsd.sh, * emulparams/elf64bmip-defs.sh, * emulparams/elf64bmip.sh, * emulparams/elf64btsmip.sh, * emulparams/elf64btsmip_fbsd.sh, * emulparams/elf64lppc.sh, * emulparams/elf64lriscv-defs.sh, * emulparams/elf64lriscv.sh, * emulparams/elf64lriscv_lp64.sh, * emulparams/elf64lriscv_lp64f.sh, * emulparams/elf64ltsmip.sh, * emulparams/elf64ltsmip_fbsd.sh, * emulparams/elf64ppc.sh, * emulparams/elf64ppc_fbsd.sh, * emulparams/elf64rdos.sh, * emulparams/elf64tilegx_be.sh, * emulparams/elf_i386.sh, * emulparams/elf_i386_be.sh, * emulparams/elf_i386_fbsd.sh, * emulparams/elf_i386_ldso.sh, * emulparams/elf_i386_nacl.sh, * emulparams/elf_i386_sol2.sh, * emulparams/elf_i386_vxworks.sh, * emulparams/elf_iamcu.sh, * emulparams/elf_k1om.sh, * emulparams/elf_k1om_fbsd.sh, * emulparams/elf_l1om.sh, * emulparams/elf_l1om_fbsd.sh, * emulparams/elf_x86_64.sh, * emulparams/elf_x86_64_cloudabi.sh, * emulparams/elf_x86_64_fbsd.sh, * emulparams/elf_x86_64_nacl.sh, * emulparams/elf_x86_64_sol2.sh, * emulparams/h8300helf.sh, * emulparams/h8300helf_linux.sh, * emulparams/h8300hnelf.sh, * emulparams/h8300self.sh, * emulparams/h8300self_linux.sh, * emulparams/h8300snelf.sh, * emulparams/h8300sxelf.sh, * emulparams/h8300sxelf_linux.sh, * emulparams/h8300sxnelf.sh, * emulparams/hppanbsd.sh, * emulparams/hppaobsd.sh, * emulparams/m32rlelf.sh, * emulparams/m32rlelf_linux.sh, * emulparams/m68kelfnbsd.sh, * emulparams/mn10300.sh, * emulparams/msp430X.sh, * emulparams/nds32belf.sh, * emulparams/nds32belf16m.sh, * emulparams/nds32belf_linux.sh, * emulparams/pjlelf.sh, * emulparams/ppclynx.sh, * emulparams/score7_elf.sh, * emulparams/shelf_fd.sh, * emulparams/shelf_linux.sh, * emulparams/shelf_nbsd.sh, * emulparams/shelf_uclinux.sh, * emulparams/shelf_vxworks.sh, * emulparams/shl.sh, * emulparams/shlelf.sh, * emulparams/shlelf_fd.sh, * emulparams/shlelf_nbsd.sh, * emulparams/shlelf_vxworks.sh: Use source_sh. * genscripts.sh: Adjust for changed parameters. Emit dependencies for e*.c to .deps/*.Pc. (source_sh): New function, use it throughout to source scripts. * genscrba.sh (source_em): Use source_sh.
2019-04-13ld TDIRS substitutionAlan Modra5-62/+28
It is no longer true that autoconf/automake cannot substitute vars with embedded new-lines. * configure.ac (TDIRS): Build up tdirs in this variable and AC_SUBST, also using AM_SUBST_NOTMAKE. * configure: Regenerate. * Makefile.am (DISTCLEANFILES): Remove tdirs. * Makefile.in: Regenerate.
2019-04-13gdb: Fix failure in gdb.base/complex-parts.exp for x86-32Andrew Burgess2-0/+16
The x86-32 ABI specifies 96-bit long double, this was causing a failure on the test gdb.base/complex-parts.exp. The problem is that GDB tries to find a builtin floating point type of the correct size in order to reuse the name of that type as the name for the components of the complex type being built. Previously GDB was only aware of floating point types sized 32, 64, or 128 bits. This patch teaches GDB how to handle 96 bit floating point type. gdb/ChangeLog: * dwarf2read.c (dwarf2_init_complex_target_type): Handle complex target types of size 96-bits, add some additional comments, and check that the builtin type we found was the correct size.
2019-04-13Automatic date update in version.inGDB Administrator1-1/+1
2019-04-12GAS: S12Z: Remove definition of macro TC_M68K.John Darrington2-3/+4
gas/config: * tc-s12z.h: Remove inappropriate macro definition.
2019-04-12S12Z: opcodes: Replace "operator" with "optr".John Darrington4-29/+34
opcodes/ * s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace operator with optr.
2019-04-12GAS: tc-s12z.c: int -> bfd_booleanJohn Darrington2-206/+210
Use bfd_boolean where appropriate.
2019-04-12Another fix for GDB stylingEli Zaretskii2-4/+7
gdb/ChangeLog: 2019-04-12 Eli Zaretskii <eliz@gnu.org> * utils.c (prompt_for_continue): Don't restore the styling at the end, as applied_style has the wrong value. This fixes styling in long lists of file names that are interrupted by the "Continue?" prompt.
2019-04-12Fix thinko in linker documentation.Nick Clifton2-1/+7
PR 24450 * ld.texi (Output Section Attributes): Add ALIGN_WITH_INPUT to example of section attributes.
2019-04-12Testsuite: Add gdbserver sysroot testAlan Hayward4-7/+118
The local board file ensures that the sysroot is always set to load files from the local filesystem. Add a gdbserver test to explicitly test the sysroot set to both the remote target and the local filesystem. gdb/testsuite/ChangeLog: * gdb.server/sysroot.c: New test. * gdb.server/sysroot.exp: New file. * lib/gdbserver-support.exp (gdb_target_cmd): Add additional text matching param.
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