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-rw-r--r--sim/mcore/interp.c8
-rw-r--r--sim/testsuite/mcore/sextb.s25
-rw-r--r--sim/testsuite/mcore/sexth.s27
3 files changed, 56 insertions, 4 deletions
diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c
index 53cfdad..48d9ff8 100644
--- a/sim/mcore/interp.c
+++ b/sim/mcore/interp.c
@@ -641,8 +641,8 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
{
long tmp;
tmp = gr[RD];
- tmp <<= 24;
- tmp >>= 24;
+ tmp <<= (sizeof (tmp) * 8) - 8;
+ tmp >>= (sizeof (tmp) * 8) - 8;
gr[RD] = tmp;
}
break;
@@ -653,8 +653,8 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
{
long tmp;
tmp = gr[RD];
- tmp <<= 16;
- tmp >>= 16;
+ tmp <<= (sizeof (tmp) * 8) - 16;
+ tmp >>= (sizeof (tmp) * 8) - 16;
gr[RD] = tmp;
}
break;
diff --git a/sim/testsuite/mcore/sextb.s b/sim/testsuite/mcore/sextb.s
new file mode 100644
index 0000000..5500f7a
--- /dev/null
+++ b/sim/testsuite/mcore/sextb.s
@@ -0,0 +1,25 @@
+# check that sext.b/sext.h work correctly
+# mach: mcore
+
+.include "testutils.inc"
+
+ start
+ # Construct -120 using bgeni+addi+sext
+ bgeni r2, 7
+ addi r2,8
+ sextb r2
+
+ # Construct -120 using movi+not
+ movi r7,119
+ not r7
+
+ # Compare them, they should be equal
+ cmpne r2,r7
+ jbt .L1
+ pass
+.L1:
+ fail
+
+
+
+
diff --git a/sim/testsuite/mcore/sexth.s b/sim/testsuite/mcore/sexth.s
new file mode 100644
index 0000000..97279c4
--- /dev/null
+++ b/sim/testsuite/mcore/sexth.s
@@ -0,0 +1,27 @@
+# check that sext.b/sext.h work correctly
+# mach: mcore
+
+.include "testutils.inc"
+
+ start
+ # Construct -32760 using bgeni+addi+sext
+ bgeni r2, 15
+ addi r2,8
+ sexth r2
+
+ # Construct -32760 using bmask+subi+not
+ bmaski r7,15
+ subi r7,8 // 32759 0x7ff7
+ not r7
+
+
+ # Compare them, they should be equal
+ cmpne r2,r7
+ jbt .L1
+ pass
+.L1:
+ fail
+
+
+
+