diff options
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/mips/ChangeLog | 14 | ||||
| -rw-r--r-- | sim/mips/mips.igen | 19 |
2 files changed, 28 insertions, 5 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 9ff5dbb..32d81c0 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,14 +1,20 @@ 2007-02-19 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> + * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2 + jumps with hazard barrier. + +2007-02-19 Thiemo Seufer <ths@mips.com> + Nigel Stephens <nigel@mips.com> + * interp.c (sim_monitor): Flush stdout and stderr file descriptors after each call to sim_io_write. -2007-02-19 Thiemo Seufer <ths@mips.com> +2007-02-19 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> - - (ColdReset): Set CP0 Config0 to reflect the address size supported - by this simulator. + + * interp.c (ColdReset): Set CP0 Config0 to reflect the address size + supported by this simulator. (decode_coproc): Recognise additional CP0 Config registers correctly. diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 6109589..93f4f2d 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -1945,8 +1945,18 @@ DELAY_SLOT (temp); } +000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB +"jalr.hb r<RS>":RD == 31 +"jalr.hb r<RD>, r<RS>" +*mips32r2: +*mips64r2: +{ + address_word temp = GPR[RS]; + GPR[RD] = CIA + 8; + DELAY_SLOT (temp); +} -000000,5.RS,000000000000000,001000:SPECIAL:32::JR +000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR "jr r<RS>" *mipsI: *mipsII: @@ -1964,6 +1974,13 @@ DELAY_SLOT (GPR[RS]); } +000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB +"jr.hb r<RS>" +*mips32r2: +*mips64r2: +{ + DELAY_SLOT (GPR[RS]); +} :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset { |