diff options
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/ppc/.Sanitize | 6 | ||||
| -rw-r--r-- | sim/ppc/ChangeLog | 145 | ||||
| -rw-r--r-- | sim/ppc/Makefile.in | 10 | ||||
| -rw-r--r-- | sim/ppc/ld-decode.c | 144 | ||||
| -rw-r--r-- | sim/ppc/ppc-opcode-complex | 35 | ||||
| -rw-r--r-- | sim/ppc/ppc-opcode-complex-array | 22 | ||||
| -rw-r--r-- | sim/ppc/ppc-opcode-complex-goto | 27 | ||||
| -rw-r--r-- | sim/ppc/ppc-opcode-complex-switch | 29 | ||||
| -rw-r--r-- | sim/ppc/ppc-opcode-goto | 22 | ||||
| -rw-r--r-- | sim/ppc/ppc-opcode-simple-array | 25 | ||||
| -rw-r--r-- | sim/ppc/ppc-opcode-simple-goto | 25 | ||||
| -rw-r--r-- | sim/ppc/ppc-opcode-simple-switch | 25 | ||||
| -rw-r--r-- | sim/ppc/ppc-opcode-stupid | 45 |
13 files changed, 538 insertions, 22 deletions
diff --git a/sim/ppc/.Sanitize b/sim/ppc/.Sanitize index c9239bf..901f913 100644 --- a/sim/ppc/.Sanitize +++ b/sim/ppc/.Sanitize @@ -140,10 +140,16 @@ pk_disklabel.c ppc-cache-rules ppc-instructions ppc-opcode-complex +ppc-opcode-complex-array +ppc-opcode-complex-goto +ppc-opcode-complex-switch ppc-opcode-flat ppc-opcode-goto ppc-opcode-jump ppc-opcode-simple +ppc-opcode-simple-array +ppc-opcode-simple-goto +ppc-opcode-simple-switch ppc-opcode-stupid ppc-opcode-test-1 ppc-opcode-test-2 diff --git a/sim/ppc/ChangeLog b/sim/ppc/ChangeLog index 83c76cc..24d62ff 100644 --- a/sim/ppc/ChangeLog +++ b/sim/ppc/ChangeLog @@ -1,5 +1,14 @@ Tue Feb 11 13:49:10 1997 Michael Meissner <meissner@tiktok.cygnus.com> + * events.c (event_queue_create): Don't use NULL to initialize an + integer field. + (even_queue_{init,schedule_after_signal,tick}): Conditionalize use + of sigprocmask to appropriate autoconf test. + + * main.c ({cntrl_c,main}): Use RETSIGTYPE for signal return type, + don't assume void. + * sim_calls.c (sim_{ctrl_c,resume}): Ditto. + * Makefile.in (callback.o): Define HAVE_CONFIG_H, so callback.c includes our config.h. @@ -8,6 +17,62 @@ Tue Feb 4 13:42:59 1997 Doug Evans <dje@canuck.cygnus.com> * configure.in: Fix typo in test for callback.c. * configure: Regenerated. +Fri Feb 7 10:04:25 1997 Andrew Cagney <cagney@kremvax.tpgi.com.au> + + * emul_chirp.c (emul_chirp_create): Handle a virtbase of -1 being + found in the device tree. + +Wed Feb 5 10:56:27 1997 Andrew Cagney <cagney@kremvax.tpgi.com.au> + + * Property create/initialization still wasn't correctly ordered. + Should be delaying everything related to ihandle creation until + after the rest of the tree has been established. + + * device.c (device_find_ihandle_runtime_property): Update. + (device_add_ihandle_runtime_property): Update. + + * tree.c (parse_ihandle_property): Delay lookup of the device to + be opened until the ihandle initialization phase. + * tree.c (print_properties): Update. + +Wed Feb 5 10:56:27 1997 Andrew Cagney <cagney@kremvax.tpgi.com.au> + + * gen-icache.c (print_icache_extraction): Add a reason parameter. + Augment each extracted field with a comment citing the codes + origin. Should simplify tracking down incorrect cache + extractions. + +Tue Feb 4 17:44:51 1997 Andrew Cagney <cagney@kremvax.tpgi.com.au> + + * gen-icache.c: Generalize code handling XXX_is_NNN so that it + works for normal and boolean table entries. + + * psim.c (psim_write_memory): last_cpu == -1 or nr_cpus is now + valid. Handle this just like *_{read,write}_register now handles + it. + +Mon Feb 3 17:18:16 1997 Andrew Cagney <cagney@kremvax.tpgi.com.au> + + * events.c (insert_event_entry): Correct loop termination + assertions. + +Fri Jan 31 16:20:26 1997 Andrew Cagney <cagney@kremvax.tpgi.com.au> + + * psim.c (psim_options): Add new option -c for max-iterations or + count. + (psim_usage): Document. + (psim_max_iterations_exceeded): New function, abort simulation if + max iterations exceeded. + + * gen-idecode.c: Re-work the table lookup code so that it assumes + that the entry is a leaf by default. Simplify the boolean table + entry code so that it involves a mask + test instead of shift + + shift + mask + test. + + * gen-idecode.c: Correct generated igen body so that it no drops + or doubles clock interrupts. + + Thu Jan 30 11:23:20 1997 Andrew Cagney <cagney@kremvax.tpgi.com.au> * Makefile.in (BUILT_SRC_WO_CONFIG): Change targ-vals.* to @@ -31,6 +96,86 @@ Wed Jan 29 12:32:41 1997 Michael Meissner <meissner@tiktok.cygnus.com> (targ-map.o): Add dependency. (clean): Remove gentmap. +Wed Jan 29 12:14:19 1997 Andrew Cagney <cagney@kremvax.tpgi.com.au> + + * igen wasn't aborting if the opcode table contained no valid + fields. + + * misc.c (name2i): Possibly abort if an invalid name is + encountered. + * ld-decode.c: Abort if the table type isn't found. + +Wed Jan 29 12:14:19 1997 Andrew Cagney <cagney@kremvax.tpgi.com.au> + + * When performance monitoring is disabled, it is still possible to + determine the simulation speed by looking at the number of elapsed + ticks recorded by the event queue. + + * psim.c (psim_write_register, psim_read_register): Force the cpu + to zero when it is either of `-1' or `nr_cpus'. In both cases the + next cpu would be zero any way. + + * mon.c (mon_print_info): If possible, print the system cycle + performance. This is an indication of the number of instructions + per second. + +Wed Jan 29 12:14:19 1997 Andrew Cagney <cagney@kremvax.tpgi.com.au> + + * The code to allow an event queue to be updated during a signal + was missing. For main.c, a cntrl-c simulation termination wasn't + handled cleanly. + + * The simulation would not correctly restart if an event requested + that the simulation be halted. + + * psim.c (psim_options): Add hack to -i option to optionally + include a level vis -i2. + (psim_usage): Document. + + * main.c (cntrl_c, cntrl_c_simulation): New functions. When a + cntrl-c occures schedule an event to halt the simulation. + (main): Catch CNTRL-C signals with the function cntrl_c. + + * events.c (event_queue_process): Mask interrupts while + manipulating the async event queue. + (event_queue_init): Ditto. + (event_queue_schedule_after_signal): Ditto. + + * events.c (event_queue_process): Mark the event queue as being in + the processing state when processing has started. Adjust code + so that it is tolerant of halts. + (event_queue_init): Start the event queue out with processing + false. + (event_queue_tick): Check that processing isn't still being + performed. + + * gen-idecode.c (print_run_until_stop_body): Call + event_queue_process_events to clear possibly pending events before + starting a simulation run. Re-arange main loop so that simulator + is correctly restarted when an event halts the simulation. + + * psim.c (psim_halt): Handle an event halting the simulation. + * psim.c (psim_init): Adjust initial cpu - == -1 - to match + reworked idecode. + +Wed Jan 29 12:14:19 1997 Andrew Cagney <cagney@kremvax.tpgi.com.au> + + * ppc-opcode-complex: Correct typo - was expanding ORA instead of + RA. Based on instruction frequency stats, expand additional + instructions. + * ppc-instructions: Change all `RA == 0' to RA_is_0. + + * ppc-opcode-stupid: Move all but the basic table in -complex into + here. Update to new format. + + * Makefile.in (tmp-defines): New target. Force defines.h to always + be built. Hence get ppc-opcode-goto to build. + +Tue Jan 28 13:00:19 1997 Andrew Cagney <cagney@kremvax.tpgi.com.au> + + * hw_com.c (hw_com_instance_read, hw_com_instance_write): + Implement. + Thu Jan 23 09:07:26 1997 Andrew Cagney <cagney@kremvax.tpgi.com.au> * hw_trace.c (hw_trace_init_data): Delete. The trace options need diff --git a/sim/ppc/Makefile.in b/sim/ppc/Makefile.in index 46644b2..f71903c 100644 --- a/sim/ppc/Makefile.in +++ b/sim/ppc/Makefile.in @@ -315,7 +315,7 @@ run: psim rm -f run ln psim run -$(TARGETLIB): tmp-igen tmp-dgen tmp-hw tmp-pk $(LIB_OBJ) $(GDB_OBJ) +$(TARGETLIB): tmp-igen tmp-dgen tmp-hw tmp-pk tmp-defines $(LIB_OBJ) $(GDB_OBJ) rm -f $(TARGETLIB) $(AR) $(AR_FLAGS) $(TARGETLIB) $(LIB_OBJ) $(GDB_OBJ) $(RANLIB) $(TARGETLIB) @@ -412,9 +412,11 @@ targ-map.o: targ-map.c targ-vals.h options.o: options.c $(BASICS_H) $(CPU_H) $(IDECODE_H) $(INLINE) $(LIB_SRC) $(BUILT_SRC) config.status Makefile defines.h $(CC) -c $(STD_CFLAGS) '-DOPCODE_RULES="@sim_opcode@"' '-DIGEN_FLAGS="$(IGEN_FLAGS)"' '-DDGEN_FLAGS="$(DGEN_FLAGS)"' $< -defines.h: config.h Makefile - rm -f defines.h - sed -n -e '/^#define HAVE_/s/ 1$$/",/' -e '/^#define HAVE_/s//"HAVE_/p' < config.h > defines.h +tmp-defines: config.h Makefile + sed -n -e '/^#define HAVE_/s/ 1$$/",/' -e '/^#define HAVE_/s//"HAVE_/p' < config.h > tmp-defines.h + $(srcdir)/../../move-if-change tmp-defines.h defines.h + touch tmp-defines + # # Rules to create the built c source code files # diff --git a/sim/ppc/ld-decode.c b/sim/ppc/ld-decode.c new file mode 100644 index 0000000..e83445f --- /dev/null +++ b/sim/ppc/ld-decode.c @@ -0,0 +1,144 @@ +/* This file is part of the program psim. + + Copyright (C) 1994,1995,1996, Andrew Cagney <cagney@highland.com.au> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + */ + +/* load the opcode stat structure */ + +#include "misc.h" +#include "lf.h" +#include "table.h" +#include "ld-decode.h" + +#ifndef NULL +#define NULL 0 +#endif + +enum { + op_options, + op_first, + op_last, + op_force_first, + op_force_last, + op_force_expansion, + op_special_mask, + op_special_value, + op_special_constant, + nr_decode_fields, +}; + +static const name_map decode_type_map[] = { + { "normal", normal_decode_rule }, + { "expand-forced", expand_forced_rule }, + { "boolean", boolean_rule }, + { NULL, normal_decode_rule }, +}; + +static const name_map decode_gen_map[] = { + { "array", array_gen }, + { "switch", switch_gen }, + { "padded-switch", padded_switch_gen }, + { "goto-switch", goto_switch_gen }, + { NULL, -1 }, +}; + +static const name_map decode_slash_map[] = { + { "variable-slash", 0 }, + { "constant-slash", 1 }, + { NULL }, +}; + + +decode_table * +load_decode_table(char *file_name, + int hi_bit_nr) +{ + table *file = table_open(file_name, nr_decode_fields, 0); + table_entry *entry; + decode_table *table = NULL; + decode_table **curr_rule = &table; + while ((entry = table_entry_read(file)) != NULL) { + decode_table *new_rule = ZALLOC(decode_table); + new_rule->type = name2i(entry->fields[op_options], decode_type_map); + new_rule->gen = name2i(entry->fields[op_options], decode_gen_map); + new_rule->force_slash = name2i(entry->fields[op_options], decode_slash_map); + new_rule->first = target_a2i(hi_bit_nr, entry->fields[op_first]); + new_rule->last = target_a2i(hi_bit_nr, entry->fields[op_last]); + new_rule->force_first = (strlen(entry->fields[op_force_first]) + ? target_a2i(hi_bit_nr, entry->fields[op_force_first]) + : new_rule->last + 1); + new_rule->force_last = (strlen(entry->fields[op_force_last]) + ? target_a2i(hi_bit_nr, entry->fields[op_force_last]) + : new_rule->first - 1); + new_rule->force_expansion = entry->fields[op_force_expansion]; + new_rule->special_mask = a2i(entry->fields[op_special_mask]); + new_rule->special_value = a2i(entry->fields[op_special_value]); + new_rule->special_constant = a2i(entry->fields[op_special_constant]); + *curr_rule = new_rule; + curr_rule = &new_rule->next; + } + return table; +} + + +void +dump_decode_rule(decode_table *rule, + int indent) +{ + dumpf(indent, "((decode_table*)%p\n", rule); + if (rule) { + dumpf(indent, " (type %s)\n", i2name(rule->type, decode_type_map)); + dumpf(indent, " (gen %s)\n", i2name(rule->gen, decode_gen_map)); + dumpf(indent, " (force_slash %d)\n", rule->force_slash); + dumpf(indent, " (first %d)\n", rule->first); + dumpf(indent, " (last %d)\n", rule->last); + dumpf(indent, " (force_first %d)\n", rule->force_first); + dumpf(indent, " (force_last %d)\n", rule->force_last); + dumpf(indent, " (force_expansion \"%s\")\n", rule->force_expansion); + dumpf(indent, " (special_mask 0x%x)\n", rule->special_mask); + dumpf(indent, " (special_value 0x%x)\n", rule->special_value); + dumpf(indent, " (special_constant 0x%x)\n", rule->special_constant); + dumpf(indent, " (next 0x%x)\n", rule->next); + } + dumpf(indent, " )\n"); +} + + +#ifdef MAIN + +static void +dump_decode_rules(decode_table *rule, + int indent) +{ + while (rule) { + dump_decode_rule(rule, indent); + rule = rule->next; + } +} + +int +main(int argc, char **argv) +{ + decode_table *rules; + if (argc != 3) + error("Usage: decode <decode-file> <hi-bit-nr>\n"); + rules = load_decode_table(argv[1], a2i(argv[2])); + dump_decode_rules(rules, 0); + return 0; +} +#endif diff --git a/sim/ppc/ppc-opcode-complex b/sim/ppc/ppc-opcode-complex index 78fac6a..13361ec 100644 --- a/sim/ppc/ppc-opcode-complex +++ b/sim/ppc/ppc-opcode-complex @@ -19,9 +19,40 @@ # array,normal: 0: 5: 0: 5: array,normal: 21:31:32:-1:OE,LR,AA,Rc,LK: +## +## Branch Conditional instruction - Expand BO{0:4} only, ignore BO{5} +## array,expand-forced: 6: 9: 6: 9:BO: 0xfc000000:0x40000000 -array,boolean: 11:15:11:15:0RA: 0xfc000000:0x38000000:0 +## +## Expand RA on equality with 0 in Add instructions were if(RA==0) appears. +## +# Add Immediate +array,boolean: 11:15:11:15:RA: 0xfc000000:0x38000000:0 +# Add Immediate Shifted array,boolean: 11:15:11:15:RA: 0xfc000000:0x3c000000:0 -# BLR instruction - LR=8 is munged into 0x100 == 256 +## +## Ditto for high frequency load/store instructions. +## +# Store Byte +#array,boolean: 11:15:11:15:RA: 0xfc000000:0x98000000:0 +# Store Word +#array,boolean: 11:15:11:15:RA: 0xfc000000:0x90000000:0 +# Load Word and Zero +#array,boolean: 11:15:11:15:RA: 0xfc000000:0x80000000:0 +## +## Move to/from SPR instructions - LR=8 is munged into 0x100 == 256 +## +#array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256 +#array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256 +## +## Compare Immediate instruction - separate out L == 0 and L == 1 +## +# Compare Immediate +#array,normal: 10:11:10:11:L: 0xfc000000:0x2c000000:0 +## +## Move to/from SPR instructions - separate out LR case +## +# Move to SPR array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256 +# Move from SPR array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256 diff --git a/sim/ppc/ppc-opcode-complex-array b/sim/ppc/ppc-opcode-complex-array new file mode 100644 index 0000000..0ff43b8 --- /dev/null +++ b/sim/ppc/ppc-opcode-complex-array @@ -0,0 +1,22 @@ +# +# This file is part of the program psim. +# +# Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +array,normal: 0: 5: 0: 5: +array,normal: 21:31:32:-1:OE,LR,AA,Rc,LK: +#array,expand-forced: 6: 9: 6: 9:BO: 0xfc000000:0x40000000 diff --git a/sim/ppc/ppc-opcode-complex-goto b/sim/ppc/ppc-opcode-complex-goto new file mode 100644 index 0000000..73e8d13 --- /dev/null +++ b/sim/ppc/ppc-opcode-complex-goto @@ -0,0 +1,27 @@ +# +# This file is part of the program psim. +# +# Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +goto-switch,normal: 0: 5: 0: 5: +goto-switch,normal: 21:31:32:-1:OE,LR,AA,Rc,LK: +goto-switch,expand-forced: 6: 9: 6: 9:BO: 0xfc000000:0x40000000 +goto-switch,boolean: 11:15:11:15:RA: 0xfc000000:0x38000000:0 +goto-switch,boolean: 11:15:11:15:RA: 0xfc000000:0x3c000000:0 +# BLR instruction - LR=8 is munged into 0x100 == 256 +goto-switch,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256 +goto-switch,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256 diff --git a/sim/ppc/ppc-opcode-complex-switch b/sim/ppc/ppc-opcode-complex-switch new file mode 100644 index 0000000..9c68d8b --- /dev/null +++ b/sim/ppc/ppc-opcode-complex-switch @@ -0,0 +1,29 @@ +# +# This file is part of the program psim. +# +# Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# sed < ppc-opcode-complex > ppc-opcode-flat -e 's/array/switch/' +# +padded-switch,normal: 0: 5: 0: 5: +padded-switch,normal: 21:31:32:-1:OE,LR,AA,Rc,LK: +padded-switch,expand-forced: 6: 9: 6: 9:BO: 0xfc000000:0x40000000 +switch,boolean: 11:15:11:15:RA: 0xfc000000:0x38000000:0 +switch,boolean: 11:15:11:15:RA: 0xfc000000:0x3c000000:0 +# BLR instruction +switch,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:0x100 +switch,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:0x100 diff --git a/sim/ppc/ppc-opcode-goto b/sim/ppc/ppc-opcode-goto index 7cbc690..49f2402 100644 --- a/sim/ppc/ppc-opcode-goto +++ b/sim/ppc/ppc-opcode-goto @@ -17,13 +17,15 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. # -# sed < ppc-opcode-complex > ppc-opcode-flat -e 's/array/switch/' -# -goto-switch,normal: 0: 5: 0: 5: -goto-switch,normal: 21:31:32:-1:OE,LR,AA,Rc,LK: -goto-switch,expand-forced: 6: 9: 6: 9:BO: 0xfc000000:0x40000000 -goto-switch,boolean: 11:15:11:15:0RA: 0xfc000000:0x38000000:0 -goto-switch,boolean: 11:15:11:15:RA: 0xfc000000:0x3c000000:0 -# BLR instruction -goto-switch,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:0x100 -goto-switch,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:0x100 +# sed < ppc-opcode-simple > ppc-opcode-goto -e 's/array/goto-switch/' +# +goto-switch: 0: 5 +goto-switch:21:31 +# +#goto-switch,normal: 21:31:32:-1:OE,LR,AA,Rc,LK: +#goto-switch,expand-forced: 6: 9: 6: 9:BO: 0xfc000000:0x40000000 +#goto-switch,boolean: 11:15:11:15:0RA: 0xfc000000:0x38000000:0 +#goto-switch,boolean: 11:15:11:15:RA: 0xfc000000:0x3c000000:0 +## BLR instruction - LR=8 is munged into 0x100 == 256 +#goto-switch,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:255 +#goto-switch,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:255 diff --git a/sim/ppc/ppc-opcode-simple-array b/sim/ppc/ppc-opcode-simple-array new file mode 100644 index 0000000..5a64405 --- /dev/null +++ b/sim/ppc/ppc-opcode-simple-array @@ -0,0 +1,25 @@ +# +# This file is part of the program psim. +# +# Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# +# Create a two level switch statement. The first level branches on bits +# 0..5 while the second level branches on bits 21..31 +# +array: 0: 5: 0: 5 +array:21:31 diff --git a/sim/ppc/ppc-opcode-simple-goto b/sim/ppc/ppc-opcode-simple-goto new file mode 100644 index 0000000..c42bc49 --- /dev/null +++ b/sim/ppc/ppc-opcode-simple-goto @@ -0,0 +1,25 @@ +# +# This file is part of the program psim. +# +# Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# +# Create a two level switch statement. The first level branches on bits +# 0..5 while the second level branches on bits 21..31 +# +goto-switch: 0: 5: 0: 5 +goto-switch:21:31 diff --git a/sim/ppc/ppc-opcode-simple-switch b/sim/ppc/ppc-opcode-simple-switch new file mode 100644 index 0000000..3909eb7 --- /dev/null +++ b/sim/ppc/ppc-opcode-simple-switch @@ -0,0 +1,25 @@ +# +# This file is part of the program psim. +# +# Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# +# Create a two level switch statement. The first level branches on bits +# 0..5 while the second level branches on bits 21..31 +# +padded-switch: 0: 5 +padded-switch:21:31 diff --git a/sim/ppc/ppc-opcode-stupid b/sim/ppc/ppc-opcode-stupid index 8493791..4238bdb 100644 --- a/sim/ppc/ppc-opcode-stupid +++ b/sim/ppc/ppc-opcode-stupid @@ -17,9 +17,42 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. # - 0: 5: 0: 5:0:0: 0:0x00000000:0x00000000:0 -21:31:32:-1:0:OE,LR,AA,Rc,LK:0:0x00000000:0x00000000:0 - 6:15: 6:15:0:BO,BI: 0:0xfc000000:0x40000000:0 -11:15:11:15:0:RA: 0:0xfc000000:0x38000000:2 -11:15:11:15:0:RA: 0:0xfc000000:0x3c000000:2 -11:20:11:20:0:spr: 0:0xfc000000:0x7c000000:0 +array,normal: 0: 5: 0: 5: +array,normal:21:31:32:-1:OE,LR,AA,Rc,LK: +## +## Branch Conditional instruction - Expand BO{0:4} only, ignore BO{5} +## +array,expand-forced: 6: 9: 6: 9:BO: 0xfc000000:0x40000000 +## +## Expand RA on equality with 0 in Add instructions were if(RA==0) appears. +## +# Add Immediate +#array,boolean: 11:15:11:15:RA: 0xfc000000:0x38000000:0 +# Add Immediate Shifted +#array,boolean: 11:15:11:15:RA: 0xfc000000:0x3c000000:0 +## +## Ditto for high frequency load/store instructions. +## +# Store Byte +#array,boolean: 11:15:11:15:RA: 0xfc000000:0x98000000:0 +# Store Word +#array,boolean: 11:15:11:15:RA: 0xfc000000:0x90000000:0 +# Load Word and Zero +#array,boolean: 11:15:11:15:RA: 0xfc000000:0x80000000:0 +## +## Move to/from SPR instructions - LR=8 is munged into 0x100 == 256 +## +#array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256 +#array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256 +## +## Compare Immediate instruction - separate out L == 0 and L == 1 +## +# Compare Immediate +#array,boolean: 10:11:10:11:L: 0xfc000000:0x2c000000:0 +## +## Move to/from SPR instructions - separate out LR case +## +# Move to SPR +#array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256 +# Move from SPR +#array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256 |