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-rw-r--r--sim/testsuite/ChangeLog26
-rw-r--r--sim/testsuite/d30v-elf/ChangeLog4
-rw-r--r--sim/testsuite/d30v-elf/do-flags.S18
-rw-r--r--sim/testsuite/sim/fr30/and.cgs14
-rw-r--r--sim/testsuite/sim/fr30/ldub.cgs12
-rw-r--r--sim/testsuite/sim/fr30/stb.cgs12
-rw-r--r--sim/testsuite/sim/fr30/sth.cgs18
-rw-r--r--sim/testsuite/sim/m32r/nop.cgs1
8 files changed, 78 insertions, 27 deletions
diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index f863482..953d2a4 100644
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,3 +1,15 @@
+1999-04-21 Doug Evans <devans@casey.cygnus.com>
+
+ * sim/m32r/nop.cgs: Add missing nop insn.
+
+Mon Mar 22 13:28:56 1999 Dave Brolley <brolley@cygnus.com>
+
+ * sim/fr30/stb.cgs: Correct for unaligned access.
+ * sim/fr30/sth.cgs: Correct for unaligned access.
+ * sim/fr30/ldub.cgs: Fix typo: lduh->ldub. Correct
+ for unaligned access.
+ * sim/fr30/and.cgs: Test unaligned access.
+
Fri Feb 5 12:41:11 1999 Doug Evans <devans@canuck.cygnus.com>
* lib/sim-defs.exp (sim_run): Print simulator arguments log message.
@@ -140,6 +152,11 @@ Tue Sep 15 14:56:22 1998 Doug Evans <devans@canuck.cygnus.com>
* sim/m32r/rte.cgs: Test bbpc,bbpsw.
* sim/m32r/trap.cgs: Test bbpc,bbpsw.
+Fri Jul 31 17:49:13 1998 Felix Lee <flee@cygnus.com>
+
+ * lib/sim-defs.exp (sim_run): remote_spawn, use writeto instead of
+ writeonly.
+
Fri Jul 24 09:40:34 1998 Doug Evans <devans@canuck.cygnus.com>
* Makefile.in (clean,mostlyclean): Change leading spaces to a tab.
@@ -148,6 +165,15 @@ Wed Jul 1 15:57:54 1998 Doug Evans <devans@seba.cygnus.com>
* sim/m32r/hw-trap.ms: New testcase.
+Tue Jun 16 15:44:01 1998 Jillian Ye <jillian@cygnus.com>
+
+ * lib/sim-defs.exp: Print out timeout setting info when "-v" is used.
+
+Thu Jun 11 15:24:53 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * lib/sim-defs.exp (sim_run): Argument env_vals renamed to options,
+ which is now a list of options controlling the behaviour of sim_run.
+
Wed Jun 10 10:53:20 1998 Doug Evans <devans@seba.cygnus.com>
* sim/m32r/addx.cgs: Add another test.
diff --git a/sim/testsuite/d30v-elf/ChangeLog b/sim/testsuite/d30v-elf/ChangeLog
index 6d8369f..98e5877 100644
--- a/sim/testsuite/d30v-elf/ChangeLog
+++ b/sim/testsuite/d30v-elf/ChangeLog
@@ -1,3 +1,7 @@
+1999-03-17 Frank Ch. Eigler <fche@cygnus.com>
+
+ * do-flags.S: Added new test for non-lkr status of MVTSYS.
+
1999-01-12 Frank Ch. Eigler <fche@cygnus.com>
* do-flags.S: Added one old, one new regression test.
diff --git a/sim/testsuite/d30v-elf/do-flags.S b/sim/testsuite/d30v-elf/do-flags.S
index 25797e5..f8a15cf 100644
--- a/sim/testsuite/d30v-elf/do-flags.S
+++ b/sim/testsuite/d30v-elf/do-flags.S
@@ -224,8 +224,22 @@
assert r60, 0x80000000
assert r61, 0x80000000
-
-
+
+ # PR 19224
+
+ add r7,r0,0x80000000
+ add r2,r0,r0 || nop
+ add r1,r0,0x1 || nop
+ # confirm that these insns do not kill the add in the right container
+ mvtsys psw,r7 -> add r2,r2,r1
+ mvtsys pswh,r7 -> add r2,r2,r1
+ mvtsys pswl,r7 -> add r2,r2,r1
+ mvtsys f0,r7 -> add r2,r2,r1
+ mvtsys mod_s,r7 -> add r2,r2,r1
+
+ assert r2, 0x5
+
+
# all okay
bra ok
diff --git a/sim/testsuite/sim/fr30/and.cgs b/sim/testsuite/sim/fr30/and.cgs
index 49db6fd..3148a31 100644
--- a/sim/testsuite/sim/fr30/and.cgs
+++ b/sim/testsuite/sim/fr30/and.cgs
@@ -42,10 +42,16 @@ and:
test_cc 1 0 0 0
test_h_mem 0xaaaa0000,sp
- mvi_h_mem 0xffff,sp
- set_cc 0x0d ; Set mask opposite of expected
+ mvr_h_gr sp,r9
+ inci_h_gr 4,r9
+ mvi_h_mem 0xffffffff,sp
+ mvi_h_mem 0xffff0000,r9
+ inci_h_gr 1,sp ; test unaligned access
+ set_cc 0x05 ; Set mask opposite of expected
and r7,@sp
- test_cc 0 0 0 1
- test_h_mem 0xaaaa,sp
+ test_cc 1 0 0 1
+ inci_h_gr -1,sp
+ test_h_mem 0xaaaaaaaa,sp
+ test_h_mem 0xffff0000,r9
pass
diff --git a/sim/testsuite/sim/fr30/ldub.cgs b/sim/testsuite/sim/fr30/ldub.cgs
index 97e00d9..8d42cfa 100644
--- a/sim/testsuite/sim/fr30/ldub.cgs
+++ b/sim/testsuite/sim/fr30/ldub.cgs
@@ -84,31 +84,31 @@ ldub:
add_h_gr r8,r14
set_cc 0x0f ; condition codes should not change
- lduh @(r14,0x7f),r7
+ ldub @(r14,0x7f),r7
test_cc 1 1 1 1
test_h_gr 0xde,r7
- inci_h_gr 0x3e,r14
+ inci_h_gr 0x3f,r14
set_cc 0x07 ; condition codes should not change
- lduh @(r14,0x40),r7
+ ldub @(r14,0x40),r7
test_cc 0 1 1 1
test_h_gr 0xde,r7
inci_h_gr 0x40,r14
set_cc 0x0b ; condition codes should not change
- lduh @(r14,0x0),r7
+ ldub @(r14,0x0),r7
test_cc 1 0 1 1
test_h_gr 0xde,r7
inci_h_gr 0x40,r14
set_cc 0x0d ; condition codes should not change
- lduh @(r14,-0x40),r7
+ ldub @(r14,-0x40),r7
test_cc 1 1 0 1
test_h_gr 0xde,r7
inci_h_gr 0x40,r14
set_cc 0x0e ; condition codes should not change
- lduh @(r14,-0x80),r7
+ ldub @(r14,-0x80),r7
test_cc 1 1 1 0
test_h_gr 0xde,r7
diff --git a/sim/testsuite/sim/fr30/stb.cgs b/sim/testsuite/sim/fr30/stb.cgs
index d9d4fd0..edbf4f2 100644
--- a/sim/testsuite/sim/fr30/stb.cgs
+++ b/sim/testsuite/sim/fr30/stb.cgs
@@ -55,13 +55,13 @@ stb:
mvi_h_gr 0xaaaaaafe,r8
mvi_h_mem 0xdeadbeef,sp
mvr_h_gr sp,r14
- inci_h_gr -127,r14
+ inci_h_gr -128,r14 ; must be aligned
+ mvi_h_mem 0xdeadbeef,r14
mvr_h_gr r14,r2
+ inci_h_gr -128,r14 ; must be aligned
mvi_h_mem 0xdeadbeef,r14
- inci_h_gr -128,r14
mvr_h_gr r14,r3
- mvi_h_mem 0xdeadbeef,r14
- inci_h_gr 128,r14
+ inci_h_gr 129,r14
set_cc 0x0b ; Condition codes should not change
stb r8,@(r14,127)
@@ -72,13 +72,13 @@ stb:
set_cc 0x0a ; Condition codes should not change
stb r8,@(r14,0)
test_cc 1 0 1 0
- test_h_mem 0xfeadbeef,r2
+ test_h_mem 0xdefebeef,r2
test_h_gr 0xaaaaaafe,r8
set_cc 0x09 ; Condition codes should not change
stb r8,@(r14,-128)
test_cc 1 0 0 1
- test_h_mem 0xfeadbeef,r3
+ test_h_mem 0xdefebeef,r3
test_h_gr 0xaaaaaafe,r8
pass
diff --git a/sim/testsuite/sim/fr30/sth.cgs b/sim/testsuite/sim/fr30/sth.cgs
index 64c83e6..8c4a115 100644
--- a/sim/testsuite/sim/fr30/sth.cgs
+++ b/sim/testsuite/sim/fr30/sth.cgs
@@ -52,33 +52,33 @@ sth:
; Test sth $Ri,@(R14,$disp9)
mvr_h_gr r9,sp ; Restore stack pointer
- mvi_h_gr 0xaaaabeef,r8
+ mvi_h_gr 0xaaaaabcd,r8
mvi_h_mem 0xdeadbeef,sp
mvr_h_gr sp,r14
- inci_h_gr -254,r14
+ inci_h_gr -256,r14 ; must be aligned
mvr_h_gr r14,r2
mvi_h_mem 0xdeadbeef,r14
inci_h_gr -256,r14
mvr_h_gr r14,r3
mvi_h_mem 0xdeadbeef,r14
- inci_h_gr 256,r14
+ inci_h_gr 258,r14
set_cc 0x0b ; Condition codes should not change
sth r8,@(r14,254)
test_cc 1 0 1 1
- test_h_mem 0xbeefbeef,r1
- test_h_gr 0xaaaabeef,r8
+ test_h_mem 0xabcdbeef,r1
+ test_h_gr 0xaaaaabcd,r8
set_cc 0x0a ; Condition codes should not change
sth r8,@(r14,0)
test_cc 1 0 1 0
- test_h_mem 0xbeefbeef,r2
- test_h_gr 0xaaaabeef,r8
+ test_h_mem 0xdeadabcd,r2
+ test_h_gr 0xaaaaabcd,r8
set_cc 0x09 ; Condition codes should not change
sth r8,@(r14,-256)
test_cc 1 0 0 1
- test_h_mem 0xbeefbeef,r3
- test_h_gr 0xaaaabeef,r8
+ test_h_mem 0xdeadabcd,r3
+ test_h_gr 0xaaaaabcd,r8
pass
diff --git a/sim/testsuite/sim/m32r/nop.cgs b/sim/testsuite/sim/m32r/nop.cgs
index 05b44bc..e06d656 100644
--- a/sim/testsuite/sim/m32r/nop.cgs
+++ b/sim/testsuite/sim/m32r/nop.cgs
@@ -7,4 +7,5 @@
.global nop
nop:
+ nop
pass
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