aboutsummaryrefslogtreecommitdiff
path: root/sim/testsuite
diff options
context:
space:
mode:
Diffstat (limited to 'sim/testsuite')
-rw-r--r--sim/testsuite/mips/basic.exp72
-rw-r--r--sim/testsuite/mips/hilo-hazard-3.s2
-rw-r--r--sim/testsuite/mips/r2-fpu.s31
-rw-r--r--sim/testsuite/mips/r6-64.s157
-rw-r--r--sim/testsuite/mips/r6-branch.s291
-rw-r--r--sim/testsuite/mips/r6-forbidden.s51
-rw-r--r--sim/testsuite/mips/r6-fpu.s446
-rw-r--r--sim/testsuite/mips/r6-llsc-dp.s57
-rw-r--r--sim/testsuite/mips/r6-llsc-wp.s41
-rw-r--r--sim/testsuite/mips/r6-removed.csv68
-rw-r--r--sim/testsuite/mips/r6-removed.s18
-rw-r--r--sim/testsuite/mips/r6.s163
-rw-r--r--sim/testsuite/mips/testutils.inc55
-rw-r--r--sim/testsuite/mips/utils-r6.inc150
14 files changed, 1597 insertions, 5 deletions
diff --git a/sim/testsuite/mips/basic.exp b/sim/testsuite/mips/basic.exp
index 81cce85..db29712 100644
--- a/sim/testsuite/mips/basic.exp
+++ b/sim/testsuite/mips/basic.exp
@@ -35,13 +35,61 @@ proc run_micromips_test { name requested_machs } {
unset ASFLAGS_FOR_TARGET
}
+# Runs endian tests
+proc run_endian_tests { name requested_machs } {
+ global ASFLAGS_FOR_TARGET
+ global LDFLAGS_FOR_TARGET
+ run_sim_test $name $requested_machs
+ set ASFLAGS_FOR_TARGET "-EL"
+ set LDFLAGS_FOR_TARGET "-EL"
+ run_sim_test $name $requested_machs
+ unset ASFLAGS_FOR_TARGET
+ unset LDFLAGS_FOR_TARGET
+}
+
# Runs all specified tests
proc run_sim_tests { name requested_machs { requested_micromips_machs "" } } {
run_sim_test $name $requested_machs
run_micromips_test $name $requested_micromips_machs
}
+
+# Runs the combination of instructions removed in R6 through the testsuite
+proc run_r6_removed_test {testfile models} {
+ global subdir srcdir
+ set fd [open "$srcdir/$subdir/r6-removed.csv" r]
+ set file_data [read $fd]
+ close $fd
+ set data [split $file_data "\n"]
+ foreach line $data {
+ set line_contents [split $line ","]
+ set mnemonic [lindex $line_contents 0]
+ set insn [lindex $line_contents 1]
+
+ if {[string compare $insn ""] == 1} {
+
+ set contents ""
+ append contents ".macro removed_instr\n"
+ append contents ".word $insn\n"
+ append contents "nop\n"
+ append contents ".endm"
+
+ verbose -log "r6-removed test: $mnemonic\n$contents"
+ set file [open r6-removed.inc w]
+ puts $file $contents
+ close $file
+
+ run_sim_test $testfile $models
+ }
+ }
+}
+
+
if {[istarget *]} {
+ # Used to locate the `run` program.
+ global arch
+ set arch "mips"
+
set dspmodels ""
set mdmxmodels ""
set micromipsmodels ""
@@ -51,18 +99,24 @@ if {[istarget *]} {
set models "sb1"
set submodels "mips1 mips2 mips3 mips4 mips32 mips64"
append mdmxmodels " mips64"
+ } elseif {[istarget mipsisa64r6*-*-elf]} {
+ set models "mips32r6 mips64r6"
+ set submodels ""
} elseif {[istarget mipsisa64*-*-elf]} {
set models "mips32 mips64 mips32r2 mips64r2"
set submodels "mips1 mips2 mips3 mips4"
append dspmodels " mips32r2 mips64r2"
append mdmxmodels " mips64 mips32r2 mips64r2"
} elseif {[istarget mips*-sde-elf*] || [istarget mips*-mti-elf*]} {
- set models "mips32 mips64 mips32r2 mips64r2"
+ set models "mips32 mips64 mips32r2 mips64r2 mips32r6 mips64r6"
set submodels ""
- append dspmodels " mips32r2 mips64r2"
- append mdmxmodels " mips64 mips32r2 mips64r2"
- append micromipsmodels " mips32r2"
+ append dspmodels " mips32r2 mips64r2 mips32r6 mips64r6"
+ append mdmxmodels " mips64 mips32r2 mips64r2 mips32r6 mips64r6"
+ append micromipsmodels " mips32r2 mips64r2"
append micromipsdspmodels " mips32r2 mips64r2"
+ } elseif {[istarget mipsisa32r6*-*-elf]} {
+ set models "mips32r6"
+ set submodels ""
} elseif {[istarget mipsisa32*-*-elf]} {
set models "mips32 mips32r2"
set submodels "mips1 mips2"
@@ -102,4 +156,14 @@ if {[istarget *]} {
run_sim_tests mips32-dsp.s $dspmodels $micromipsdspmodels
run_sim_tests mips32-dsp2.s $dspmodels $micromipsdspmodels
+ run_sim_test r2-fpu.s $models
+
+ run_sim_test r6-fpu.s $models
+ run_sim_test r6.s $models
+ run_sim_test r6-forbidden.s $models
+ run_r6_removed_test r6-removed.s $models
+ run_sim_test r6-64.s $models
+ run_sim_test r6-branch.s $models
+ run_endian_tests r6-llsc-wp.s $models
+ run_endian_tests r6-llsc-dp.s $models
}
diff --git a/sim/testsuite/mips/hilo-hazard-3.s b/sim/testsuite/mips/hilo-hazard-3.s
index 1a0949d..9d50da2 100644
--- a/sim/testsuite/mips/hilo-hazard-3.s
+++ b/sim/testsuite/mips/hilo-hazard-3.s
@@ -1,6 +1,6 @@
# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween.
#
-# mach: all
+# mach: -mips32r6 -mips64r6 all
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: pass\\n
diff --git a/sim/testsuite/mips/r2-fpu.s b/sim/testsuite/mips/r2-fpu.s
new file mode 100644
index 0000000..1001f93
--- /dev/null
+++ b/sim/testsuite/mips/r2-fpu.s
@@ -0,0 +1,31 @@
+# mips r2 fpu tests
+# mach: mips32r2 mips64r2
+# as: -mabi=eabi
+# ld: -N -Ttext=0x80010000
+# output: *\\npass\\n
+
+ .include "testutils.inc"
+
+ setup
+
+ .set noreorder
+
+ .ent DIAG
+
+DIAG:
+ writemsg "[1] Test qNaN format is 754-1985"
+ li $6, 0x7fbfffff
+ mtc1 $0, $f2
+ mtc1 $0, $f4
+ div.s $f6, $f2, $f4
+ mfc1 $8, $f6
+ beq $8, $6, L1
+ nop
+ fail
+
+ L1:
+ #TODO: More tests?
+
+ pass
+
+ .end DIAG
diff --git a/sim/testsuite/mips/r6-64.s b/sim/testsuite/mips/r6-64.s
new file mode 100644
index 0000000..365f49f
--- /dev/null
+++ b/sim/testsuite/mips/r6-64.s
@@ -0,0 +1,157 @@
+# mips64 specific r6 tests (non FPU)
+# mach: mips64r6
+# as: -mabi=eabi
+# ld: -N -Ttext=0x80010000 -Tdata=0x80020000
+# output: *\\npass\\n
+
+ .include "testutils.inc"
+ .include "utils-r6.inc"
+
+ .data
+d0: .dword 0
+dval: .dword 0xaa55bb66cc77dd88
+d1: .dword 0xaaaabbbbccccdddd
+d2: .dword 256
+dlo: .dword 0xaabbbbccccdddd00
+dhi: .dword 0xffffffffffffffaa
+dhiu: .dword 0x00000000000000aa
+d3: .dword 0xffaaaabbbbccccde
+d4: .dword 0xffffffffffffffdd
+d5: .dword 0x00000000000000dd
+d6: .dword 0x00aaaabbbbccccdd
+d7: .dword 0xeeeeffff00001111
+d8: .dword 0xbbccccddddeeeeff
+d9: .dword 0x000000ddaaaabbbb
+d10: .dword 0x5555dddd3333bbbb
+d11: .dword 0x9999999999999999
+d12: .dword 56
+d13: .dword 8
+d14: .dword 57
+d15: .dword 0x000000ddaaaac98b
+d16: .dword 0xffffffffdead00dd
+d17: .dword 0xffffffffc0de0000
+d18: .dword 0x0000123400000000
+d19: .dword 0xffffabcddead00dd
+d20: .dword 0xc0de000000000000
+d21: .dword 0x8000abcddead00dd
+dmask:.dword 0xffffffffffff0000
+dval1: .word 0x1234abcd
+dval2: .word 0xffee0000
+dval3: .dword 0xffffffffffffffff
+ .fill 240,1,0
+dval4: .dword 0x5555555555555555
+ .fill 264,1,0
+dval5: .dword 0xaaaaaaaaaaaaaaaa
+
+ .text
+
+ setup
+
+ .set noreorder
+
+ .ent DIAG
+DIAG:
+
+ writemsg "[1] Test DMUL"
+ r6ck_2r dmul, 6, 5, 30
+ r6ck_2r dmul, -7, 9, -63
+ r6ck_2r dmul, -1, 1, -1
+ r6ck_2dr dmul, d1, d2, dlo
+
+ writemsg "[2] Test DMUH"
+ r6ck_2r dmuh, 6, 5, 0
+ r6ck_2r dmuh, -7, 9, 0xffffffffffffffff
+ r6ck_2r dmuh, -1, 1, -1
+ r6ck_2dr dmuh, d1, d2, dhi
+
+ writemsg "[3] Test DMULU"
+ r6ck_2r dmulu, 12, 10, 120
+ r6ck_2r dmulu, -1, 1, -1
+ r6ck_2dr dmulu, d1, d2, dlo
+
+ writemsg "[4] Test DMUHU"
+ r6ck_2r dmuhu, 12, 10, 0
+ r6ck_2r dmuhu, -1, 1, 0
+ r6ck_2dr dmuhu, d1, d2, dhiu
+
+ writemsg "[5] Test DDIV"
+ r6ck_2r ddiv, 10001, 10, 1000
+ r6ck_2r ddiv, -123456, 560, -220
+ r6ck_2dr ddiv, d1, d2, d3
+
+ writemsg "[6] Test DMOD"
+ r6ck_2r dmod, 10001, 10, 1
+ r6ck_2r dmod, -123456, 560, 0xffffffffffffff00
+ r6ck_2dr dmod, d1, d2, d4
+
+ writemsg "[7] Test DDIVU"
+ r6ck_2r ddivu, 9, 100, 0
+ r6ck_2dr ddivu, d1, d2, d6
+
+ writemsg "[8] Test DMODU"
+ r6ck_2r dmodu, 9, 100, 9
+ r6ck_2dr dmodu, d1, d2, d5
+
+ writemsg "[9] Test DALIGN"
+ r6ck_2dr1i dalign, d7, d1, 3, d8
+ r6ck_2dr1i dalign, d1, d5, 4, d9
+
+ writemsg "[10] Test DBITSWAP"
+ r6ck_1dr dbitswap, d1, d10
+ r6ck_1dr dbitswap, d11, d11
+
+ writemsg "[11] Test DCLZ"
+ r6ck_1dr dclz, d5, d12
+ r6ck_1dr dclz, d6, d13
+
+ writemsg "[12] Test DCLO"
+ r6ck_1dr dclo, d5, d0
+ r6ck_1dr dclo, dhi, d14
+
+ writemsg "[13] Test DLSA"
+ r6ck_2r1i dlsa, 0x82, 0x2000068, 4, 0x2000888
+ r6ck_2dr1i dlsa, d5, d9, 4, d15
+
+ writemsg "[14] Test DAUI"
+ r6ck_1dr1i daui, d5, 0xdead, d16
+ r6ck_1dr1i daui, d0, 0xc0de, d17
+
+ writemsg "[15] Test DAHI"
+ r6ck_0dr1i dahi, d0, 0x1234, d18
+ r6ck_0dr1i dahi, d16, 0xabce, d19
+
+ writemsg "[16] Test DATI"
+ r6ck_0dr1i dati, d0, 0xc0de, d20
+ r6ck_0dr1i dati, d19, 0x8001, d21
+
+ writemsg "[17] Test LDPC"
+ ld $5, dval
+ nop
+ ldpc $4, dval
+ fp_assert $4, $5
+
+ writemsg "[18] Test LWUPC"
+ lwu $5, dval1
+ lwupc $4, dval1
+ fp_assert $4, $5
+ lwu $5, dval2
+ lwupc $4, dval2
+ fp_assert $4, $5
+
+ writemsg "[19] Test LLD"
+ ld $5, dval3
+ dla $3, dval4
+ lld $4, -248($3)
+ fp_assert $4, $5
+
+ writemsg "[20] Test SCD"
+ lld $4, -248($3)
+ dli $4, 0xafaf
+ scd $4, -248($3)
+ ld $5, dval3
+ dli $4, 0xafaf
+ fp_assert $4, $5
+
+ pass
+
+ .end DIAG
diff --git a/sim/testsuite/mips/r6-branch.s b/sim/testsuite/mips/r6-branch.s
new file mode 100644
index 0000000..2d905ba
--- /dev/null
+++ b/sim/testsuite/mips/r6-branch.s
@@ -0,0 +1,291 @@
+# mips r6 branch tests (non FPU)
+# mach: mips32r6 mips64r6
+# as: -mabi=eabi
+# ld: -N -Ttext=0x80010000
+# output: *\\npass\\n
+
+ .include "testutils.inc"
+ .include "utils-r6.inc"
+
+ setup
+
+ .set noreorder
+
+ .ent DIAG
+DIAG:
+ li $14, 0xffffffff
+ li $13, 0x123
+ li $12, 0x45
+ li $7, 0x45
+ li $8, 0xfffffffe
+ li $9, 2147483647
+ li $11, 0
+
+ writemsg "[1] Test BOVC"
+ bovc $12, $13, Lfail
+ nop
+ bovc $9, $13, L2
+ nop
+ fail
+
+L2:
+ writemsg "[2] Test BNVC"
+ bnvc $9, $13, Lfail
+ nop
+ bnvc $12, $13, L3
+ nop
+ fail
+
+L3:
+ writemsg "[3] Test BEQC"
+ beqc $12, $13, Lfail
+ nop
+ beqc $12, $7, L4
+ nop
+ fail
+
+L4:
+ writemsg "[4] Test BNEC"
+ bnec $12, $7, Lfail
+ nop
+ bnec $12, $13, L5
+ nop
+ fail
+
+L5:
+ writemsg "[5] Test BLTC"
+ bltc $13, $12, Lfail
+ nop
+ bltc $12, $13, L6
+ nop
+ fail
+
+L6:
+# writemsg "[6] Test BLEC"
+# blec $13, $12, Lfail
+# nop
+# blec $7, $12, L7
+# nop
+# fail
+
+L7:
+ writemsg "[7] Test BGEC"
+ bgec $12, $13, Lfail
+ nop
+ bgec $13, $12, L8
+ nop
+ fail
+
+L8:
+# writemsg "[8] Test BGTC"
+# bgtc $12, $13, Lfail
+# nop
+# bgtc $13, $12, L9
+# nop
+# fail
+
+
+L9:
+ writemsg "[9] Test BLTUC"
+ bltuc $14, $13, Lfail
+ nop
+ bltuc $8, $14, L10
+ nop
+ fail
+
+L10:
+# writemsg "[10] Test BLEUC"
+# bleuc $14, $13, Lfail
+# nop
+# bleuc $8, $14, L11
+# nop
+# fail
+
+L11:
+ writemsg "[11] Test BGEUC"
+ bgeuc $13, $14, Lfail
+ nop
+ bgeuc $14, $8, L12
+ nop
+ fail
+
+L12:
+# writemsg "[12] Test BGTUC"
+# bgtuc $13, $14, Lfail
+# nop
+# bgtuc $14, $8, L13
+# nop
+# fail
+
+L13:
+ writemsg "[13] Test BLTZC"
+ bltzc $13, Lfail
+ nop
+ bltzc $11, Lfail
+ nop
+ bltzc $14, L14
+ nop
+ fail
+
+L14:
+ writemsg "[14] Test BLEZC"
+ blezc $13, Lfail
+ nop
+ blezc $11, L145
+ nop
+ fail
+L145:
+ blezc $14, L15
+ nop
+ fail
+
+L15:
+ writemsg "[15] Test BGEZC"
+ bgezc $8, Lfail
+ nop
+ bgezc $11, L155
+ nop
+ fail
+L155:
+ bgezc $13, L16
+ nop
+ fail
+
+L16:
+ writemsg "[16] Test BGTZC"
+ bgtzc $8, Lfail
+ nop
+ bgtzc $11, Lfail
+ nop
+ bgtzc $13, L17
+ nop
+ fail
+
+ li $10, 0
+
+L17:
+ writemsg "[17] Test BLEZALC"
+ blezalc $12, Lfail
+ nop
+ blezalc $11, Lret
+ li $10, 1
+ beqzc $10, L175
+ nop
+ fail
+L175:
+ blezalc $14, Lret
+ li $10, 1
+ beqzc $10, L18
+ nop
+ fail
+
+L18:
+ writemsg "[18] Test BGEZALC"
+ bgezalc $14, Lfail
+ nop
+ bgezalc $11, Lret
+ li $10, 1
+ beqzc $10, L185
+ nop
+ fail
+L185:
+ bgezalc $12, Lret
+ li $10, 1
+ beqzc $10, L19
+ nop
+ fail
+
+L19:
+ writemsg "[19] Test BGTZALC"
+ bgtzalc $14, Lfail
+ nop
+ bgtzalc $11, Lfail
+ nop
+ bgtzalc $12, Lret
+ li $10, 1
+ beqzc $10, L20
+ nop
+ fail
+
+L20:
+ writemsg "[20] Test BLTZALC"
+ bltzalc $12, Lfail
+ nop
+ bltzalc $11, Lfail
+ nop
+ bltzalc $14, Lret
+ li $10, 1
+ beqzc $10, L21
+ nop
+ fail
+
+L21:
+ writemsg "[21] Test BC"
+ bc L22
+ fail
+
+L22:
+ writemsg "[22] Test BALC"
+ balc Lret
+ li $10, 1
+ beqzc $10, L23
+ nop
+ fail
+
+L23:
+ writemsg "[23] Test JIC"
+ jal GetPC
+ nop
+ jic $6, 4
+ nop
+ fail
+
+L24:
+ writemsg "[24] Test JIALC"
+ li $10, 1
+ jal GetPC
+ nop
+ jialc $6, 20
+ nop
+ beqzc $10, L25
+ nop
+ fail
+
+LJIALCRET:
+ li $10, 0
+ jr $ra
+ nop
+
+L25:
+ writemsg "[25] Test NAL"
+ jal GetPC
+ nop
+ move $11, $6
+ nal
+ nop
+ addiu $11, 12
+ beqc $11, $31, L26
+ nop
+ fail
+
+L26:
+ writemsg "[26] Test BAL"
+ balc Lret
+ li $10, 1
+ beqzc $10, Lend
+ nop
+ fail
+
+Lend:
+ pass
+
+Lfail:
+ fail
+
+ .end DIAG
+
+Lret:
+ li $10, 0
+ addiu $ra, 4
+ jr $ra
+ nop
diff --git a/sim/testsuite/mips/r6-forbidden.s b/sim/testsuite/mips/r6-forbidden.s
new file mode 100644
index 0000000..6ce56d3
--- /dev/null
+++ b/sim/testsuite/mips/r6-forbidden.s
@@ -0,0 +1,51 @@
+# mips r6 test for forbidden slot behaviour
+# mach: mips32r6 mips64r6
+# as: -mabi=eabi
+# ld: -N -Ttext=0x80010000
+# output: *\\nReservedInstruction at PC = *\\nprogram stopped with signal 4 (Illegal instruction).\\n
+# xerror:
+
+ .include "testutils.inc"
+
+ setup
+
+ .set noreorder
+
+ .ent DIAG
+DIAG:
+
+ writemsg "[1] Test if FS is ignored when branch is taken"
+ li $4, 0
+ beqzalc $4, L1
+ bc L2
+
+L2:
+ fail
+
+L1:
+ writemsg "[2] Test if FS is used when branch is not taken"
+ li $4, 1
+ blezc $4, L3
+ addiu $4, $4, 1
+ li $2, 2
+ beq $4, $2, L4
+
+L3:
+ nop
+ fail
+
+L4:
+ writemsg "[3] Test if FS causes an error when it contains a branch"
+ li $4, 3
+ beqzalc $4, L6
+ bc L5
+
+L5:
+ nop
+ fail
+
+L6:
+ #There is no passing condition here, all routes to the end indicate failure
+ fail
+
+ .end DIAG
diff --git a/sim/testsuite/mips/r6-fpu.s b/sim/testsuite/mips/r6-fpu.s
new file mode 100644
index 0000000..14a2ea5
--- /dev/null
+++ b/sim/testsuite/mips/r6-fpu.s
@@ -0,0 +1,446 @@
+# mips r6 fpu test for FMADD/FMSUB etc.
+# mach: mips64r6
+# as: -mabi=eabi
+# ld: -N -Ttext=0x80010000
+# output: *\\npass\\n
+
+ .include "testutils.inc"
+ .include "utils-r6.inc"
+
+ setup
+
+ .set noreorder
+
+ .ent DIAG
+DIAG:
+
+ writemsg "[1] Test qNaN format is 754-2008"
+ li $4, 0x0
+ li $5, 0x0
+ li $6, 0x7fc00000
+ mtc1 $4, $f2
+ mtc1 $5, $f4
+ div.s $f6, $f2, $f4
+ mfc1 $8, $f6
+ fp_assert $6, $8
+
+ writemsg "[2] Test maddf.s"
+ r6ck_3s maddf.s, 0x0, 0x0, 0x0, 0x0
+ r6ck_3s maddf.s, 0x3f800000, 0x3f800000, 0x3f800000, 0x40000000
+ r6ck_3s maddf.s, 0xc0b1f5c3, 0x40490fd0, 0x402df854, 0x403e9f5d
+
+ writemsg "[3] Test maddf.d"
+ r6ck_3d maddf.d, 0x0, 0x0, 0x0, 0x0
+ r6ck_3d maddf.d, 0x3ff0000000000000, 0x3ff0000000000000, 0x3ff0000000000000, 0x4000000000000000
+ r6ck_3d maddf.d, 0xc0163eb851eb851f, 0x400921f9f01b866e, 0x4005bf0a8b24919b, 0x4007d3ebc14f6cee
+
+ writemsg "[4] Test msubf.s"
+ r6ck_3s msubf.s, 0x0, 0x0, 0x0, 0x0
+ r6ck_3s msubf.s, 0x3f800000, 0x3f800000, 0x3f800000, 0x0
+ r6ck_3s msubf.s, 0xc0b1f5c3, 0x40490fd0, 0x402df854, 0xc1619d9a
+
+ writemsg "[5] Test msubf.d"
+ r6ck_3d msubf.d, 0x0, 0x0, 0x0, 0x0
+ r6ck_3d msubf.d, 0x3ff0000000000000, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
+ r6ck_3d msubf.d, 0xc0163eb851eb851f, 0x400921f9f01b866e, 0x4005bf0a8b24919b, 0xc02c33b3423f605b
+
+ writemsg "[6] Test CMP.af.s"
+ r6ck_3s cmp.af.s, 0x0, 0x3f800000, 0x3f800000, 0x0
+ r6ck_3s cmp.af.s, 0x0, 0x00000000, 0x3f800000, 0x0
+
+ writemsg "[7] Test CMP.af.d"
+ r6ck_3d cmp.af.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
+ r6ck_3d cmp.af.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0x0
+
+ writemsg "[8] Test CMP.eq.s"
+ r6ck_3s cmp.eq.s, 0x0, 0x3f800000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.eq.s, 0x0, 0x00000000, 0x3f800000, 0x0
+ r6ck_3s cmp.eq.s, 0x0, 0x80000000, 0x00000000, 0xffffffff
+ r6ck_3s cmp.eq.s, 0x0, 0x7fc00000, 0x7fc00000, 0x0
+ r6ck_3s cmp.eq.s, 0x0, 0x7fc00000, 0xffc00000, 0x0
+ r6ck_3s cmp.eq.s, 0x0, 0x7fa00000, 0x7fa00000, 0x0
+ r6ck_3s cmp.eq.s, 0x0, 0x7fa00000, 0x7fc00000, 0x0
+ r6ck_3s cmp.eq.s, 0x0, 0x7f800000, 0x7f800000, 0xffffffff
+ r6ck_3s cmp.eq.s, 0x0, 0xff800000, 0xff800000, 0xffffffff
+
+ writemsg "[9] Test CMP.eq.d"
+ r6ck_3d cmp.eq.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.eq.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0x0
+ r6ck_3d cmp.eq.d, 0x0, 0x8000000000000000, 0x0000000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.eq.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0x0
+ r6ck_3d cmp.eq.d, 0x0, 0x7ff8000000000000, 0xffc0000000000000, 0x0
+ r6ck_3d cmp.eq.d, 0x0, 0x7fa0000000000000, 0x7fa0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.eq.d, 0x0, 0x7fa0000000000000, 0x7ff8000000000000, 0x0
+ r6ck_3d cmp.eq.d, 0x0, 0x7ff0000000000000, 0x7ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.eq.d, 0x0, 0xfff0000000000000, 0xfff0000000000000, 0xffffffffffffffff
+
+ writemsg "[10] Test CMP.ne.s"
+ r6ck_3s cmp.ne.s, 0x0, 0x3f800000, 0x3f800000, 0x0
+ r6ck_3s cmp.ne.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.ne.s, 0x0, 0x80000000, 0x00000000, 0x0
+ r6ck_3s cmp.ne.s, 0x0, 0x7fc00000, 0x7fc00000, 0x0
+ r6ck_3s cmp.ne.s, 0x0, 0x7fc00000, 0xffc00000, 0x0
+ r6ck_3s cmp.ne.s, 0x0, 0x7fa00000, 0x7fa00000, 0x0
+ r6ck_3s cmp.ne.s, 0x0, 0x7fa00000, 0x7fc00000, 0x0
+ r6ck_3s cmp.ne.s, 0x0, 0x7f800000, 0x7f800000, 0x0
+ r6ck_3s cmp.ne.s, 0x0, 0xff800000, 0xff800000, 0x0
+
+ writemsg "[11] Test CMP.ne.d"
+ r6ck_3d cmp.ne.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
+ r6ck_3d cmp.ne.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.ne.d, 0x0, 0x8000000000000000, 0x0000000000000000, 0x0
+ r6ck_3d cmp.ne.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0x0
+ r6ck_3d cmp.ne.d, 0x0, 0x7ff8000000000000, 0xffc0000000000000, 0x0
+ r6ck_3d cmp.ne.d, 0x0, 0x7fa0000000000000, 0x7fa0000000000000, 0x0
+ r6ck_3d cmp.ne.d, 0x0, 0x7fa0000000000000, 0x7ff8000000000000, 0x0
+ r6ck_3d cmp.ne.d, 0x0, 0x7ff0000000000000, 0x7ff0000000000000, 0x0
+ r6ck_3d cmp.ne.d, 0x0, 0xfff0000000000000, 0xfff0000000000000, 0x0
+ r6ck_3d cmp.ne.d, 0x0, 0xab19546120965720, 0x92452014f194abc3, 0xffffffffffffffff
+
+ writemsg "[12] Test CMP.lt.s"
+ r6ck_3s cmp.lt.s, 0x0, 0x3f800000, 0x3f800000, 0x0
+ r6ck_3s cmp.lt.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.lt.s, 0x0, 0xbf800000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.lt.s, 0x0, 0x3f800000, 0xbf800000, 0x0
+ r6ck_3s cmp.lt.s, 0x0, 0xff800000, 0xbf800000, 0xffffffff
+ r6ck_3s cmp.lt.s, 0x0, 0xbf800000, 0x7f800000, 0xffffffff
+ r6ck_3s cmp.lt.s, 0x0, 0xbf800000, 0xff800000, 0x0
+ r6ck_3s cmp.lt.s, 0x0, 0x7f800000, 0xbf800000, 0x0
+
+ writemsg "[13] Test CMP.lt.d"
+ r6ck_3d cmp.lt.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
+ r6ck_3d cmp.lt.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.lt.d, 0x0, 0xbff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.lt.d, 0x0, 0x3ff0000000000000, 0xbff0000000000000, 0x0
+ r6ck_3d cmp.lt.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.lt.d, 0x0, 0xbff0000000000000, 0x7ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.lt.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0x0
+ r6ck_3d cmp.lt.d, 0x0, 0x7ff0000000000000, 0xbff0000000000000, 0x0
+
+ writemsg "[14] Test CMP.le.s"
+ r6ck_3s cmp.le.s, 0x0, 0x3f800000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.le.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.le.s, 0x0, 0xbf800000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.le.s, 0x0, 0x3f800000, 0xbf800000, 0x0
+ r6ck_3s cmp.le.s, 0x0, 0xff800000, 0xbf800000, 0xffffffff
+ r6ck_3s cmp.le.s, 0x0, 0xbf800000, 0x7f800000, 0xffffffff
+ r6ck_3s cmp.le.s, 0x0, 0xbf800000, 0xff800000, 0x0
+ r6ck_3s cmp.le.s, 0x0, 0x7f800000, 0xbf800000, 0x0
+
+ writemsg "[15] Test CMP.le.d"
+ r6ck_3d cmp.le.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.le.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.le.d, 0x0, 0xbff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.le.d, 0x0, 0x3ff0000000000000, 0xbff0000000000000, 0x0
+ r6ck_3d cmp.le.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.le.d, 0x0, 0xbff0000000000000, 0x7ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.le.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0x0
+ r6ck_3d cmp.le.d, 0x0, 0x7ff0000000000000, 0xbff0000000000000, 0x0
+
+ writemsg "[16] Test CMP.un.s"
+ r6ck_3s cmp.un.s, 0x0, 0x3f800000, 0x3f800000, 0x0
+ r6ck_3s cmp.un.s, 0x0, 0x3f800000, 0xbf800000, 0x0
+ r6ck_3s cmp.un.s, 0x0, 0x3f800000, 0x7fc00000, 0xffffffff
+ r6ck_3s cmp.un.s, 0x0, 0x7fc01234, 0x7fc00000, 0xffffffff
+ r6ck_3s cmp.un.s, 0x0, 0x7fc00000, 0x7fc00000, 0xffffffff
+ r6ck_3s cmp.un.s, 0x0, 0x3f800000, 0xff800000, 0x0
+ r6ck_3s cmp.un.s, 0x0, 0x3f800000, 0x7f800000, 0x0
+
+ writemsg "[17] Test CMP.un.d"
+ r6ck_3d cmp.un.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
+ r6ck_3d cmp.un.d, 0x0, 0x3ff0000000000000, 0xbff0000000000000, 0x0
+ r6ck_3d cmp.un.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.un.d, 0x0, 0x7fc0123400000000, 0x7ff8000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.un.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.un.d, 0x0, 0x3ff0000000000000, 0xfff0000000000000, 0x0
+ r6ck_3d cmp.un.d, 0x0, 0x3ff0000000000000, 0x7ff0000000000000, 0x0
+
+ writemsg "[18] Test CMP.or.s"
+ r6ck_3s cmp.or.s, 0x0, 0x3f800000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.or.s, 0x0, 0xbf800000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.or.s, 0x0, 0x3f800000, 0x7fc00000, 0x0
+ r6ck_3s cmp.or.s, 0x0, 0x7fc00000, 0x3f800000, 0x0
+ r6ck_3s cmp.or.s, 0x0, 0xffc00000, 0x3f800000, 0x0
+ r6ck_3s cmp.or.s, 0x0, 0x7fc01234, 0x7fc00000, 0x0
+ r6ck_3s cmp.or.s, 0x0, 0xff800000, 0x00000000, 0xffffffff
+ r6ck_3s cmp.or.s, 0x0, 0x00000000, 0x7f800000, 0xffffffff
+ r6ck_3s cmp.or.s, 0x0, 0x00000000, 0xff800000, 0xffffffff
+ r6ck_3s cmp.or.s, 0x0, 0x7f800000, 0x00000000, 0xffffffff
+ r6ck_3s cmp.or.s, 0x0, 0x7f800000, 0x00000000, 0xffffffff
+
+ writemsg "[19] Test CMP.or.d"
+ r6ck_3d cmp.or.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.or.d, 0x0, 0xbff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.or.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0x0
+ r6ck_3d cmp.or.d, 0x0, 0x7ff8000000000000, 0x3ff0000000000000, 0x0
+ r6ck_3d cmp.or.d, 0x0, 0xfff8000000000000, 0x3ff0000000000000, 0x0
+ r6ck_3d cmp.or.d, 0x0, 0x7ff8123492134352, 0x7ff8000000000000, 0x0
+ r6ck_3d cmp.or.d, 0x0, 0xfff0000000000000, 0x0000000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.or.d, 0x0, 0x0000000000000000, 0x7ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.or.d, 0x0, 0x0000000000000000, 0xfff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.or.d, 0x0, 0x7ff0000000000000, 0x0000000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.or.d, 0x0, 0x7ff0000000000000, 0x0000000000000000, 0xffffffffffffffff
+
+ writemsg "[20] Test CMP.ueq.s"
+ r6ck_3s cmp.ueq.s, 0x0, 0x3f800000, 0x00000000, 0x0
+ r6ck_3s cmp.ueq.s, 0x0, 0x3f800000, 0x7fc00000, 0xffffffff
+ r6ck_3s cmp.ueq.s, 0x0, 0x7fc00000, 0x7fc00000, 0xffffffff
+ r6ck_3s cmp.ueq.s, 0x0, 0x3f800000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.ueq.s, 0x0, 0x00000000, 0x3f800000, 0x0
+ r6ck_3s cmp.ueq.s, 0x0, 0x80000000, 0x00000000, 0xffffffff
+ r6ck_3s cmp.ueq.s, 0x0, 0x7f800000, 0x7fc00000, 0xffffffff
+ r6ck_3s cmp.ueq.s, 0x0, 0xff800000, 0xff800000, 0xffffffff
+
+ writemsg "[21] Test CMP.ueq.d"
+ r6ck_3d cmp.ueq.d, 0x0, 0x3ff0000000000000, 0x0000000000000000, 0x0
+ r6ck_3d cmp.ueq.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.ueq.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.ueq.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.ueq.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0x0
+ r6ck_3d cmp.ueq.d, 0x0, 0x8000000000000000, 0x0000000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.ueq.d, 0x0, 0x7ff0000000000000, 0x7ff8000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.ueq.d, 0x0, 0xfff0000000000000, 0xfff0000000000000, 0xffffffffffffffff
+
+ writemsg "[22] Test CMP.une.s"
+ r6ck_3s cmp.une.s, 0x0, 0x3f800000, 0x3f800000, 0x0
+ r6ck_3s cmp.une.s, 0x0, 0x3f800000, 0x7fc00000, 0xffffffff
+ r6ck_3s cmp.une.s, 0x0, 0x7fc00000, 0x7fc00000, 0xffffffff
+ r6ck_3s cmp.une.s, 0x0, 0x3f800000, 0x3f800000, 0x0
+ r6ck_3s cmp.une.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.une.s, 0x0, 0x80000000, 0x00000000, 0x0
+ r6ck_3s cmp.une.s, 0x0, 0x7f800000, 0x7fc00000, 0xffffffff
+ r6ck_3s cmp.une.s, 0x0, 0xff800000, 0xff800000, 0x0
+
+ writemsg "[23] Test CMP.une.d"
+ r6ck_3d cmp.une.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
+ r6ck_3d cmp.une.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.une.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.une.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
+ r6ck_3d cmp.une.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.une.d, 0x0, 0x8000000000000000, 0x0000000000000000, 0x0
+ r6ck_3d cmp.une.d, 0x0, 0x7ff0000000000000, 0x7ff8000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.une.d, 0x0, 0xfff0000000000000, 0xfff0000000000000, 0x0
+
+ writemsg "[24] Test CMP.ult.s"
+ r6ck_3s cmp.ult.s, 0x0, 0x3f800000, 0x3f800000, 0x0
+ r6ck_3s cmp.ult.s, 0x0, 0x3f800000, 0x7fc00000, 0xffffffff
+ r6ck_3s cmp.ult.s, 0x0, 0x7fc00000, 0x7fc00000, 0xffffffff
+ r6ck_3s cmp.ult.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.ult.s, 0x0, 0xbf800000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.ult.s, 0x0, 0x3f800000, 0xbf800000, 0x0
+
+ writemsg "[25] Test CMP.ult.d"
+ r6ck_3d cmp.ult.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
+ r6ck_3d cmp.ult.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.ult.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.ult.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.ult.d, 0x0, 0xbff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.ult.d, 0x0, 0x3ff0000000000000, 0xbff0000000000000, 0x0
+
+ writemsg "[26] Test CMP.ule.s"
+ r6ck_3s cmp.ule.s, 0x0, 0x3f800000, 0x7fc00000, 0xffffffff
+ r6ck_3s cmp.ule.s, 0x0, 0x7fc00000, 0x7fc00000, 0xffffffff
+ r6ck_3s cmp.ule.s, 0x0, 0x3f800000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.ule.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.ule.s, 0x0, 0xbf800000, 0x3f800000, 0xffffffff
+ r6ck_3s cmp.ule.s, 0x0, 0x3f800000, 0xbf800000, 0x0
+ r6ck_3s cmp.ule.s, 0x0, 0x3f800000, 0xff800000, 0x0
+
+ writemsg "[27] Test CMP.ule.d"
+ r6ck_3d cmp.ule.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.ule.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.ule.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.ule.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.ule.d, 0x0, 0xbff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
+ r6ck_3d cmp.ule.d, 0x0, 0x3ff0000000000000, 0xbff0000000000000, 0x0
+ r6ck_3d cmp.ule.d, 0x0, 0x3ff0000000000000, 0xfff0000000000000, 0x0
+
+ writemsg "[28] Test rint.s"
+ r6ck_2s rint.s, 0x0, 0x3fbf10cb, 0x3f800000
+ r6ck_2s rint.s, 0x0, 0xb9011423, 0x0
+ r6ck_2s rint.s, 0x0, 0x43fa4687, 0x43fa8000
+ r6ck_2s rint.s, 0x0, 0x41380000, 0x41400000
+ r6ck_2s rint.s, 0x0, 0x3ff33333, 0x40000000
+
+ writemsg "[29] Test rint.d"
+ r6ck_2d rint.d, 0x0, 0x3ff1f9a6b50b0f28, 0x3ff0000000000000
+ r6ck_2d rint.d, 0x0, 0xbf543bf727136a40, 0x0
+ r6ck_2d rint.d, 0x0, 0x407f48d0e5604189, 0x407f500000000000
+ r6ck_2d rint.d, 0x0, 0x5b7c2d43b93b0a8c, 0x5b7c2d43b93b0a8c,
+
+ writemsg "[30] Test class.s"
+ r6ck_2s class.s, 0x0, 0x7f800010, 0x1
+ r6ck_2s class.s, 0x0, 0x7fc00000, 0x2
+ r6ck_2s class.s, 0x0, 0xff800000, 0x4
+ r6ck_2s class.s, 0x0, 0xbf800000, 0x8
+ r6ck_2s class.s, 0x0, 0x80000001, 0x10
+ r6ck_2s class.s, 0x0, 0x80000000, 0x20
+ r6ck_2s class.s, 0x0, 0x7f800000, 0x40
+ r6ck_2s class.s, 0x0, 0x3f800000, 0x80
+ r6ck_2s class.s, 0x0, 0x00000001, 0x100
+ r6ck_2s class.s, 0x0, 0x00000000, 0x200
+
+ writemsg "[31] Test class.d"
+ r6ck_2d class.d, 0x0, 0x7ff0000000000010, 0x1
+ r6ck_2d class.d, 0x0, 0x7ff8000000000000, 0x2
+ r6ck_2d class.d, 0x0, 0xfff0000000000000, 0x4
+ r6ck_2d class.d, 0x0, 0xbff0000000000000, 0x8
+ r6ck_2d class.d, 0x0, 0x8000000000000001, 0x10
+ r6ck_2d class.d, 0x0, 0x8000000000000000, 0x20
+ r6ck_2d class.d, 0x0, 0x7ff0000000000000, 0x40
+ r6ck_2d class.d, 0x0, 0x3ff0000000000000, 0x80
+ r6ck_2d class.d, 0x0, 0x0000000000000001, 0x100
+ r6ck_2d class.d, 0x0, 0x0000000000000000, 0x200
+
+ writemsg "[32] Test min.s"
+ r6ck_3s min.s, 0x0, 0x3f800000, 0x0, 0x0
+ r6ck_3s min.s, 0x0, 0x0, 0x3f800000, 0x0
+ r6ck_3s min.s, 0x0, 0x7f800000, 0x3f800000, 0x3f800000
+ r6ck_3s min.s, 0x0, 0x3f800000, 0x7f800000, 0x3f800000
+ r6ck_3s min.s, 0x0, 0xff800000, 0xbf800000, 0xff800000
+ r6ck_3s min.s, 0x0, 0xbf800000, 0xff800000, 0xff800000
+ r6ck_3s min.s, 0x0, 0x7fffffff, 0x3f800000, 0x3f800000
+ r6ck_3s min.s, 0x0, 0x3f800000, 0x7fffffff, 0x3f800000
+
+ writemsg "[33] Test min.d"
+ r6ck_3d min.d, 0x0, 0x3ff0000000000000, 0x0, 0x0
+ r6ck_3d min.d, 0x0, 0x0, 0x3ff0000000000000, 0x0
+ r6ck_3d min.d, 0x0, 0x7ff0000000000000, 0x3ff0000000000000, 0x3ff0000000000000
+ r6ck_3d min.d, 0x0, 0x3ff0000000000000, 0x7ff0000000000000, 0x3ff0000000000000
+ r6ck_3d min.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xfff0000000000000
+ r6ck_3d min.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0xfff0000000000000
+ r6ck_3d min.d, 0x0, 0x7fffffffffffffff, 0x3ff0000000000000, 0x3ff0000000000000
+ r6ck_3d min.d, 0x0, 0x3ff0000000000000, 0x7fffffffffffffff, 0x3ff0000000000000
+
+ writemsg "[34] Test max.s"
+ r6ck_3s max.s, 0x0, 0x3f800000, 0x0, 0x3f800000
+ r6ck_3s max.s, 0x0, 0x0, 0x3f800000, 0x3f800000
+ r6ck_3s max.s, 0x0, 0x7f800000, 0x3f800000, 0x7f800000
+ r6ck_3s max.s, 0x0, 0x3f800000, 0x7f800000, 0x7f800000
+ r6ck_3s max.s, 0x0, 0xff800000, 0xbf800000, 0xbf800000
+ r6ck_3s max.s, 0x0, 0xbf800000, 0xff800000, 0xbf800000
+ r6ck_3s max.s, 0x0, 0x7fffffff, 0x3f800000, 0x3f800000
+ r6ck_3s max.s, 0x0, 0x3f800000, 0x7fffffff, 0x3f800000
+
+ writemsg "[35] Test max.d"
+ r6ck_3d max.d, 0x0, 0x3ff0000000000000, 0x0, 0x3ff0000000000000
+ r6ck_3d max.d, 0x0, 0x0, 0x3ff0000000000000, 0x3ff0000000000000
+ r6ck_3d max.d, 0x0, 0x7ff0000000000000, 0x3ff0000000000000, 0x7ff0000000000000
+ r6ck_3d max.d, 0x0, 0x3ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000
+ r6ck_3d max.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xbff0000000000000
+ r6ck_3d max.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0xbff0000000000000
+ r6ck_3d max.d, 0x0, 0x7fffffffffffffff, 0x3ff0000000000000, 0x3ff0000000000000
+ r6ck_3d max.d, 0x0, 0x3ff0000000000000, 0x7fffffffffffffff, 0x3ff0000000000000
+
+ writemsg "[36] Test mina.s"
+ r6ck_3s mina.s, 0x0, 0x3f800000, 0x0, 0x0
+ r6ck_3s mina.s, 0x0, 0x0, 0x3f800000, 0x0
+ r6ck_3s mina.s, 0x0, 0x7f800000, 0x3f800000, 0x3f800000
+ r6ck_3s mina.s, 0x0, 0x3f800000, 0x7f800000, 0x3f800000
+ r6ck_3s mina.s, 0x0, 0xff800000, 0xbf800000, 0xbf800000
+ r6ck_3s mina.s, 0x0, 0xbf800000, 0xff800000, 0xbf800000
+ r6ck_3s mina.s, 0x0, 0x7fffffff, 0x3f800000, 0x3f800000
+ r6ck_3s mina.s, 0x0, 0x3f800000, 0x7fffffff, 0x3f800000
+ r6ck_3s mina.s, 0x0, 0xc0000000, 0x3f800000, 0x3f800000
+ r6ck_3s mina.s, 0x0, 0x3f800000, 0xc0000000, 0x3f800000
+
+ writemsg "[37] Test mina.d"
+ r6ck_3d mina.d, 0x0, 0x3ff0000000000000, 0x0, 0x0
+ r6ck_3d mina.d, 0x0, 0x0, 0x3ff0000000000000, 0x0
+ r6ck_3d mina.d, 0x0, 0x7ff0000000000000, 0x3ff0000000000000, 0x3ff0000000000000
+ r6ck_3d mina.d, 0x0, 0x3ff0000000000000, 0x7ff0000000000000, 0x3ff0000000000000
+ r6ck_3d mina.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xbff0000000000000
+ r6ck_3d mina.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0xbff0000000000000
+ r6ck_3d mina.d, 0x0, 0x7fffffffffffffff, 0x3ff0000000000000, 0x3ff0000000000000
+ r6ck_3d mina.d, 0x0, 0x3ff0000000000000, 0x7fffffffffffffff, 0x3ff0000000000000
+ r6ck_3d mina.d, 0x0, 0xc000000000000000, 0x3ff0000000000000, 0x3ff0000000000000
+ r6ck_3d mina.d, 0x0, 0x3ff0000000000000, 0xc000000000000000, 0x3ff0000000000000
+
+ writemsg "[38] Test maxa.s"
+ r6ck_3s maxa.s, 0x0, 0x3f800000, 0x0, 0x3f800000
+ r6ck_3s maxa.s, 0x0, 0x0, 0x3f800000, 0x3f800000
+ r6ck_3s maxa.s, 0x0, 0x7f800000, 0x3f800000, 0x7f800000
+ r6ck_3s maxa.s, 0x0, 0x3f800000, 0x7f800000, 0x7f800000
+ r6ck_3s maxa.s, 0x0, 0xff800000, 0xbf800000, 0xff800000
+ r6ck_3s maxa.s, 0x0, 0xbf800000, 0xff800000, 0xff800000
+ r6ck_3s maxa.s, 0x0, 0x7fffffff, 0x3f800000, 0x3f800000
+ r6ck_3s maxa.s, 0x0, 0x3f800000, 0x7fffffff, 0x3f800000
+ r6ck_3s maxa.s, 0x0, 0xc0000000, 0x3f800000, 0xc0000000
+ r6ck_3s maxa.s, 0x0, 0x3f800000, 0xc0000000, 0xc0000000
+
+ writemsg "[39] Test maxa.d"
+ r6ck_3d maxa.d, 0x0, 0x3ff0000000000000, 0x0, 0x3ff0000000000000
+ r6ck_3d maxa.d, 0x0, 0x0, 0x3ff0000000000000, 0x3ff0000000000000
+ r6ck_3d maxa.d, 0x0, 0x7ff0000000000000, 0x3ff0000000000000, 0x7ff0000000000000
+ r6ck_3d maxa.d, 0x0, 0x3ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000
+ r6ck_3d maxa.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xfff0000000000000
+ r6ck_3d maxa.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0xfff0000000000000
+ r6ck_3d maxa.d, 0x0, 0x7fffffffffffffff, 0x3ff0000000000000, 0x3ff0000000000000
+ r6ck_3d maxa.d, 0x0, 0x3ff0000000000000, 0x7fffffffffffffff, 0x3ff0000000000000
+ r6ck_3d maxa.d, 0x0, 0xc000000000000000, 0x3ff0000000000000, 0xc000000000000000
+ r6ck_3d maxa.d, 0x0, 0x3ff0000000000000, 0xc000000000000000, 0xc000000000000000
+
+ writemsg "[40] Test sel.s"
+ r6ck_3s sel.s, 0x0, 0xabcdef12, 0x12345678, 0xabcdef12
+ r6ck_3s sel.s, 0x1, 0xdeadbeef, 0xcafe1234, 0xcafe1234
+ r6ck_3s sel.s, 0xfffffffe, 0xbadcafe0, 0x12345678, 0xbadcafe0
+ r6ck_3s sel.s, 0xffffffff, 0xdeadbeef, 0xcadf00ab, 0xcadf00ab
+
+ writemsg "[41] Test sel.d"
+ r6ck_3d sel.d, 0x0, 0xabcdef123456789, 0x12345678abcdefa, 0xabcdef123456789
+ r6ck_3d sel.d, 0x1, 0xdeadbeef1534567, 0xcafe12340145279, 0xcafe12340145279
+ r6ck_3d sel.d, 0xfffffffffffffffe, 0xbadcafe00efacdab, 0x1234567887654321, 0xbadcafe00efacdab
+ r6ck_3d sel.d, 0xffffffffffffffff, 0xdeadbeeffeebdaed, 0xcadf00abba00fdac, 0xcadf00abba00fdac
+
+ writemsg "[42] Test seleqz.s"
+ r6ck_3s seleqz.s, 0x0, 0x1234abcd, 0x0, 0x1234abcd
+ r6ck_3s seleqz.s, 0x0, 0xabcdef01, 0x1, 0x0
+ r6ck_3s seleqz.s, 0x0, 0xffeebbcc, 0xfffffffe, 0xffeebbcc
+ r6ck_3s seleqz.s, 0x0, 0x12345678, 0xffffffff, 0
+
+ writemsg "[43] Test seleqz.d"
+ r6ck_3d seleqz.d, 0x0, 0x1234abcddcba4321, 0x0, 0x1234abcddcba4321
+ r6ck_3d seleqz.d, 0x0, 0xabcdef0110fedcba, 0x1, 0x0
+ r6ck_3d seleqz.d, 0x0, 0xffeebbccccbbeeff, 0xfffffffffffffffe, 0xffeebbccccbbeeff
+ r6ck_3d seleqz.d, 0x0, 0x1234567887654321, 0xffffffffffffffff, 0x0
+
+ writemsg "[44] Test selnez.s"
+ r6ck_3s selnez.s, 0x0, 0x1234abcd, 0x0, 0x0
+ r6ck_3s selnez.s, 0x0, 0xabcdef01, 0x1, 0xabcdef01
+ r6ck_3s selnez.s, 0x0, 0xffeebbcc, 0xfffffffe, 0x0
+ r6ck_3s selnez.s, 0x0, 0x12345678, 0xffffffff, 0x12345678
+
+ writemsg "[45] Test selnez.d"
+ r6ck_3d selnez.d, 0x0, 0x1234abcddcba4321, 0x0, 0x0
+ r6ck_3d selnez.d, 0x0, 0xabcdef0110fedcba, 0x1, 0xabcdef0110fedcba
+ r6ck_3d selnez.d, 0x0, 0xffeebbccccbbeeff, 0xfffffffffffffffe, 0x0
+ r6ck_3d selnez.d, 0x0, 0x1234567887654321, 0xffffffffffffffff, 0x1234567887654321
+
+ writemsg "[46] Test bc1eqz"
+ li $10, 0x01
+ mtc1 $10, $f2
+ mtc1 $0, $f4
+ bc1eqz $f2, L1
+ nop
+ bc1eqz $f4, L2
+ nop
+ fail
+
+L1:
+ fail
+
+L2:
+ writemsg "[47] Test bc1nez"
+ bc1nez $f4, L3
+ nop
+ bc1nez $f2, L4
+ nop
+ fail
+
+L3:
+ fail
+
+L4:
+ pass
+
+ .end DIAG
diff --git a/sim/testsuite/mips/r6-llsc-dp.s b/sim/testsuite/mips/r6-llsc-dp.s
new file mode 100644
index 0000000..1eec3e4
--- /dev/null
+++ b/sim/testsuite/mips/r6-llsc-dp.s
@@ -0,0 +1,57 @@
+# mips64 specific r6 tests - paired LL/SC variants
+# mach: mips64r6
+# as: -mabi=eabi
+# ld: -N -Ttext=0x80010000 -Tdata=0x80020000
+# output: *\\npass\\n
+
+ .include "testutils.inc"
+ .include "utils-r6.inc"
+
+ .data
+ .align 16
+test_data:
+ .word 0xaaaaaaaa
+ .word 0xbbbbbbbb
+ .word 0xcccccccc
+ .word 0xdddddddd
+end_check:
+ .byte 0
+ .byte 0
+ .byte 0
+ .byte 0x1
+
+ .text
+
+ setup
+
+ .ent DIAG
+DIAG:
+ writemsg "[1] Test LLWP"
+ llwp $2, $3, test_data
+ checkpair_dword $2, $3, test_data, end_check
+
+ sll $2, $2, 1
+ srl $3, $3, 1
+ move $s0, $2
+
+ scwp $2, $3, test_data
+ check32 $2, 1
+ checkpair_dword $s0, $3, test_data, end_check
+ writemsg "[2] Test SCWP, done"
+
+ writemsg "[3] Test LLDP"
+ lldp $2, $3, test_data
+ checkpair_qword $2, $3, test_data, end_check
+
+ dsll $2, $2, 1
+ dsrl $3, $3, 1
+ move $s0, $2
+
+ scdp $2, $3, test_data
+ check32 $2, 1
+ checkpair_qword $s0, $3, test_data, end_check
+ writemsg "[4] Test SCDP, done"
+
+ pass
+
+ .end DIAG
diff --git a/sim/testsuite/mips/r6-llsc-wp.s b/sim/testsuite/mips/r6-llsc-wp.s
new file mode 100644
index 0000000..55ad924
--- /dev/null
+++ b/sim/testsuite/mips/r6-llsc-wp.s
@@ -0,0 +1,41 @@
+# mips32 specific r6 tests - paired LL/SC variants
+# mach: mips32r6
+# as: -mabi=eabi
+# ld: -N -Ttext=0x80010000 -Tdata=0x80020000
+# output: *\\npass\\n
+
+ .include "testutils.inc"
+ .include "utils-r6.inc"
+
+ .data
+ .align 8
+test_data:
+ .word 0xaaaaaaaa
+ .word 0xbbbbbbbb
+end_check:
+ .byte 0
+ .byte 0
+ .byte 0
+ .byte 0x1
+ .text
+
+ setup
+
+ .ent DIAG
+DIAG:
+ writemsg "[1] Test LLWP"
+ llwp $2, $3, test_data
+ checkpair_dword $2, $3, test_data, end_check
+
+ sll $2, $2, 1
+ srl $3, $3, 1
+ move $s0, $2
+
+ scwp $2, $3, test_data
+ check32 $2, 1
+ checkpair_dword $s0, $3, test_data, end_check
+ writemsg "[2] Test SCWP, done"
+
+pass
+
+ .end DIAG
diff --git a/sim/testsuite/mips/r6-removed.csv b/sim/testsuite/mips/r6-removed.csv
new file mode 100644
index 0000000..5f2285c
--- /dev/null
+++ b/sim/testsuite/mips/r6-removed.csv
@@ -0,0 +1,68 @@
+BC1F,0x45000000
+BEQL,0x50000000
+BGEZAL,0x04310000
+BGEZALL,0x04130000
+BGEZL,0x04030000
+BLTZALL,0x04120000
+BLTZL,0x04020000
+BNEL,0x54000000
+C.DEQ.D,0x44000030
+CACHE,0xbc000000
+CVT.PS.S,0x46000026
+CVT.S.PL,0x46c00028
+CVT.S.PU,0x46c00020
+DCLO,0x70000025
+DCLZ,0x70000024
+LDL,0x68000000
+LDR,0x6c000000
+LDXC1,0x4c000001
+LL,0xc0000000
+LLD,0xd0000000
+LUXC1,0x4c000005
+LWL,0x88000000
+LWLE,0x7c000019
+LWR,0x98000000
+LWRE,0x7c00001a
+LWXC1,0x4c000000
+MADD,0x70000000
+MADD.D,0x4c000020
+MADDU,0x70000001
+MOVF,0x00000001
+MOVF.D,0x44000011
+MOVN.D,0x44000013
+MOVT,0x00010001
+MOVT.D,0x44010011
+MOVZ.D,0x44000012
+MSUB,0x70000004
+MSUB.D,0x4c000028
+MSUBU,0x70000005
+MUL,0x70000002
+NEG.S,0x44000007
+NMADD.D,0x4c000030
+NMSUB.D,0x4c000038
+PLL.PS,0x46c0002c
+PLU.PS,0x46c0002d
+PREF,0xcc000000
+PREFX,0x4c00000f
+PUL.PS,0x46c0005e
+PUU.PS,0x46c0002f
+RINT.fmt,0x4400001a
+SC,0xe0000000
+SCD,0xf0000000
+SDBBP,0x7000003f
+SDL,0xb0000000
+SDR,0xb4000000
+SDXC1,0x4c000009
+SUB.D,0x44000001
+SUXC1,0x4c00000d
+SWL,0xa8000000
+SWLE,0x7c000021
+SWR,0xb8000000
+SWRE,0x7c000022
+SWXC1,0x4c000008
+TEQI,0x040c0000
+TGEI,0x04080000
+TGEIU,0x04090000
+TLTI,0x040a0000
+TLTIU,0x040b0000
+TNEI,0x040c0000
diff --git a/sim/testsuite/mips/r6-removed.s b/sim/testsuite/mips/r6-removed.s
new file mode 100644
index 0000000..4f2605f
--- /dev/null
+++ b/sim/testsuite/mips/r6-removed.s
@@ -0,0 +1,18 @@
+# Tests the instructions removed in R6 are correctly invalidated
+# mach: mips32r6 mips64r6
+# as: -mabi=eabi
+# ld: -N -Ttext=0x80010000
+# output: ReservedInstruction at PC = *\nprogram stopped with signal 4 (Illegal instruction).\n
+# xerror:
+
+ .include "testutils.inc"
+ .include "r6-removed.inc"
+
+ setup
+
+ .set noreorder
+ .ent DIAG
+DIAG:
+ removed_instr
+ fail
+ .end DIAG
diff --git a/sim/testsuite/mips/r6.s b/sim/testsuite/mips/r6.s
new file mode 100644
index 0000000..d30ffff
--- /dev/null
+++ b/sim/testsuite/mips/r6.s
@@ -0,0 +1,163 @@
+# mips r6 tests (non FPU)
+# mach: mips32r6 mips64r6
+# as: -mabi=eabi
+# ld: -N -Ttext=0x80010000
+# output: *\\npass\\n
+
+ .include "testutils.inc"
+ .include "utils-r6.inc"
+
+ setup
+
+ .data
+dval1: .word 0xabcd1234
+dval2: .word 0x1234eeff
+ .fill 248,1,0
+dval3: .word 0x55555555
+ .fill 260,1,0
+dval4: .word 0xaaaaaaaa
+ .text
+
+ .set noreorder
+
+ .ent DIAG
+DIAG:
+
+ writemsg "[1] Test MUL"
+ r6ck_2r mul, 7, 9, 63
+ r6ck_2r mul, -7, -9, 63
+ r6ck_2r mul, 61, -11, -671
+ r6ck_2r mul, 1001, 1234, 1235234
+ r6ck_2r mul, 123456789, 999999, 0x7eb1e22b
+ r6ck_2r mul, 0xaaaabbbb, 0xccccdddd, 0x56787f6f
+
+ writemsg "[2] Test MUH"
+ r6ck_2r muh, 61, -11, 0xffffffff
+ r6ck_2r muh, 1001, 1234, 0
+ r6ck_2r muh, 123456789, 999999, 0x7048
+ r6ck_2r muh, 0xaaaabbbb, 0xccccdddd, 0x111107f7
+
+ writemsg "[3] Test MULU"
+ r6ck_2r mulu, 7, 9, 63
+ r6ck_2r mulu, -7, -9, 63
+ r6ck_2r mulu, 61, -11, -671
+ r6ck_2r mulu, 1001, 1234, 1235234
+ r6ck_2r mulu, 123456789, 999999, 0x7eb1e22b
+ r6ck_2r mulu, 0xaaaabbbb, 0xccccdddd, 0x56787f6f
+
+ writemsg "[4] Test MUHU"
+ r6ck_2r muhu, 1001, 1234, 0
+ r6ck_2r muhu, 123456789, 999999, 0x7048
+ r6ck_2r muhu, 0xaaaabbbb, 0xccccdddd, 0x8888a18f
+ r6ck_2r muhu, 0xaaaabbbb, 0xccccdddd, 0x8888a18f
+
+ writemsg "[5] Test DIV"
+ r6ck_2r div, 10001, 10, 1000
+ r6ck_2r div, -123456, 560, -220
+ r6ck_2r div, 9, 100, 0
+
+ writemsg "[6] Test MOD"
+ r6ck_2r mod, 10001, 10, 1
+ r6ck_2r mod, -123456, 560, 0xffffff00
+ r6ck_2r mod, 9, 100, 9
+
+ writemsg "[7] Test DIVU"
+ r6ck_2r divu, 10001, 10, 1000
+ r6ck_2r divu, -123456, 560, 0x750674
+ r6ck_2r divu, 9, 100, 0
+ r6ck_2r divu, 0xaaaabbbb, 3, 0x38e393e9
+
+ writemsg "[8] Test MODU"
+ r6ck_2r modu, 10001, 10, 1
+ r6ck_2r modu, -123456, 560, 0
+ r6ck_2r modu, 9, 100, 9
+ r6ck_2r modu, 0xaaaabbbb, 5, 4
+
+ writemsg "[9] Test LSA"
+ r6ck_2r1i lsa, 1, 2, 2, 6
+ r6ck_2r1i lsa, 0x8000, 0xa000, 1, 0x1a000
+ r6ck_2r1i lsa, 0x82, 0x2000068, 4, 0x2000888
+
+ writemsg "[10] Test AUI"
+ r6ck_1r1i aui, 0x0000c0de, 0xdead, 0xdeadc0de
+ r6ck_1r1i aui, 0x00005678, 0x1234, 0x12345678
+ r6ck_1r1i aui, 0x0000eeff, 0xabab, 0xababeeff
+
+ writemsg "[11] Test SELEQZ"
+ r6ck_2r seleqz, 0x1234, 0, 0x1234
+ r6ck_2r seleqz, 0x1234, 4, 0
+ r6ck_2r seleqz, 0x80010001, 0, 0x80010001
+
+ writemsg "[12] Test SELNEZ"
+ r6ck_2r selnez, 0x1234, 0, 0
+ r6ck_2r selnez, 0x1234, 1, 0x1234
+ r6ck_2r selnez, 0x80010001, 0xffffffff, 0x80010001
+
+ writemsg "[13] Test ALIGN"
+ r6ck_2r1i align, 0xaabbccdd, 0xeeff0011, 1, 0xff0011aa
+ r6ck_2r1i align, 0xaabbccdd, 0xeeff0011, 3, 0x11aabbcc
+
+ writemsg "[14] Test BITSWAP"
+ r6ck_1r bitswap, 0xaabbccdd, 0x55dd33bb
+ r6ck_1r bitswap, 0x11884422, 0x88112244
+
+ writemsg "[15] Test CLZ"
+ r6ck_1r clz, 0x00012340, 15
+ r6ck_1r clz, 0x80012340, 0
+ r6ck_1r clz, 0x40012340, 1
+
+ writemsg "[16] Test CLO"
+ r6ck_1r clo, 0x00123050, 0
+ r6ck_1r clo, 0xff123050, 8
+ r6ck_1r clo, 0x8f123050, 1
+
+ writemsg "[17] Test ADDIUPC"
+ jal GetPC
+ nop
+ addiu $4, $6, 8
+ addiupc $5, 4
+ fp_assert $4, $5
+
+ writemsg "[18] Test AUIPC"
+ jal GetPC
+ nop
+ addiu $4, $6, 8
+ aui $4, $4, 8
+ auipc $5, 8
+ fp_assert $4, $5
+
+ writemsg "[19] Test ALUIPC"
+ jal GetPC
+ nop
+ addiu $4, $6, 16
+ aui $4, $4, 8
+ li $7, 0xffff0000
+ and $4, $4, $7
+ aluipc $5, 8
+ fp_assert $4, $5
+
+ writemsg "[20] Test LWPC"
+ lw $5, dval1
+ lwpc $4, dval1
+ fp_assert $4, $5
+ lw $5, dval2
+ lwpc $4, dval2
+ fp_assert $4, $5
+
+ writemsg "[21] Test LL"
+ lw $5, dval2
+ la $3, dval3
+ ll $4, -252($3)
+ fp_assert $4, $5
+
+ writemsg "[22] Test SC"
+ ll $4, -252($3)
+ li $4, 0xafaf
+ sc $4, -252($3)
+ lw $5, dval2
+ li $4, 0xafaf
+ fp_assert $4, $5
+
+ pass
+
+ .end DIAG
diff --git a/sim/testsuite/mips/testutils.inc b/sim/testsuite/mips/testutils.inc
index 14d31e8..1f64ba7 100644
--- a/sim/testsuite/mips/testutils.inc
+++ b/sim/testsuite/mips/testutils.inc
@@ -148,3 +148,58 @@ _dowrite:
checkreg \reg, $1
.set pop
.endm
+
+
+ # Check hi-lo register pair against data stored at base+o1 and base+o2
+ # Clobbers $1 - $5
+ .macro checkpair lo, hi, base, w, o1, o2
+ move $2, \lo
+ move $3, \hi
+ .set noat
+ la $1, \base
+ l\w $4, \o1($1)
+ l\w $5, \o2($1)
+ .set at
+ checkreg $2, $4
+ checkreg $3, $5
+ .endm
+
+ .macro checkpair_le_d lo, hi, base
+ checkpair \lo, \hi, \base, w, 0, 4
+ .endm
+
+ .macro checkpair_be_d lo, hi, base
+ checkpair \lo, \hi, \base, w, 4, 0
+ .endm
+
+ .macro checkpair_le_q lo, hi, base
+ checkpair \lo, \hi, \base, d, 0, 8
+ .endm
+
+ .macro checkpair_be_q lo, hi, base
+ checkpair \lo, \hi, \base, d, 8, 0
+ .endm
+
+ # Endian-ness for comparison is determined by reading a word at ec
+ .macro checkpair_xendian lo, hi, base, ec, w
+ .set noat
+ lw $1, \ec
+ andi $1, $1, 0x1
+ # check endianess
+ beqz $1, 2f
+ .set at
+1: # big endian
+ checkpair_be_\w \lo, \hi, \base
+ b 3f
+2: # little endian
+ checkpair_le_\w \lo, \hi, \base
+3:
+ .endm
+
+ .macro checkpair_qword lo, hi, base, oe
+ checkpair_xendian \lo, \hi, \base, \oe, q
+ .endm
+
+ .macro checkpair_dword lo, hi, base, oe
+ checkpair_xendian \lo, \hi, \base, \oe, d
+ .endm
diff --git a/sim/testsuite/mips/utils-r6.inc b/sim/testsuite/mips/utils-r6.inc
new file mode 100644
index 0000000..b5c88e5
--- /dev/null
+++ b/sim/testsuite/mips/utils-r6.inc
@@ -0,0 +1,150 @@
+ .macro fp_assert a, b
+ beq \a, \b, 1f
+ nop
+ j _fail
+ nop
+1:
+ .endm
+
+ .macro r6ck_1r inst, a, ret
+ li $4, \a
+ li $6, \ret
+ \inst $7, $4
+ fp_assert $6, $7
+ .endm
+
+ .macro r6ck_1dr inst, a, ret
+ ld $4, \a
+ ld $6, \ret
+ \inst $7, $4
+ fp_assert $6, $7
+ .endm
+
+ .macro r6ck_2r inst, a, b, ret
+ li $4, \a
+ li $5, \b
+ li $6, \ret
+ \inst $7, $4, $5
+ fp_assert $6, $7
+ .endm
+
+ .macro r6ck_2dr inst, a, b, ret
+ ld $4, \a
+ ld $5, \b
+ ld $6, \ret
+ \inst $7, $4, $5
+ fp_assert $6, $7
+ .endm
+
+ .macro r6ck_2dr1i inst, a, b, imm, ret
+ ld $4, \a
+ ld $5, \b
+ ld $6, \ret
+ \inst $7, $4, $5, \imm
+ fp_assert $6, $7
+ .endm
+
+ .macro r6ck_1r1i inst, a, imm, ret
+ li $4, \a
+ li $6, \ret
+ \inst $7, $4, \imm
+ fp_assert $6, $7
+ .endm
+
+ .macro r6ck_1dr1i inst, a, imm, ret
+ ld $4, \a
+ ld $6, \ret
+ \inst $7, $4, \imm
+ fp_assert $6, $7
+ .endm
+
+ .macro r6ck_0dr1i inst, a, imm, ret
+ ld $4, \a
+ ld $6, \ret
+ \inst $4, $4, \imm
+ fp_assert $6, $4
+ .endm
+
+ .macro r6ck_2r1i inst, a, b, imm, ret
+ li $4, \a
+ li $5, \b
+ li $6, \ret
+ \inst $7, $4, $5, \imm
+ fp_assert $6, $7
+ .endm
+
+ .macro r6ck_3s inst, a, b, c, ret
+ li $4, \a
+ li $5, \b
+ li $6, \c
+ li $7, \ret
+ mtc1 $4, $f2
+ mtc1 $5, $f4
+ mtc1 $6, $f6
+ \inst $f2, $f4, $f6
+ mfc1 $8, $f2
+ fp_assert $7, $8
+ .endm
+
+ .macro r6ck_2s inst, a, b, ret
+ li $4, \a
+ li $5, \b
+ li $6, \ret
+ mtc1 $4, $f2
+ mtc1 $5, $f4
+ \inst $f2, $f4
+ mfc1 $7, $f2
+ fp_assert $6, $7
+ .endm
+
+ .macro r6ck_2d inst, a, b, ret
+ .data
+1: .dword \a
+2: .dword \b
+3: .dword \ret
+ .text
+ la $4, 1b
+ la $5, 2b
+ la $6, 3b
+ ldc1 $f2, 0($4)
+ ldc1 $f4, 0($5)
+ lw $7, 0($6)
+ lw $8, 4($6)
+ \inst $f2, $f4
+
+ #simulate dmfc1
+ mfhc1 $9, $f2
+ mfc1 $10, $f2
+ fp_assert $7, $9
+ fp_assert $8, $10
+ .endm
+
+ .macro r6ck_3d inst, a, b, c, ret
+ .data
+1: .dword \a
+2: .dword \b
+3: .dword \c
+4: .dword \ret
+ .text
+ la $4, 1b
+ la $5, 2b
+ la $6, 3b
+ la $2, 4b
+ ldc1 $f2, 0($4)
+ ldc1 $f4, 0($5)
+ ldc1 $f6, 0($6)
+ lw $7, 0($2)
+ lw $8, 4($2)
+ \inst $f2, $f4, $f6
+
+ #simulate dmfc1
+ mfhc1 $9, $f2
+ mfc1 $10, $f2
+ fp_assert $7, $9
+ fp_assert $8, $10
+ .endm
+
+.text
+GetPC:
+ move $6, $ra
+ jr $ra
generated by cgit v1.1 at 2024-08-27 10:35:52 +0000