diff options
Diffstat (limited to 'sim/testsuite/sim/frv/interrupts/fp_exception.cgs')
| -rw-r--r-- | sim/testsuite/sim/frv/interrupts/fp_exception.cgs | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception.cgs index 710b5ba..ad5f7e4 100644 --- a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs +++ b/sim/testsuite/sim/frv/interrupts/fp_exception.cgs @@ -16,6 +16,24 @@ align: set_gr_addr pack,gr10 flush_data_cache gr10 + ; Make the the source register number odd at badst. We can't simply + ; code an odd register number because the assembler will catch the + ; error. + set_gr_mem badst,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,badst + set_gr_addr badst,gr10 + flush_data_cache gr10 + + ; Make the the dest register number odd at ld. We can't simply + ; code an odd register number because the assembler will catch the + ; error. + set_gr_mem badld,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,badld + set_gr_addr badld,gr10 + flush_data_cache gr10 + and_spr_immed -4081,tbr ; clear tbr.tt set_gr_spr tbr,gr17 inc_gr_immed 0x070,gr17 ; address of exception handler @@ -31,12 +49,12 @@ align: set_gr_immed 0,gr15 set_spr_addr ok3,lr - stdfi fr1,@(sp,0) ; misaligned reg -- slot I0 +badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0 test_gr_immed 1,gr15 set_spr_addr ok4,lr nop.p - lddfi @(sp,0),fr9 ; misaligned reg -- slot I1 +badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1 test_gr_immed 2,gr15 set_spr_addr ok5,lr |