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Diffstat (limited to 'sim/rx/ChangeLog')
| -rw-r--r-- | sim/rx/ChangeLog | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/sim/rx/ChangeLog b/sim/rx/ChangeLog index 25dc711..ff3c808 100644 --- a/sim/rx/ChangeLog +++ b/sim/rx/ChangeLog @@ -1,3 +1,30 @@ +2010-07-27 DJ Delorie <dj@redhat.com> + + * README.txt: New. + * config.h (CYCLE_ACCURATE, CYCLE_STATS): New. + * configure.in (--enable-cycle-accurate, --enable-cycle-stats): + New. Default to enabled. + * configure: Regenerate. + + * cpu.h (regs_type): Add cycle tracking info. + (reset_pipeline_stats): Declare. + (halt_pipeline_stats): Declare. + (pipeline_stats): Declare. + * main.c (done): Call pipeline_stats(). + * mem.h (rx_mem_ptr): Moved to here ... + * mem.c (mem_ptr): ... from here. Rename throughout. + (mem_put_byte): Move LEDs to Port A. Add Port B to control cycle + statistics. Move UART to SCI4. + (mem_put_hi): Add TPU 1-2. TPU 1 and 2 count CPU cycles. + * reg.c (init_regs): Set Rt reg to -1 (no reg). + * rx.c: Add cycle counting and statistics throughout. + (rx_get_byte): Optimize for speed. + (decode_opcode): Likewise. + (reset_pipeline_stats): New. + (halt_pipeline_stats): New. + (pipeline_stats): New. + * trace.c (sim_disasm_one): Print cycle count. + 2010-07-07 Kevin Buettner <kevinb@redhat.com> * gdb-if.c (sim_store_register): Add case for sim_rx_acc_regnum. |