diff options
Diffstat (limited to 'sim/ppc/e500.igen')
| -rw-r--r-- | sim/ppc/e500.igen | 1274 |
1 files changed, 637 insertions, 637 deletions
diff --git a/sim/ppc/e500.igen b/sim/ppc/e500.igen index 5b9c553..dce1865 100644 --- a/sim/ppc/e500.igen +++ b/sim/ppc/e500.igen @@ -37,8 +37,8 @@ } while (0) # Schedule an instruction that takes 2 integer register and produces a special purpose output register plus an integer output register -void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr, const unsigned32 out_mask, const unsigned32 in_mask, const unsigned nSPR - const unsigned32 int_mask = out_mask | in_mask; +void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr, const uint32_t out_mask, const uint32_t in_mask, const unsigned nSPR + const uint32_t int_mask = out_mask | in_mask; model_busy *busy_ptr; while ((model_ptr->int_busy & int_mask) != 0 || model_ptr->spr_busy[nSPR] != 0) { @@ -60,23 +60,23 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr # # SPE Modulo Fractional Multiplication handling support # -:function:e500::unsigned64:ev_multiply16_smf:signed16 a, signed16 b, int *sat - signed32 a32 = a, b32 = b, rv32; +:function:e500::uint64_t:ev_multiply16_smf:int16_t a, int16_t b, int *sat + int32_t a32 = a, b32 = b, rv32; rv32 = a * b; *sat = (rv32 & (3<<30)) == (3<<30); - return (signed64)rv32 << 1; + return (int64_t)rv32 << 1; -:function:e500::unsigned64:ev_multiply32_smf:signed32 a, signed32 b, int *sat - signed64 rv64, a64 = a, b64 = b; +:function:e500::uint64_t:ev_multiply32_smf:int32_t a, int32_t b, int *sat + int64_t rv64, a64 = a, b64 = b; rv64 = a64 * b64; - *sat = (rv64 & ((signed64)3<<62)) == ((signed64)3<<62); + *sat = (rv64 & ((int64_t)3<<62)) == ((int64_t)3<<62); /* Loses top sign bit. */ return rv64 << 1; # # SPE Saturation handling support # -:function:e500::signed32:ev_multiply16_ssf:signed16 a, signed16 b, int *sat - signed32 rv32; +:function:e500::int32_t:ev_multiply16_ssf:int16_t a, int16_t b, int *sat + int32_t rv32; if (a == 0xffff8000 && b == 0xffff8000) { rv32 = 0x7fffffffL; @@ -85,15 +85,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr } else { - signed32 a32 = a, b32 = b; + int32_t a32 = a, b32 = b; rv32 = a * b; * sat = (rv32 & (3<<30)) == (3<<30); - return (signed64)rv32 << 1; + return (int64_t)rv32 << 1; } -:function:e500::signed64:ev_multiply32_ssf:signed32 a, signed32 b, int *sat - signed64 rv64; +:function:e500::int64_t:ev_multiply32_ssf:int32_t a, int32_t b, int *sat + int64_t rv64; if (a == 0x80000000 && b == 0x80000000) { rv64 = 0x7fffffffffffffffLL; @@ -102,9 +102,9 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr } else { - signed64 a64 = a, b64 = b; + int64_t a64 = a, b64 = b; rv64 = a64 * b64; - *sat = (rv64 & ((signed64)3<<62)) == ((signed64)3<<62); + *sat = (rv64 & ((int64_t)3<<62)) == ((int64_t)3<<62); /* Loses top sign bit. */ return rv64 << 1; } @@ -114,21 +114,21 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr # :function:e500::void:ev_check_guard:sim_fpu *a, int fg, int fx, cpu *processor - unsigned64 guard; + uint64_t guard; guard = sim_fpu_guard(a, 0); if (guard & 1) EV_SET_SPEFSCR_BITS(fg); if (guard & ~1) EV_SET_SPEFSCR_BITS(fx); -:function:e500::void:booke_sim_fpu_32to:sim_fpu *dst, unsigned32 packed +:function:e500::void:booke_sim_fpu_32to:sim_fpu *dst, uint32_t packed sim_fpu_32to (dst, packed); /* Set normally unused fields to allow booke arithmetic. */ if (dst->class == sim_fpu_class_infinity) { dst->normal_exp = 128; - dst->fraction = ((unsigned64)1 << 60); + dst->fraction = ((uint64_t)1 << 60); } else if (dst->class == sim_fpu_class_qnan || dst->class == sim_fpu_class_snan) @@ -136,7 +136,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr dst->normal_exp = 128; /* This is set, but without the implicit bit, so we have to or in the implicit bit. */ - dst->fraction |= ((unsigned64)1 << 60); + dst->fraction |= ((uint64_t)1 << 60); } :function:e500::int:booke_sim_fpu_add:sim_fpu *d, sim_fpu *a, sim_fpu *b, int inv, int over, int under, cpu *processor @@ -207,9 +207,9 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr return invalid_operand || overflow_result || underflow_result; -:function:e500::unsigned32:ev_fs_add:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor +:function:e500::uint32_t:ev_fs_add:uint32_t aa, uint32_t bb, int inv, int over, int under, int fg, int fx, cpu *processor sim_fpu a, b, d; - unsigned32 w; + uint32_t w; int exception; booke_sim_fpu_32to (&a, aa); @@ -223,9 +223,9 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr ev_check_guard(&d, fg, fx, processor); return w; -:function:e500::unsigned32:ev_fs_sub:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor +:function:e500::uint32_t:ev_fs_sub:uint32_t aa, uint32_t bb, int inv, int over, int under, int fg, int fx, cpu *processor sim_fpu a, b, d; - unsigned32 w; + uint32_t w; int exception; booke_sim_fpu_32to (&a, aa); @@ -244,7 +244,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr # sim_fpu_exp leaves the normal_exp field undefined for Inf and NaN. # The booke algorithms require exp values, so we fake them here. # fixme: It also apparently does the same for zero, but should not. -:function:e500::unsigned32:booke_sim_fpu_exp:sim_fpu *x +:function:e500::uint32_t:booke_sim_fpu_exp:sim_fpu *x int y = sim_fpu_is (x); if (y == SIM_FPU_IS_PZERO || y == SIM_FPU_IS_NZERO) return 0; @@ -254,9 +254,9 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr else return sim_fpu_exp (x); -:function:e500::unsigned32:ev_fs_mul:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor +:function:e500::uint32_t:ev_fs_mul:uint32_t aa, uint32_t bb, int inv, int over, int under, int fg, int fx, cpu *processor sim_fpu a, b, d; - unsigned32 w; + uint32_t w; int sa, sb, ea, eb, ei; sim_fpu_32to (&a, aa); sim_fpu_32to (&b, bb); @@ -296,9 +296,9 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr } return w; -:function:e500::unsigned32:ev_fs_div:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int dbz, int fg, int fx, cpu *processor +:function:e500::uint32_t:ev_fs_div:uint32_t aa, uint32_t bb, int inv, int over, int under, int dbz, int fg, int fx, cpu *processor sim_fpu a, b, d; - unsigned32 w; + uint32_t w; int sa, sb, ea, eb, ei; sim_fpu_32to (&a, aa); @@ -381,7 +381,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr # 0.4,6.RS,11.RA,16.RB,21.512:X:e500:evaddw %RS,%RA,%RB:Vector Add Word - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rBh + *rAh; w2 = *rB + *rA; EV_SET_REG2(*rSh, *rS, w1, w2); @@ -389,7 +389,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.IMM,16.RB,21.514:X:e500:evaddiw %RS,%RB,%IMM:Vector Add Immediate Word - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rBh + IMM; w2 = *rB + IMM; EV_SET_REG2(*rSh, *rS, w1, w2); @@ -397,7 +397,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.516:X:e500:evsubfw %RS,%RA,%RB:Vector Subtract from Word - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rBh - *rAh; w2 = *rB - *rA; EV_SET_REG2(*rSh, *rS, w1, w2); @@ -405,7 +405,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.IMM,16.RB,21.518:X:e500:evsubifw %RS,%RB,%IMM:Vector Subtract Immediate from Word - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rBh - IMM; w2 = *rB - IMM; EV_SET_REG2(*rSh, *rS, w1, w2); @@ -413,7 +413,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.RA,16.0,21.520:X:e500:evabs %RS,%RA:Vector Absolute Value - signed32 w1, w2; + int32_t w1, w2; w1 = *rAh; if (w1 < 0 && w1 != 0x80000000) w1 = -w1; @@ -424,7 +424,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.0,21.521:X:e500:evneg %RS,%RA:Vector Negate - signed32 w1, w2; + int32_t w1, w2; w1 = *rAh; /* the negative most negative number is the most negative number */ if (w1 != 0x80000000) @@ -436,7 +436,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.0,21.522:X:e500:evextsb %RS,%RA:Vector Extend Signed Byte - unsigned64 w1, w2; + uint64_t w1, w2; w1 = *rAh & 0xff; if (w1 & 0x80) w1 |= 0xffffff00; @@ -447,7 +447,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK , 0); 0.4,6.RS,11.RA,16.0,21.523:X:e500:evextsb %RS,%RA:Vector Extend Signed Half Word - unsigned64 w1, w2; + uint64_t w1, w2; w1 = *rAh & 0xffff; if (w1 & 0x8000) w1 |= 0xffff0000; @@ -458,49 +458,49 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.529:X:e500:evand %RS,%RA,%RB:Vector AND - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rBh & *rAh; w2 = *rB & *rA; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.535:X:e500:evor %RS,%RA,%RB:Vector OR - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rBh | *rAh; w2 = *rB | *rA; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.534:X:e500:evxor %RS,%RA,%RB:Vector XOR - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rBh ^ *rAh; w2 = *rB ^ *rA; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.542:X:e500:evnand %RS,%RA,%RB:Vector NAND - unsigned32 w1, w2; + uint32_t w1, w2; w1 = ~(*rBh & *rAh); w2 = ~(*rB & *rA); EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.536:X:e500:evnor %RS,%RA,%RB:Vector NOR - unsigned32 w1, w2; + uint32_t w1, w2; w1 = ~(*rBh | *rAh); w2 = ~(*rB | *rA); EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.537:X:e500:eveqv %RS,%RA,%RB:Vector Equivalent - unsigned32 w1, w2; + uint32_t w1, w2; w1 = (~*rBh) ^ *rAh; w2 = (~*rB) ^ *rA; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.530:X:e500:evandc %RS,%RA,%RB:Vector AND with Compliment - unsigned32 w1, w2; + uint32_t w1, w2; w1 = (~*rBh) & *rAh; w2 = (~*rB) & *rA; EV_SET_REG2(*rSh, *rS, w1, w2); @@ -508,7 +508,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.539:X:e500:evorc %RS,%RA,%RB:Vector OR with Compliment - unsigned32 w1, w2; + uint32_t w1, w2; w1 = (~*rBh) | *rAh; w2 = (~*rB) | *rA; EV_SET_REG2(*rSh, *rS, w1, w2); @@ -516,76 +516,76 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.552:X:e500:evrlw %RS,%RA,%RB:Vector Rotate Left Word - unsigned32 nh, nl, w1, w2; + uint32_t nh, nl, w1, w2; nh = *rBh & 0x1f; nl = *rB & 0x1f; - w1 = ((unsigned32)*rAh) << nh | ((unsigned32)*rAh) >> (32 - nh); - w2 = ((unsigned32)*rA) << nl | ((unsigned32)*rA) >> (32 - nl); + w1 = ((uint32_t)*rAh) << nh | ((uint32_t)*rAh) >> (32 - nh); + w2 = ((uint32_t)*rA) << nl | ((uint32_t)*rA) >> (32 - nl); EV_SET_REG2(*rSh, *rS, w1, w2); //printf("evrlw: nh %d nl %d *rSh = %08x; *rS = %08x\n", nh, nl, *rSh, *rS); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.UIMM,21.554:X:e500:evrlwi %RS,%RA,%UIMM:Vector Rotate Left Word Immediate - unsigned32 w1, w2, imm; - imm = (unsigned32)UIMM; - w1 = ((unsigned32)*rAh) << imm | ((unsigned32)*rAh) >> (32 - imm); - w2 = ((unsigned32)*rA) << imm | ((unsigned32)*rA) >> (32 - imm); + uint32_t w1, w2, imm; + imm = (uint32_t)UIMM; + w1 = ((uint32_t)*rAh) << imm | ((uint32_t)*rAh) >> (32 - imm); + w2 = ((uint32_t)*rA) << imm | ((uint32_t)*rA) >> (32 - imm); EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.548:X:e500:evslw %RS,%RA,%RB:Vector Shift Left Word - unsigned32 nh, nl, w1, w2; + uint32_t nh, nl, w1, w2; nh = *rBh & 0x1f; nl = *rB & 0x1f; - w1 = ((unsigned32)*rAh) << nh; - w2 = ((unsigned32)*rA) << nl; + w1 = ((uint32_t)*rAh) << nh; + w2 = ((uint32_t)*rA) << nl; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.UIMM,21.550:X:e500:evslwi %RS,%RA,%UIMM:Vector Shift Left Word Immediate - unsigned32 w1, w2, imm = UIMM; - w1 = ((unsigned32)*rAh) << imm; - w2 = ((unsigned32)*rA) << imm; + uint32_t w1, w2, imm = UIMM; + w1 = ((uint32_t)*rAh) << imm; + w2 = ((uint32_t)*rA) << imm; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.545:X:e500:evsrws %RS,%RA,%RB:Vector Shift Right Word Signed - signed32 w1, w2; - unsigned32 nh, nl; + int32_t w1, w2; + uint32_t nh, nl; nh = *rBh & 0x1f; nl = *rB & 0x1f; - w1 = ((signed32)*rAh) >> nh; - w2 = ((signed32)*rA) >> nl; + w1 = ((int32_t)*rAh) >> nh; + w2 = ((int32_t)*rA) >> nl; EV_SET_REG2(*rSh, *rS, w1, w2); //printf("evsrws: nh %d nl %d *rSh = %08x; *rS = %08x\n", nh, nl, *rSh, *rS); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.544:X:e500:evsrwu %RS,%RA,%RB:Vector Shift Right Word Unsigned - unsigned32 w1, w2, nh, nl; + uint32_t w1, w2, nh, nl; nh = *rBh & 0x1f; nl = *rB & 0x1f; - w1 = ((unsigned32)*rAh) >> nh; - w2 = ((unsigned32)*rA) >> nl; + w1 = ((uint32_t)*rAh) >> nh; + w2 = ((uint32_t)*rA) >> nl; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.UIMM,21.547:X:e500:evsrwis %RS,%RA,%UIMM:Vector Shift Right Word Immediate Signed - signed32 w1, w2; - unsigned32 imm = UIMM; - w1 = ((signed32)*rAh) >> imm; - w2 = ((signed32)*rA) >> imm; + int32_t w1, w2; + uint32_t imm = UIMM; + w1 = ((int32_t)*rAh) >> imm; + w2 = ((int32_t)*rA) >> imm; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.UIMM,21.546:X:e500:evsrwiu %RS,%RA,%UIMM:Vector Shift Right Word Immediate Unsigned - unsigned32 w1, w2, imm = UIMM; - w1 = ((unsigned32)*rAh) >> imm; - w2 = ((unsigned32)*rA) >> imm; + uint32_t w1, w2, imm = UIMM; + w1 = ((uint32_t)*rAh) >> imm; + w2 = ((uint32_t)*rA) >> imm; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.0,21.525:X:e500:evcntlzw %RS,%RA:Vector Count Leading Zeros Word - unsigned32 w1, w2, mask, c1, c2; + uint32_t w1, w2, mask, c1, c2; for (c1 = 0, mask = 0x80000000, w1 = *rAh; !(w1 & mask) && mask != 0; mask >>= 1) c1++; @@ -596,7 +596,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.0,21.526:X:e500:evcntlsw %RS,%RA:Vector Count Leading Sign Bits Word - unsigned32 w1, w2, mask, sign_bit, c1, c2; + uint32_t w1, w2, mask, sign_bit, c1, c2; for (c1 = 0, mask = 0x80000000, w1 = *rAh, sign_bit = w1 & mask; ((w1 & mask) == sign_bit) && mask != 0; mask >>= 1, sign_bit >>= 1) @@ -609,43 +609,43 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.0,21.524:X:e500:evrndw %RS,%RA:Vector Round Word - unsigned32 w1, w2; - w1 = ((unsigned32)*rAh + 0x8000) & 0xffff0000; - w2 = ((unsigned32)*rA + 0x8000) & 0xffff0000; + uint32_t w1, w2; + w1 = ((uint32_t)*rAh + 0x8000) & 0xffff0000; + w2 = ((uint32_t)*rA + 0x8000) & 0xffff0000; EV_SET_REG2(*rSh, *rS, w1, w2); //printf("evrndw: *rSh = %08x; *rS = %08x\n", *rSh, *rS); PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.556:X:e500:evmergehi %RS,%RA,%RB:Vector Merge Hi - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rAh; w2 = *rBh; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.557:X:e500:evmergelo %RS,%RA,%RB:Vector Merge Low - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rA; w2 = *rB; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.559:X:e500:evmergelohi %RS,%RA,%RB:Vector Merge Low Hi - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rA; w2 = *rBh; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.558:X:e500:evmergehilo %RS,%RA,%RB:Vector Merge Hi Low - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rAh; w2 = *rB; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.SIMM,16.0,21.553:X:e500:evsplati %RS,%SIMM:Vector Splat Immediate - unsigned32 w; + uint32_t w; w = SIMM & 0x1f; if (w & 0x10) w |= 0xffffffe0; @@ -653,13 +653,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, 0, 0); 0.4,6.RS,11.SIMM,16.0,21.555:X:e500:evsplatfi %RS,%SIMM:Vector Splat Fractional Immediate - unsigned32 w; + uint32_t w; w = SIMM << 27; EV_SET_REG2(*rSh, *rS, w, w); PPC_INSN_INT(RS_BITMASK, 0, 0); 0.4,6.BF,9.0,11.RA,16.RB,21.561:X:e500:evcmpgts %BF,%RA,%RB:Vector Compare Greater Than Signed - signed32 ah, al, bh, bl; + int32_t ah, al, bh, bl; int w, ch, cl; ah = *rAh; al = *rA; @@ -678,7 +678,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 0.4,6.BF,9.0,11.RA,16.RB,21.560:X:e500:evcmpgtu %BF,%RA,%RB:Vector Compare Greater Than Unsigned - unsigned32 ah, al, bh, bl; + uint32_t ah, al, bh, bl; int w, ch, cl; ah = *rAh; al = *rA; @@ -697,7 +697,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 0.4,6.BF,9.0,11.RA,16.RB,21.563:X:e500:evcmplts %BF,%RA,%RB:Vector Compare Less Than Signed - signed32 ah, al, bh, bl; + int32_t ah, al, bh, bl; int w, ch, cl; ah = *rAh; al = *rA; @@ -716,7 +716,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 0.4,6.BF,9.0,11.RA,16.RB,21.562:X:e500:evcmpltu %BF,%RA,%RB:Vector Compare Less Than Unsigned - unsigned32 ah, al, bh, bl; + uint32_t ah, al, bh, bl; int w, ch, cl; ah = *rAh; al = *rA; @@ -735,7 +735,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 0.4,6.BF,9.0,11.RA,16.RB,21.564:X:e500:evcmpeq %BF,%RA,%RB:Vector Compare Equal - unsigned32 ah, al, bh, bl; + uint32_t ah, al, bh, bl; int w, ch, cl; ah = *rAh; al = *rA; @@ -755,7 +755,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 0.4,6.RS,11.RA,16.RB,21.79,29.CRFS:X:e500:evsel %RS,%RA,%RB,%CRFS:Vector Select - unsigned32 w1, w2; + uint32_t w1, w2; int cr; cr = CR_FIELD(CRFS); if (cr & 8) @@ -770,7 +770,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.527:X:e500:brinc %RS,%RA,%RB:Bit Reversed Increment - unsigned32 w1, w2, a, d, mask; + uint32_t w1, w2, a, d, mask; mask = (*rB) & 0xffff; a = (*rA) & 0xffff; d = EV_BITREVERSE16(1 + EV_BITREVERSE16(a | ~mask)); @@ -783,14 +783,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr # 0.4,6.RS,11.RA,16.RB,21.1031:EVX:e500:evmhossf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional - signed16 al, ah, bl, bh; - signed32 tl, th; + int16_t al, ah, bl, bh; + int32_t tl, th; int movl, movh; - al = (signed16) EV_LOHALF (*rA); - ah = (signed16) EV_LOHALF (*rAh); - bl = (signed16) EV_LOHALF (*rB); - bh = (signed16) EV_LOHALF (*rBh); + al = (int16_t) EV_LOHALF (*rA); + ah = (int16_t) EV_LOHALF (*rAh); + bl = (int16_t) EV_LOHALF (*rB); + bh = (int16_t) EV_LOHALF (*rBh); tl = ev_multiply16_ssf (al, bl, &movl); th = ev_multiply16_ssf (ah, bh, &movh); EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), @@ -799,14 +799,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1063:EVX:e500:evmhossfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional Accumulate - signed16 al, ah, bl, bh; - signed32 tl, th; + int16_t al, ah, bl, bh; + int32_t tl, th; int movl, movh; - al = (signed16) EV_LOHALF (*rA); - ah = (signed16) EV_LOHALF (*rAh); - bl = (signed16) EV_LOHALF (*rB); - bh = (signed16) EV_LOHALF (*rBh); + al = (int16_t) EV_LOHALF (*rA); + ah = (int16_t) EV_LOHALF (*rAh); + bl = (int16_t) EV_LOHALF (*rB); + bh = (int16_t) EV_LOHALF (*rBh); tl = ev_multiply16_ssf (al, bl, &movl); th = ev_multiply16_ssf (ah, bh, &movh); EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), @@ -815,39 +815,39 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1039:EVX:e500:evmhosmf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional - signed16 al, ah, bl, bh; - signed32 tl, th; + int16_t al, ah, bl, bh; + int32_t tl, th; int dummy; - al = (signed16) EV_LOHALF (*rA); - ah = (signed16) EV_LOHALF (*rAh); - bl = (signed16) EV_LOHALF (*rB); - bh = (signed16) EV_LOHALF (*rBh); + al = (int16_t) EV_LOHALF (*rA); + ah = (int16_t) EV_LOHALF (*rAh); + bl = (int16_t) EV_LOHALF (*rB); + bh = (int16_t) EV_LOHALF (*rBh); tl = ev_multiply16_smf (al, bl, & dummy); th = ev_multiply16_smf (ah, bh, & dummy); EV_SET_REG2 (*rSh, *rS, th, tl); PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1071:EVX:e500:evmhosmfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional Accumulate - signed32 al, ah, bl, bh; - signed32 tl, th; + int32_t al, ah, bl, bh; + int32_t tl, th; int dummy; - al = (signed16) EV_LOHALF (*rA); - ah = (signed16) EV_LOHALF (*rAh); - bl = (signed16) EV_LOHALF (*rB); - bh = (signed16) EV_LOHALF (*rBh); + al = (int16_t) EV_LOHALF (*rA); + ah = (int16_t) EV_LOHALF (*rAh); + bl = (int16_t) EV_LOHALF (*rB); + bh = (int16_t) EV_LOHALF (*rBh); tl = ev_multiply16_smf (al, bl, & dummy); th = ev_multiply16_smf (ah, bh, & dummy); EV_SET_REG2_ACC (*rSh, *rS, th, tl); PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1037:EVX:e500:evmhosmi %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer - signed32 al, ah, bl, bh, tl, th; - al = (signed32)(signed16)EV_LOHALF(*rA); - ah = (signed32)(signed16)EV_LOHALF(*rAh); - bl = (signed32)(signed16)EV_LOHALF(*rB); - bh = (signed32)(signed16)EV_LOHALF(*rBh); + int32_t al, ah, bl, bh, tl, th; + al = (int32_t)(int16_t)EV_LOHALF(*rA); + ah = (int32_t)(int16_t)EV_LOHALF(*rAh); + bl = (int32_t)(int16_t)EV_LOHALF(*rB); + bh = (int32_t)(int16_t)EV_LOHALF(*rBh); tl = al * bl; th = ah * bh; EV_SET_REG2(*rSh, *rS, th, tl); @@ -855,11 +855,11 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1069:EVX:e500:evmhosmia %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer Accumulate - signed32 al, ah, bl, bh, tl, th; - al = (signed32)(signed16)EV_LOHALF(*rA); - ah = (signed32)(signed16)EV_LOHALF(*rAh); - bl = (signed32)(signed16)EV_LOHALF(*rB); - bh = (signed32)(signed16)EV_LOHALF(*rBh); + int32_t al, ah, bl, bh, tl, th; + al = (int32_t)(int16_t)EV_LOHALF(*rA); + ah = (int32_t)(int16_t)EV_LOHALF(*rAh); + bl = (int32_t)(int16_t)EV_LOHALF(*rB); + bh = (int32_t)(int16_t)EV_LOHALF(*rBh); tl = al * bl; th = ah * bh; EV_SET_REG2_ACC(*rSh, *rS, th, tl); @@ -867,36 +867,36 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1036:EVX:e500:evmhoumi %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer - unsigned32 al, ah, bl, bh, tl, th; - al = (unsigned32)(unsigned16)EV_LOHALF(*rA); - ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); - bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); - bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); + uint32_t al, ah, bl, bh, tl, th; + al = (uint32_t)(uint16_t)EV_LOHALF(*rA); + ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh); + bl = (uint32_t)(uint16_t)EV_LOHALF(*rB); + bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh); tl = al * bl; th = ah * bh; EV_SET_REG2(*rSh, *rS, th, tl); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1068:EVX:e500:evmhoumia %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer Accumulate - unsigned32 al, ah, bl, bh, tl, th; - al = (unsigned32)(unsigned16)EV_LOHALF(*rA); - ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); - bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); - bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); + uint32_t al, ah, bl, bh, tl, th; + al = (uint32_t)(uint16_t)EV_LOHALF(*rA); + ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh); + bl = (uint32_t)(uint16_t)EV_LOHALF(*rB); + bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh); tl = al * bl; th = ah * bh; EV_SET_REG2_ACC(*rSh, *rS, th, tl); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1027:EVX:e500:evmhessf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional - signed16 al, ah, bl, bh; - signed32 tl, th; + int16_t al, ah, bl, bh; + int32_t tl, th; int movl, movh; - al = (signed16) EV_HIHALF (*rA); - ah = (signed16) EV_HIHALF (*rAh); - bl = (signed16) EV_HIHALF (*rB); - bh = (signed16) EV_HIHALF (*rBh); + al = (int16_t) EV_HIHALF (*rA); + ah = (int16_t) EV_HIHALF (*rAh); + bl = (int16_t) EV_HIHALF (*rB); + bh = (int16_t) EV_HIHALF (*rBh); tl = ev_multiply16_ssf (al, bl, &movl); th = ev_multiply16_ssf (ah, bh, &movh); EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), @@ -905,14 +905,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1059:EVX:e500:evmhessfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional Accumulate - signed16 al, ah, bl, bh; - signed32 tl, th; + int16_t al, ah, bl, bh; + int32_t tl, th; int movl, movh; - al = (signed16) EV_HIHALF (*rA); - ah = (signed16) EV_HIHALF (*rAh); - bl = (signed16) EV_HIHALF (*rB); - bh = (signed16) EV_HIHALF (*rBh); + al = (int16_t) EV_HIHALF (*rA); + ah = (int16_t) EV_HIHALF (*rAh); + bl = (int16_t) EV_HIHALF (*rB); + bh = (int16_t) EV_HIHALF (*rBh); tl = ev_multiply16_ssf (al, bl, &movl); th = ev_multiply16_ssf (ah, bh, &movh); EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), @@ -921,14 +921,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1035:EVX:e500:evmhesmf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional - signed16 al, ah, bl, bh; - signed64 tl, th; + int16_t al, ah, bl, bh; + int64_t tl, th; int movl, movh; - al = (signed16) EV_HIHALF (*rA); - ah = (signed16) EV_HIHALF (*rAh); - bl = (signed16) EV_HIHALF (*rB); - bh = (signed16) EV_HIHALF (*rBh); + al = (int16_t) EV_HIHALF (*rA); + ah = (int16_t) EV_HIHALF (*rAh); + bl = (int16_t) EV_HIHALF (*rB); + bh = (int16_t) EV_HIHALF (*rBh); tl = ev_multiply16_smf (al, bl, &movl); th = ev_multiply16_smf (ah, bh, &movh); EV_SET_REG2 (*rSh, *rS, th, tl); @@ -936,75 +936,75 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1067:EVX:e500:evmhesmfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional Accumulate - signed16 al, ah, bl, bh; - signed32 tl, th; + int16_t al, ah, bl, bh; + int32_t tl, th; int dummy; - al = (signed16) EV_HIHALF (*rA); - ah = (signed16) EV_HIHALF (*rAh); - bl = (signed16) EV_HIHALF (*rB); - bh = (signed16) EV_HIHALF (*rBh); + al = (int16_t) EV_HIHALF (*rA); + ah = (int16_t) EV_HIHALF (*rAh); + bl = (int16_t) EV_HIHALF (*rB); + bh = (int16_t) EV_HIHALF (*rBh); tl = ev_multiply16_smf (al, bl, & dummy); th = ev_multiply16_smf (ah, bh, & dummy); EV_SET_REG2_ACC (*rSh, *rS, th, tl); PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1033:EVX:e500:evmhesmi %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer - signed16 al, ah, bl, bh; - signed32 tl, th; + int16_t al, ah, bl, bh; + int32_t tl, th; - al = (signed16) EV_HIHALF (*rA); - ah = (signed16) EV_HIHALF (*rAh); - bl = (signed16) EV_HIHALF (*rB); - bh = (signed16) EV_HIHALF (*rBh); + al = (int16_t) EV_HIHALF (*rA); + ah = (int16_t) EV_HIHALF (*rAh); + bl = (int16_t) EV_HIHALF (*rB); + bh = (int16_t) EV_HIHALF (*rBh); tl = al * bl; th = ah * bh; EV_SET_REG2 (*rSh, *rS, th, tl); PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1065:EVX:e500:evmhesmia %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer Accumulate - signed32 al, ah, bl, bh, tl, th; - al = (signed32)(signed16)EV_HIHALF(*rA); - ah = (signed32)(signed16)EV_HIHALF(*rAh); - bl = (signed32)(signed16)EV_HIHALF(*rB); - bh = (signed32)(signed16)EV_HIHALF(*rBh); + int32_t al, ah, bl, bh, tl, th; + al = (int32_t)(int16_t)EV_HIHALF(*rA); + ah = (int32_t)(int16_t)EV_HIHALF(*rAh); + bl = (int32_t)(int16_t)EV_HIHALF(*rB); + bh = (int32_t)(int16_t)EV_HIHALF(*rBh); tl = al * bl; th = ah * bh; EV_SET_REG2_ACC(*rSh, *rS, th, tl); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1032:EVX:e500:evmheumi %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer - unsigned32 al, ah, bl, bh, tl, th; - al = (unsigned32)(unsigned16)EV_HIHALF(*rA); - ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); - bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); - bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); + uint32_t al, ah, bl, bh, tl, th; + al = (uint32_t)(uint16_t)EV_HIHALF(*rA); + ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh); + bl = (uint32_t)(uint16_t)EV_HIHALF(*rB); + bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh); tl = al * bl; th = ah * bh; EV_SET_REG2(*rSh, *rS, th, tl); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1064:EVX:e500:evmheumia %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer Accumulate - unsigned32 al, ah, bl, bh, tl, th; - al = (unsigned32)(unsigned16)EV_HIHALF(*rA); - ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); - bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); - bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); + uint32_t al, ah, bl, bh, tl, th; + al = (uint32_t)(uint16_t)EV_HIHALF(*rA); + ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh); + bl = (uint32_t)(uint16_t)EV_HIHALF(*rB); + bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh); tl = al * bl; th = ah * bh; EV_SET_REG2_ACC(*rSh, *rS, th, tl); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1287:EVX:e500:evmhossfaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional and Accumulate into Words - signed16 al, ah, bl, bh; - signed32 t1, t2; - signed64 tl, th; + int16_t al, ah, bl, bh; + int32_t t1, t2; + int64_t tl, th; int movl, movh, ovl, ovh; - al = (signed16) EV_LOHALF (*rA); - ah = (signed16) EV_LOHALF (*rAh); - bl = (signed16) EV_LOHALF (*rB); - bh = (signed16) EV_LOHALF (*rBh); + al = (int16_t) EV_LOHALF (*rA); + ah = (int16_t) EV_LOHALF (*rAh); + bl = (int16_t) EV_LOHALF (*rB); + bh = (int16_t) EV_LOHALF (*rBh); t1 = ev_multiply16_ssf (ah, bh, &movh); t2 = ev_multiply16_ssf (al, bl, &movl); th = EV_ACCHIGH + EV_SATURATE (movh, 0x7fffffff, t1); @@ -1017,13 +1017,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1285:EVX:e500:evmhossiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Integer and Accumulate into Words - signed32 al, ah, bl, bh; - signed64 t1, t2, tl, th; + int32_t al, ah, bl, bh; + int64_t t1, t2, tl, th; int ovl, ovh; - al = (signed32)(signed16)EV_LOHALF(*rA); - ah = (signed32)(signed16)EV_LOHALF(*rAh); - bl = (signed32)(signed16)EV_LOHALF(*rB); - bh = (signed32)(signed16)EV_LOHALF(*rBh); + al = (int32_t)(int16_t)EV_LOHALF(*rA); + ah = (int32_t)(int16_t)EV_LOHALF(*rAh); + bl = (int32_t)(int16_t)EV_LOHALF(*rB); + bh = (int32_t)(int16_t)EV_LOHALF(*rBh); t1 = ah * bh; t2 = al * bl; th = EV_ACCHIGH + t1; @@ -1038,26 +1038,26 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1295:EVX:e500:evmhosmfaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional and Accumulate into Words - signed32 al, ah, bl, bh; - signed64 t1, t2, tl, th; - al = (signed32)(signed16)EV_LOHALF(*rA); - ah = (signed32)(signed16)EV_LOHALF(*rAh); - bl = (signed32)(signed16)EV_LOHALF(*rB); - bh = (signed32)(signed16)EV_LOHALF(*rBh); - t1 = ((signed64)ah * bh) << 1; - t2 = ((signed64)al * bl) << 1; + int32_t al, ah, bl, bh; + int64_t t1, t2, tl, th; + al = (int32_t)(int16_t)EV_LOHALF(*rA); + ah = (int32_t)(int16_t)EV_LOHALF(*rAh); + bl = (int32_t)(int16_t)EV_LOHALF(*rB); + bh = (int32_t)(int16_t)EV_LOHALF(*rBh); + t1 = ((int64_t)ah * bh) << 1; + t2 = ((int64_t)al * bl) << 1; th = EV_ACCHIGH + (t1 & 0xffffffff); tl = EV_ACCLOW + (t2 & 0xffffffff); EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1293:EVX:e500:evmhosmiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer and Accumulate into Words - signed32 al, ah, bl, bh; - signed64 t1, t2, tl, th; - al = (signed32)(signed16)EV_LOHALF(*rA); - ah = (signed32)(signed16)EV_LOHALF(*rAh); - bl = (signed32)(signed16)EV_LOHALF(*rB); - bh = (signed32)(signed16)EV_LOHALF(*rBh); + int32_t al, ah, bl, bh; + int64_t t1, t2, tl, th; + al = (int32_t)(int16_t)EV_LOHALF(*rA); + ah = (int32_t)(int16_t)EV_LOHALF(*rAh); + bl = (int32_t)(int16_t)EV_LOHALF(*rB); + bh = (int32_t)(int16_t)EV_LOHALF(*rBh); t1 = ah * bh; t2 = al * bl; th = EV_ACCHIGH + t1; @@ -1068,18 +1068,18 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1284:EVX:e500:evmhousiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Saturate Integer and Accumulate into Words - unsigned32 al, ah, bl, bh; - unsigned64 t1, t2; - signed64 tl, th; + uint32_t al, ah, bl, bh; + uint64_t t1, t2; + int64_t tl, th; int ovl, ovh; - al = (unsigned32)(unsigned16)EV_LOHALF(*rA); - ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); - bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); - bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); + al = (uint32_t)(uint16_t)EV_LOHALF(*rA); + ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh); + bl = (uint32_t)(uint16_t)EV_LOHALF(*rB); + bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh); t1 = ah * bh; t2 = al * bl; - th = (signed64)EV_ACCHIGH + (signed64)t1; - tl = (signed64)EV_ACCLOW + (signed64)t2; + th = (int64_t)EV_ACCHIGH + (int64_t)t1; + tl = (int64_t)EV_ACCLOW + (int64_t)t2; ovh = EV_SAT_P_U32(th); ovl = EV_SAT_P_U32(tl); EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), @@ -1090,13 +1090,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1292:EVX:e500:evmhoumiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer and Accumulate into Words - unsigned32 al, ah, bl, bh; - unsigned32 t1, t2; - signed64 tl, th; - al = (unsigned32)(unsigned16)EV_LOHALF(*rA); - ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); - bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); - bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); + uint32_t al, ah, bl, bh; + uint32_t t1, t2; + int64_t tl, th; + al = (uint32_t)(uint16_t)EV_LOHALF(*rA); + ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh); + bl = (uint32_t)(uint16_t)EV_LOHALF(*rB); + bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh); t1 = ah * bh; t2 = al * bl; th = EV_ACCHIGH + t1; @@ -1107,15 +1107,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1283:EVX:e500:evmhessfaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional and Accumulate into Words - signed16 al, ah, bl, bh; - signed32 t1, t2; - signed64 tl, th; + int16_t al, ah, bl, bh; + int32_t t1, t2; + int64_t tl, th; int movl, movh, ovl, ovh; - al = (signed16) EV_HIHALF (*rA); - ah = (signed16) EV_HIHALF (*rAh); - bl = (signed16) EV_HIHALF (*rB); - bh = (signed16) EV_HIHALF (*rBh); + al = (int16_t) EV_HIHALF (*rA); + ah = (int16_t) EV_HIHALF (*rAh); + bl = (int16_t) EV_HIHALF (*rB); + bh = (int16_t) EV_HIHALF (*rBh); t1 = ev_multiply16_ssf (ah, bh, &movh); t2 = ev_multiply16_ssf (al, bl, &movl); th = EV_ACCHIGH + EV_SATURATE (movh, 0x7fffffff, t1); @@ -1128,13 +1128,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1281:EVX:e500:evmhessiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Integer and Accumulate into Words - signed32 al, ah, bl, bh; - signed64 t1, t2, tl, th; + int32_t al, ah, bl, bh; + int64_t t1, t2, tl, th; int ovl, ovh; - al = (signed32)(signed16)EV_HIHALF(*rA); - ah = (signed32)(signed16)EV_HIHALF(*rAh); - bl = (signed32)(signed16)EV_HIHALF(*rB); - bh = (signed32)(signed16)EV_HIHALF(*rBh); + al = (int32_t)(int16_t)EV_HIHALF(*rA); + ah = (int32_t)(int16_t)EV_HIHALF(*rAh); + bl = (int32_t)(int16_t)EV_HIHALF(*rB); + bh = (int32_t)(int16_t)EV_HIHALF(*rBh); t1 = ah * bh; t2 = al * bl; th = EV_ACCHIGH + t1; @@ -1149,14 +1149,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1291:EVX:e500:evmhesmfaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional and Accumulate into Words - signed16 al, ah, bl, bh; - signed32 t1, t2, th, tl; + int16_t al, ah, bl, bh; + int32_t t1, t2, th, tl; int dummy; - al = (signed16)EV_HIHALF(*rA); - ah = (signed16)EV_HIHALF(*rAh); - bl = (signed16)EV_HIHALF(*rB); - bh = (signed16)EV_HIHALF(*rBh); + al = (int16_t)EV_HIHALF(*rA); + ah = (int16_t)EV_HIHALF(*rAh); + bl = (int16_t)EV_HIHALF(*rB); + bh = (int16_t)EV_HIHALF(*rBh); t1 = ev_multiply16_smf (ah, bh, &dummy); t2 = ev_multiply16_smf (al, bl, &dummy); th = EV_ACCHIGH + t1; @@ -1165,12 +1165,12 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1289:EVX:e500:evmhesmiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer and Accumulate into Words - signed32 al, ah, bl, bh; - signed64 t1, t2, tl, th; - al = (signed32)(signed16)EV_HIHALF(*rA); - ah = (signed32)(signed16)EV_HIHALF(*rAh); - bl = (signed32)(signed16)EV_HIHALF(*rB); - bh = (signed32)(signed16)EV_HIHALF(*rBh); + int32_t al, ah, bl, bh; + int64_t t1, t2, tl, th; + al = (int32_t)(int16_t)EV_HIHALF(*rA); + ah = (int32_t)(int16_t)EV_HIHALF(*rAh); + bl = (int32_t)(int16_t)EV_HIHALF(*rB); + bh = (int32_t)(int16_t)EV_HIHALF(*rBh); t1 = ah * bh; t2 = al * bl; th = EV_ACCHIGH + t1; @@ -1179,18 +1179,18 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1280:EVX:e500:evmheusiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Saturate Integer and Accumulate into Words - unsigned32 al, ah, bl, bh; - unsigned64 t1, t2; - signed64 tl, th; + uint32_t al, ah, bl, bh; + uint64_t t1, t2; + int64_t tl, th; int ovl, ovh; - al = (unsigned32)(unsigned16)EV_HIHALF(*rA); - ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); - bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); - bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); + al = (uint32_t)(uint16_t)EV_HIHALF(*rA); + ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh); + bl = (uint32_t)(uint16_t)EV_HIHALF(*rB); + bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh); t1 = ah * bh; t2 = al * bl; - th = (signed64)EV_ACCHIGH + (signed64)t1; - tl = (signed64)EV_ACCLOW + (signed64)t2; + th = (int64_t)EV_ACCHIGH + (int64_t)t1; + tl = (int64_t)EV_ACCLOW + (int64_t)t2; ovh = EV_SAT_P_U32(th); ovl = EV_SAT_P_U32(tl); EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), @@ -1199,13 +1199,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1288:EVX:e500:evmheumiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer and Accumulate into Words - unsigned32 al, ah, bl, bh; - unsigned32 t1, t2; - unsigned64 tl, th; - al = (unsigned32)(unsigned16)EV_HIHALF(*rA); - ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); - bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); - bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); + uint32_t al, ah, bl, bh; + uint32_t t1, t2; + uint64_t tl, th; + al = (uint32_t)(uint16_t)EV_HIHALF(*rA); + ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh); + bl = (uint32_t)(uint16_t)EV_HIHALF(*rB); + bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh); t1 = ah * bh; t2 = al * bl; th = EV_ACCHIGH + t1; @@ -1215,15 +1215,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.1415:EVX:e500:evmhossfanw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional and Accumulate Negative into Words - signed16 al, ah, bl, bh; - signed32 t1, t2; - signed64 tl, th; + int16_t al, ah, bl, bh; + int32_t t1, t2; + int64_t tl, th; int movl, movh, ovl, ovh; - al = (signed16) EV_LOHALF (*rA); - ah = (signed16) EV_LOHALF (*rAh); - bl = (signed16) EV_LOHALF (*rB); - bh = (signed16) EV_LOHALF (*rBh); + al = (int16_t) EV_LOHALF (*rA); + ah = (int16_t) EV_LOHALF (*rAh); + bl = (int16_t) EV_LOHALF (*rB); + bh = (int16_t) EV_LOHALF (*rBh); t1 = ev_multiply16_ssf (ah, bh, &movh); t2 = ev_multiply16_ssf (al, bl, &movl); th = EV_ACCHIGH - EV_SATURATE (movh, 0x7fffffff, t1); @@ -1236,13 +1236,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1413:EVX:e500:evmhossianw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Integer and Accumulate Negative into Words - signed32 al, ah, bl, bh; - signed64 t1, t2, tl, th; + int32_t al, ah, bl, bh; + int64_t t1, t2, tl, th; int ovl, ovh; - al = (signed32)(signed16)EV_LOHALF(*rA); - ah = (signed32)(signed16)EV_LOHALF(*rAh); - bl = (signed32)(signed16)EV_LOHALF(*rB); - bh = (signed32)(signed16)EV_LOHALF(*rBh); + al = (int32_t)(int16_t)EV_LOHALF(*rA); + ah = (int32_t)(int16_t)EV_LOHALF(*rAh); + bl = (int32_t)(int16_t)EV_LOHALF(*rB); + bh = (int32_t)(int16_t)EV_LOHALF(*rBh); t1 = ah * bh; t2 = al * bl; th = EV_ACCHIGH - t1; @@ -1256,26 +1256,26 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1423:EVX:e500:evmhosmfanw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional and Accumulate Negative into Words - signed32 al, ah, bl, bh; - signed64 t1, t2, tl, th; - al = (signed32)(signed16)EV_LOHALF(*rA); - ah = (signed32)(signed16)EV_LOHALF(*rAh); - bl = (signed32)(signed16)EV_LOHALF(*rB); - bh = (signed32)(signed16)EV_LOHALF(*rBh); - t1 = ((signed64)ah * bh) << 1; - t2 = ((signed64)al * bl) << 1; + int32_t al, ah, bl, bh; + int64_t t1, t2, tl, th; + al = (int32_t)(int16_t)EV_LOHALF(*rA); + ah = (int32_t)(int16_t)EV_LOHALF(*rAh); + bl = (int32_t)(int16_t)EV_LOHALF(*rB); + bh = (int32_t)(int16_t)EV_LOHALF(*rBh); + t1 = ((int64_t)ah * bh) << 1; + t2 = ((int64_t)al * bl) << 1; th = EV_ACCHIGH - (t1 & 0xffffffff); tl = EV_ACCLOW - (t2 & 0xffffffff); EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1421:EVX:e500:evmhosmianw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer and Accumulate Negative into Words - signed32 al, ah, bl, bh; - signed64 t1, t2, tl, th; - al = (signed32)(signed16)EV_LOHALF(*rA); - ah = (signed32)(signed16)EV_LOHALF(*rAh); - bl = (signed32)(signed16)EV_LOHALF(*rB); - bh = (signed32)(signed16)EV_LOHALF(*rBh); + int32_t al, ah, bl, bh; + int64_t t1, t2, tl, th; + al = (int32_t)(int16_t)EV_LOHALF(*rA); + ah = (int32_t)(int16_t)EV_LOHALF(*rAh); + bl = (int32_t)(int16_t)EV_LOHALF(*rB); + bh = (int32_t)(int16_t)EV_LOHALF(*rBh); t1 = ah * bh; t2 = al * bl; th = EV_ACCHIGH - t1; @@ -1284,18 +1284,18 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1412:EVX:e500:evmhousianw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Saturate Integer and Accumulate Negative into Words - unsigned32 al, ah, bl, bh; - unsigned64 t1, t2; - signed64 tl, th; + uint32_t al, ah, bl, bh; + uint64_t t1, t2; + int64_t tl, th; int ovl, ovh; - al = (unsigned32)(unsigned16)EV_LOHALF(*rA); - ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); - bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); - bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); + al = (uint32_t)(uint16_t)EV_LOHALF(*rA); + ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh); + bl = (uint32_t)(uint16_t)EV_LOHALF(*rB); + bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh); t1 = ah * bh; t2 = al * bl; - th = (signed64)EV_ACCHIGH - (signed64)t1; - tl = (signed64)EV_ACCLOW - (signed64)t2; + th = (int64_t)EV_ACCHIGH - (int64_t)t1; + tl = (int64_t)EV_ACCLOW - (int64_t)t2; ovl = EV_SAT_P_U32(tl); ovh = EV_SAT_P_U32(th); EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), @@ -1306,13 +1306,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1420:EVX:e500:evmhoumianw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer and Accumulate Negative into Words - unsigned32 al, ah, bl, bh; - unsigned32 t1, t2; - unsigned64 tl, th; - al = (unsigned32)(unsigned16)EV_LOHALF(*rA); - ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); - bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); - bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); + uint32_t al, ah, bl, bh; + uint32_t t1, t2; + uint64_t tl, th; + al = (uint32_t)(uint16_t)EV_LOHALF(*rA); + ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh); + bl = (uint32_t)(uint16_t)EV_LOHALF(*rB); + bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh); t1 = ah * bh; t2 = al * bl; th = EV_ACCHIGH - t1; @@ -1321,15 +1321,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1411:EVX:e500:evmhessfanw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional and Accumulate Negative into Words - signed16 al, ah, bl, bh; - signed32 t1, t2; - signed64 tl, th; + int16_t al, ah, bl, bh; + int32_t t1, t2; + int64_t tl, th; int movl, movh, ovl, ovh; - al = (signed16) EV_HIHALF (*rA); - ah = (signed16) EV_HIHALF (*rAh); - bl = (signed16) EV_HIHALF (*rB); - bh = (signed16) EV_HIHALF (*rBh); + al = (int16_t) EV_HIHALF (*rA); + ah = (int16_t) EV_HIHALF (*rAh); + bl = (int16_t) EV_HIHALF (*rB); + bh = (int16_t) EV_HIHALF (*rBh); t1 = ev_multiply16_ssf (ah, bh, &movh); t2 = ev_multiply16_ssf (al, bl, &movl); th = EV_ACCHIGH - EV_SATURATE (movh, 0x7fffffff, t1); @@ -1342,13 +1342,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1409:EVX:e500:evmhessianw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Integer and Accumulate Negative into Words - signed32 al, ah, bl, bh; - signed64 t1, t2, tl, th; + int32_t al, ah, bl, bh; + int64_t t1, t2, tl, th; int ovl, ovh; - al = (signed32)(signed16)EV_HIHALF(*rA); - ah = (signed32)(signed16)EV_HIHALF(*rAh); - bl = (signed32)(signed16)EV_HIHALF(*rB); - bh = (signed32)(signed16)EV_HIHALF(*rBh); + al = (int32_t)(int16_t)EV_HIHALF(*rA); + ah = (int32_t)(int16_t)EV_HIHALF(*rAh); + bl = (int32_t)(int16_t)EV_HIHALF(*rB); + bh = (int32_t)(int16_t)EV_HIHALF(*rBh); t1 = ah * bh; t2 = al * bl; th = EV_ACCHIGH - t1; @@ -1361,26 +1361,26 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1419:EVX:e500:evmhesmfanw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional and Accumulate Negative into Words - signed32 al, ah, bl, bh; - signed64 t1, t2, tl, th; - al = (unsigned32)(unsigned16)EV_HIHALF(*rA); - ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); - bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); - bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); - t1 = ((signed64)ah * bh) << 1; - t2 = ((signed64)al * bl) << 1; + int32_t al, ah, bl, bh; + int64_t t1, t2, tl, th; + al = (uint32_t)(uint16_t)EV_HIHALF(*rA); + ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh); + bl = (uint32_t)(uint16_t)EV_HIHALF(*rB); + bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh); + t1 = ((int64_t)ah * bh) << 1; + t2 = ((int64_t)al * bl) << 1; th = EV_ACCHIGH - (t1 & 0xffffffff); tl = EV_ACCLOW - (t2 & 0xffffffff); EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1417:EVX:e500:evmhesmianw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer and Accumulate Negative into Words - signed32 al, ah, bl, bh; - signed64 t1, t2, tl, th; - al = (signed32)(signed16)EV_HIHALF(*rA); - ah = (signed32)(signed16)EV_HIHALF(*rAh); - bl = (signed32)(signed16)EV_HIHALF(*rB); - bh = (signed32)(signed16)EV_HIHALF(*rBh); + int32_t al, ah, bl, bh; + int64_t t1, t2, tl, th; + al = (int32_t)(int16_t)EV_HIHALF(*rA); + ah = (int32_t)(int16_t)EV_HIHALF(*rAh); + bl = (int32_t)(int16_t)EV_HIHALF(*rB); + bh = (int32_t)(int16_t)EV_HIHALF(*rBh); t1 = ah * bh; t2 = al * bl; th = EV_ACCHIGH - t1; @@ -1391,18 +1391,18 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1408:EVX:e500:evmheusianw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Saturate Integer and Accumulate Negative into Words - unsigned32 al, ah, bl, bh; - unsigned64 t1, t2; - signed64 tl, th; + uint32_t al, ah, bl, bh; + uint64_t t1, t2; + int64_t tl, th; int ovl, ovh; - al = (unsigned32)(unsigned16)EV_HIHALF(*rA); - ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); - bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); - bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); + al = (uint32_t)(uint16_t)EV_HIHALF(*rA); + ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh); + bl = (uint32_t)(uint16_t)EV_HIHALF(*rB); + bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh); t1 = ah * bh; t2 = al * bl; - th = (signed64)EV_ACCHIGH - (signed64)t1; - tl = (signed64)EV_ACCLOW - (signed64)t2; + th = (int64_t)EV_ACCHIGH - (int64_t)t1; + tl = (int64_t)EV_ACCLOW - (int64_t)t2; ovl = EV_SAT_P_U32(tl); ovh = EV_SAT_P_U32(th); EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), @@ -1413,13 +1413,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1416:EVX:e500:evmheumianw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer and Accumulate Negative into Words - unsigned32 al, ah, bl, bh; - unsigned32 t1, t2; - unsigned64 tl, th; - al = (unsigned32)(unsigned16)EV_HIHALF(*rA); - ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); - bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); - bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); + uint32_t al, ah, bl, bh; + uint32_t t1, t2; + uint64_t tl, th; + al = (uint32_t)(uint16_t)EV_HIHALF(*rA); + ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh); + bl = (uint32_t)(uint16_t)EV_HIHALF(*rB); + bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh); t1 = ah * bh; t2 = al * bl; th = EV_ACCHIGH - t1; @@ -1428,66 +1428,66 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1327:EVX:e500:evmhogsmfaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Fractional and Accumulate - signed32 a, b; - signed64 t1, t2; - a = (signed32)(signed16)EV_LOHALF(*rA); - b = (signed32)(signed16)EV_LOHALF(*rB); + int32_t a, b; + int64_t t1, t2; + a = (int32_t)(int16_t)EV_LOHALF(*rA); + b = (int32_t)(int16_t)EV_LOHALF(*rB); t1 = EV_MUL16_SSF(a, b); - if (t1 & ((unsigned64)1 << 32)) + if (t1 & ((uint64_t)1 << 32)) t1 |= 0xfffffffe00000000; t2 = ACC + t1; EV_SET_REG1_ACC(*rSh, *rS, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1325:EVX:e500:evmhogsmiaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Integer and Accumulate - signed32 a, b; - signed64 t1, t2; - a = (signed32)(signed16)EV_LOHALF(*rA); - b = (signed32)(signed16)EV_LOHALF(*rB); - t1 = (signed64)a * (signed64)b; - t2 = (signed64)ACC + t1; + int32_t a, b; + int64_t t1, t2; + a = (int32_t)(int16_t)EV_LOHALF(*rA); + b = (int32_t)(int16_t)EV_LOHALF(*rB); + t1 = (int64_t)a * (int64_t)b; + t2 = (int64_t)ACC + t1; EV_SET_REG1_ACC(*rSh, *rS, t2); //printf("evmhogsmiaa: a %d b %d t1 %qd t2 %qd\n", a, b, t1, t2); //printf("evmhogsmiaa: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1324:EVX:e500:evmhogumiaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Unsigned Modulo Integer and Accumulate - unsigned32 a, b; - unsigned64 t1, t2; - a = (unsigned32)(unsigned16)EV_LOHALF(*rA); - b = (unsigned32)(unsigned16)EV_LOHALF(*rB); + uint32_t a, b; + uint64_t t1, t2; + a = (uint32_t)(uint16_t)EV_LOHALF(*rA); + b = (uint32_t)(uint16_t)EV_LOHALF(*rB); t1 = a * b; t2 = ACC + t1; EV_SET_REG1_ACC(*rSh, *rS, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1323:EVX:e500:evmhegsmfaa %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Fractional and Accumulate - signed32 a, b; - signed64 t1, t2; - a = (signed32)(signed16)EV_HIHALF(*rA); - b = (signed32)(signed16)EV_HIHALF(*rB); + int32_t a, b; + int64_t t1, t2; + a = (int32_t)(int16_t)EV_HIHALF(*rA); + b = (int32_t)(int16_t)EV_HIHALF(*rB); t1 = EV_MUL16_SSF(a, b); - if (t1 & ((unsigned64)1 << 32)) + if (t1 & ((uint64_t)1 << 32)) t1 |= 0xfffffffe00000000; t2 = ACC + t1; EV_SET_REG1_ACC(*rSh, *rS, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1321:EVX:e500:evmhegsmiaa %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Integer and Accumulate - signed32 a, b; - signed64 t1, t2; - a = (signed32)(signed16)EV_HIHALF(*rA); - b = (signed32)(signed16)EV_HIHALF(*rB); - t1 = (signed64)(a * b); + int32_t a, b; + int64_t t1, t2; + a = (int32_t)(int16_t)EV_HIHALF(*rA); + b = (int32_t)(int16_t)EV_HIHALF(*rB); + t1 = (int64_t)(a * b); t2 = ACC + t1; EV_SET_REG1_ACC(*rSh, *rS, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1320:EVX:e500:evmhegumiaa %RS,%RA,%RB:Multiply Half Words Even Guarded Unsigned Modulo Integer and Accumulate - unsigned32 a, b; - unsigned64 t1, t2; - a = (unsigned32)(unsigned16)EV_HIHALF(*rA); - b = (unsigned32)(unsigned16)EV_HIHALF(*rB); + uint32_t a, b; + uint64_t t1, t2; + a = (uint32_t)(uint16_t)EV_HIHALF(*rA); + b = (uint32_t)(uint16_t)EV_HIHALF(*rB); t1 = a * b; t2 = ACC + t1; EV_SET_REG1_ACC(*rSh, *rS, t2); @@ -1495,23 +1495,23 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.1455:EVX:e500:evmhogsmfan %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Fractional and Accumulate Negative - signed32 a, b; - signed64 t1, t2; - a = (signed32)(signed16)EV_LOHALF(*rA); - b = (signed32)(signed16)EV_LOHALF(*rB); + int32_t a, b; + int64_t t1, t2; + a = (int32_t)(int16_t)EV_LOHALF(*rA); + b = (int32_t)(int16_t)EV_LOHALF(*rB); t1 = EV_MUL16_SSF(a, b); - if (t1 & ((unsigned64)1 << 32)) + if (t1 & ((uint64_t)1 << 32)) t1 |= 0xfffffffe00000000; t2 = ACC - t1; EV_SET_REG1_ACC(*rSh, *rS, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1453:EVX:e500:evmhogsmian %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Integer and Accumulate Negative - signed32 a, b; - signed64 t1, t2; - a = (signed32)(signed16)EV_LOHALF(*rA); - b = (signed32)(signed16)EV_LOHALF(*rB); - t1 = (signed64)a * (signed64)b; + int32_t a, b; + int64_t t1, t2; + a = (int32_t)(int16_t)EV_LOHALF(*rA); + b = (int32_t)(int16_t)EV_LOHALF(*rB); + t1 = (int64_t)a * (int64_t)b; t2 = ACC - t1; EV_SET_REG1_ACC(*rSh, *rS, t2); //printf("evmhogsmian: a %d b %d t1 %qd t2 %qd\n", a, b, t1, t2); @@ -1519,51 +1519,51 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1452:EVX:e500:evmhogumian %RS,%RA,%RB:Multiply Half Words Odd Guarded Unsigned Modulo Integer and Accumulate Negative - unsigned32 a, b; - unsigned64 t1, t2; - a = (unsigned32)(unsigned16)EV_LOHALF(*rA); - b = (unsigned32)(unsigned16)EV_LOHALF(*rB); - t1 = (unsigned64)a * (unsigned64)b; + uint32_t a, b; + uint64_t t1, t2; + a = (uint32_t)(uint16_t)EV_LOHALF(*rA); + b = (uint32_t)(uint16_t)EV_LOHALF(*rB); + t1 = (uint64_t)a * (uint64_t)b; t2 = ACC - t1; EV_SET_REG1_ACC(*rSh, *rS, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1451:EVX:e500:evmhegsmfan %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Fractional and Accumulate Negative - signed32 a, b; - signed64 t1, t2; - a = (signed32)(signed16)EV_HIHALF(*rA); - b = (signed32)(signed16)EV_HIHALF(*rB); + int32_t a, b; + int64_t t1, t2; + a = (int32_t)(int16_t)EV_HIHALF(*rA); + b = (int32_t)(int16_t)EV_HIHALF(*rB); t1 = EV_MUL16_SSF(a, b); - if (t1 & ((unsigned64)1 << 32)) + if (t1 & ((uint64_t)1 << 32)) t1 |= 0xfffffffe00000000; t2 = ACC - t1; EV_SET_REG1_ACC(*rSh, *rS, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1449:EVX:e500:evmhegsmian %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Integer and Accumulate Negative - signed32 a, b; - signed64 t1, t2; - a = (signed32)(signed16)EV_HIHALF(*rA); - b = (signed32)(signed16)EV_HIHALF(*rB); - t1 = (signed64)a * (signed64)b; + int32_t a, b; + int64_t t1, t2; + a = (int32_t)(int16_t)EV_HIHALF(*rA); + b = (int32_t)(int16_t)EV_HIHALF(*rB); + t1 = (int64_t)a * (int64_t)b; t2 = ACC - t1; EV_SET_REG1_ACC(*rSh, *rS, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1448:EVX:e500:evmhegumian %RS,%RA,%RB:Multiply Half Words Even Guarded Unsigned Modulo Integer and Accumulate Negative - unsigned32 a, b; - unsigned64 t1, t2; - a = (unsigned32)(unsigned16)EV_HIHALF(*rA); - b = (unsigned32)(unsigned16)EV_HIHALF(*rB); - t1 = (unsigned64)a * (unsigned64)b; + uint32_t a, b; + uint64_t t1, t2; + a = (uint32_t)(uint16_t)EV_HIHALF(*rA); + b = (uint32_t)(uint16_t)EV_HIHALF(*rB); + t1 = (uint64_t)a * (uint64_t)b; t2 = ACC - t1; EV_SET_REG1_ACC(*rSh, *rS, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1095:EVX:e500:evmwhssf %RS,%RA,%RB:Vector Multiply Word High Signed Saturate Fractional - signed32 al, ah, bl, bh; - signed64 t1, t2; + int32_t al, ah, bl, bh; + int64_t t1, t2; int movl, movh; al = *rA; ah = *rAh; @@ -1577,8 +1577,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1127:EVX:e500:evmwhssfa %RS,%RA,%RB:Vector Multiply Word High Signed Saturate Fractional and Accumulate - signed32 al, ah, bl, bh; - signed64 t1, t2; + int32_t al, ah, bl, bh; + int64_t t1, t2; int movl, movh; al = *rA; ah = *rAh; @@ -1592,8 +1592,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1103:EVX:e500:evmwhsmf %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Fractional - signed32 al, ah, bl, bh; - signed64 t1, t2; + int32_t al, ah, bl, bh; + int64_t t1, t2; al = *rA; ah = *rAh; bl = *rB; @@ -1604,8 +1604,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1135:EVX:e500:evmwhsmfa %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Fractional and Accumulate - signed32 al, ah, bl, bh; - signed64 t1, t2; + int32_t al, ah, bl, bh; + int64_t t1, t2; al = *rA; ah = *rAh; bl = *rB; @@ -1616,57 +1616,57 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1101:EVX:e500:evmwhsmi %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Integer - signed32 al, ah, bl, bh; - signed64 t1, t2; + int32_t al, ah, bl, bh; + int64_t t1, t2; al = *rA; ah = *rAh; bl = *rB; bh = *rBh; - t1 = (signed64)al * (signed64)bl; - t2 = (signed64)ah * (signed64)bh; + t1 = (int64_t)al * (int64_t)bl; + t2 = (int64_t)ah * (int64_t)bh; EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1133:EVX:e500:evmwhsmia %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Integer and Accumulate - signed32 al, ah, bl, bh; - signed64 t1, t2; + int32_t al, ah, bl, bh; + int64_t t1, t2; al = *rA; ah = *rAh; bl = *rB; bh = *rBh; - t1 = (signed64)al * (signed64)bl; - t2 = (signed64)ah * (signed64)bh; + t1 = (int64_t)al * (int64_t)bl; + t2 = (int64_t)ah * (int64_t)bh; EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1100:EVX:e500:evmwhumi %RS,%RA,%RB:Vector Multiply Word High Unsigned Modulo Integer - unsigned32 al, ah, bl, bh; - unsigned64 t1, t2; + uint32_t al, ah, bl, bh; + uint64_t t1, t2; al = *rA; ah = *rAh; bl = *rB; bh = *rBh; - t1 = (unsigned64)al * (unsigned64)bl; - t2 = (unsigned64)ah * (unsigned64)bh; + t1 = (uint64_t)al * (uint64_t)bl; + t2 = (uint64_t)ah * (uint64_t)bh; EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1132:EVX:e500:evmwhumia %RS,%RA,%RB:Vector Multiply Word High Unsigned Modulo Integer and Accumulate - unsigned32 al, ah, bl, bh; - unsigned64 t1, t2; + uint32_t al, ah, bl, bh; + uint64_t t1, t2; al = *rA; ah = *rAh; bl = *rB; bh = *rBh; - t1 = (unsigned64)al * (unsigned64)bl; - t2 = (unsigned64)ah * (unsigned64)bh; + t1 = (uint64_t)al * (uint64_t)bl; + t2 = (uint64_t)ah * (uint64_t)bh; EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1091:EVX:e500:evmwlssf %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional - signed32 al, ah, bl, bh; - signed64 t1, t2; + int32_t al, ah, bl, bh; + int64_t t1, t2; int movl, movh; al = *rA; ah = *rAh; @@ -1680,8 +1680,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1123:EVX:e500:evmwlssfa %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate - signed32 al, ah, bl, bh; - signed64 t1, t2; + int32_t al, ah, bl, bh; + int64_t t1, t2; int movl, movh; al = *rA; ah = *rAh; @@ -1695,8 +1695,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1099:EVX:e500:evmwlsmf %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional - signed32 al, ah, bl, bh; - signed64 t1, t2; + int32_t al, ah, bl, bh; + int64_t t1, t2; al = *rA; ah = *rAh; bl = *rB; @@ -1707,8 +1707,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1131:EVX:e500:evmwlsmfa %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate - signed32 al, ah, bl, bh; - signed64 t1, t2; + int32_t al, ah, bl, bh; + int64_t t1, t2; al = *rA; ah = *rAh; bl = *rB; @@ -1719,33 +1719,33 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1096:EVX:e500:evmwlumi %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer - unsigned32 al, ah, bl, bh; - unsigned64 t1, t2; + uint32_t al, ah, bl, bh; + uint64_t t1, t2; al = *rA; ah = *rAh; bl = *rB; bh = *rBh; - t1 = (unsigned64)al * (unsigned64)bl; - t2 = (unsigned64)ah * (unsigned64)bh; + t1 = (uint64_t)al * (uint64_t)bl; + t2 = (uint64_t)ah * (uint64_t)bh; EV_SET_REG2(*rSh, *rS, t2, t1); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1128:EVX:e500:evmwlumia %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate - unsigned32 al, ah, bl, bh; - unsigned64 t1, t2; + uint32_t al, ah, bl, bh; + uint64_t t1, t2; al = *rA; ah = *rAh; bl = *rB; bh = *rBh; - t1 = (unsigned64)al * (unsigned64)bl; - t2 = (unsigned64)ah * (unsigned64)bh; + t1 = (uint64_t)al * (uint64_t)bl; + t2 = (uint64_t)ah * (uint64_t)bh; EV_SET_REG2_ACC(*rSh, *rS, t2, t1); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1347:EVX:e500:evmwlssfaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate in Words - signed32 al, ah, bl, bh; - signed64 t1, t2, tl, th; + int32_t al, ah, bl, bh; + int64_t t1, t2, tl, th; int movl, movh, ovl, ovh; al = *rA; ah = *rAh; @@ -1763,15 +1763,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1345:EVX:e500:evmwlssiaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Integer and Accumulate in Words - signed32 al, ah, bl, bh; - signed64 t1, t2, tl, th; + int32_t al, ah, bl, bh; + int64_t t1, t2, tl, th; int ovl, ovh; al = *rA; ah = *rAh; bl = *rB; bh = *rBh; - t1 = (signed64)ah * (signed64)bh; - t2 = (signed64)al * (signed64)bl; + t1 = (int64_t)ah * (int64_t)bh; + t2 = (int64_t)al * (int64_t)bl; th = EV_ACCHIGH + (t1 & 0xffffffff); tl = EV_ACCLOW + (t2 & 0xffffffff); ovh = EV_SAT_P_S32(th); @@ -1782,8 +1782,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1355:EVX:e500:evmwlsmfaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate in Words - signed32 al, ah, bl, bh; - signed64 t1, t2; + int32_t al, ah, bl, bh; + int64_t t1, t2; int mov; al = *rA; ah = *rAh; @@ -1796,14 +1796,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1353:EVX:e500:evmwlsmiaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Integer and Accumulate in Words - signed32 al, ah, bl, bh; - signed64 t1, t2; + int32_t al, ah, bl, bh; + int64_t t1, t2; al = *rA; ah = *rAh; bl = *rB; bh = *rBh; - t1 = (signed64)ah * (signed64)bh; - t2 = (signed64)al * (signed64)bl; + t1 = (int64_t)ah * (int64_t)bh; + t2 = (int64_t)al * (int64_t)bl; EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff), EV_ACCLOW + (t2 & 0xffffffff)); //printf("evmwlsmiaaw: al %d ah %d bl %d bh %d t1 %qd t2 %qd\n", al, ah, bl, bh, t1, t2); @@ -1811,15 +1811,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1344:EVX:e500:evmwlusiaaw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Saturate Integer and Accumulate in Words - unsigned32 al, ah, bl, bh; - unsigned64 t1, t2, tl, th; + uint32_t al, ah, bl, bh; + uint64_t t1, t2, tl, th; int ovl, ovh; al = *rA; ah = *rAh; bl = *rB; bh = *rBh; - t1 = (unsigned64)ah * (unsigned64)bh; - t2 = (unsigned64)al * (unsigned64)bl; + t1 = (uint64_t)ah * (uint64_t)bh; + t2 = (uint64_t)al * (uint64_t)bl; th = EV_ACCHIGH + (t1 & 0xffffffff); tl = EV_ACCLOW + (t2 & 0xffffffff); ovh = (th >> 32); @@ -1830,22 +1830,22 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1352:EVX:e500:evmwlumiaaw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate in Words - unsigned32 al, ah, bl, bh; - unsigned64 t1, t2; + uint32_t al, ah, bl, bh; + uint64_t t1, t2; al = *rA; ah = *rAh; bl = *rB; bh = *rBh; - t1 = (unsigned64)ah * (unsigned64)bh; - t2 = (unsigned64)al * (unsigned64)bl; + t1 = (uint64_t)ah * (uint64_t)bh; + t2 = (uint64_t)al * (uint64_t)bl; EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff), EV_ACCLOW + (t2 & 0xffffffff)); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1475:EVX:e500:evmwlssfanw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate Negative in Words - signed32 al, ah, bl, bh; - signed64 t1, t2, tl, th; + int32_t al, ah, bl, bh; + int64_t t1, t2, tl, th; int movl, movh, ovl, ovh; al = *rA; ah = *rAh; @@ -1863,15 +1863,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1473:EVX:e500:evmwlssianw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Integer and Accumulate Negative in Words - signed32 al, ah, bl, bh; - signed64 t1, t2, tl, th; + int32_t al, ah, bl, bh; + int64_t t1, t2, tl, th; int ovl, ovh; al = *rA; ah = *rAh; bl = *rB; bh = *rBh; - t1 = (signed64)ah * (signed64)bh; - t2 = (signed64)al * (signed64)bl; + t1 = (int64_t)ah * (int64_t)bh; + t2 = (int64_t)al * (int64_t)bl; th = EV_ACCHIGH - (t1 & 0xffffffff); tl = EV_ACCLOW - (t2 & 0xffffffff); ovh = EV_SAT_P_S32(th); @@ -1882,8 +1882,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1483:EVX:e500:evmwlsmfanw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate Negative in Words - signed32 al, ah, bl, bh; - signed64 t1, t2; + int32_t al, ah, bl, bh; + int64_t t1, t2; int mov; al = *rA; ah = *rAh; @@ -1896,28 +1896,28 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1481:EVX:e500:evmwlsmianw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Integer and Accumulate Negative in Words - signed32 al, ah, bl, bh; - signed64 t1, t2; + int32_t al, ah, bl, bh; + int64_t t1, t2; al = *rA; ah = *rAh; bl = *rB; bh = *rBh; - t1 = (signed64)ah * (signed64)bh; - t2 = (signed64)al * (signed64)bl; + t1 = (int64_t)ah * (int64_t)bh; + t2 = (int64_t)al * (int64_t)bl; EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH - (t1 & 0xffffffff), EV_ACCLOW - (t2 & 0xffffffff)); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1472:EVX:e500:evmwlusianw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Saturate Integer and Accumulate Negative in Words - unsigned32 al, ah, bl, bh; - unsigned64 t1, t2, tl, th; + uint32_t al, ah, bl, bh; + uint64_t t1, t2, tl, th; int ovl, ovh; al = *rA; ah = *rAh; bl = *rB; bh = *rBh; - t1 = (unsigned64)ah * (unsigned64)bh; - t2 = (unsigned64)al * (unsigned64)bl; + t1 = (uint64_t)ah * (uint64_t)bh; + t2 = (uint64_t)al * (uint64_t)bl; th = EV_ACCHIGH - (t1 & 0xffffffff); tl = EV_ACCLOW - (t2 & 0xffffffff); ovh = (th >> 32); @@ -1930,22 +1930,22 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1480:EVX:e500:evmwlumianw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate Negative in Words - unsigned32 al, ah, bl, bh; - unsigned64 t1, t2; + uint32_t al, ah, bl, bh; + uint64_t t1, t2; al = *rA; ah = *rAh; bl = *rB; bh = *rBh; - t1 = (unsigned64)ah * (unsigned64)bh; - t2 = (unsigned64)al * (unsigned64)bl; + t1 = (uint64_t)ah * (uint64_t)bh; + t2 = (uint64_t)al * (uint64_t)bl; EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH - (t1 & 0xffffffff), EV_ACCLOW - (t2 & 0xffffffff)); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1107:EVX:e500:evmwssf %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional - signed32 a, b; - signed64 t; + int32_t a, b; + int64_t t; int movl; a = *rA; b = *rB; @@ -1955,8 +1955,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1139:EVX:e500:evmwssfa %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional and Accumulate - signed32 a, b; - signed64 t; + int32_t a, b; + int64_t t; int movl; a = *rA; b = *rB; @@ -1966,8 +1966,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1115:EVX:e500:evmwsmf %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional - signed32 a, b; - signed64 t; + int32_t a, b; + int64_t t; int movl; a = *rA; b = *rB; @@ -1976,8 +1976,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1147:EVX:e500:evmwsmfa %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional and Accumulate - signed32 a, b; - signed64 t; + int32_t a, b; + int64_t t; int movl; a = *rA; b = *rB; @@ -1986,49 +1986,49 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1113:EVX:e500:evmwsmi %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer - signed32 a, b; - signed64 t; + int32_t a, b; + int64_t t; int movl; a = *rA; b = *rB; - t = (signed64)a * (signed64)b; + t = (int64_t)a * (int64_t)b; EV_SET_REG1(*rSh, *rS, t); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1145:EVX:e500:evmwsmia %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer and Accumulate - signed32 a, b; - signed64 t; + int32_t a, b; + int64_t t; int movl; a = *rA; b = *rB; - t = (signed64)a * (signed64)b; + t = (int64_t)a * (int64_t)b; EV_SET_REG1_ACC(*rSh, *rS, t); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1112:EVX:e500:evmwumi %RS,%RA,%RB:Vector Multiply Word Unigned Modulo Integer - unsigned32 a, b; - unsigned64 t; + uint32_t a, b; + uint64_t t; int movl; a = *rA; b = *rB; - t = (signed64)a * (signed64)b; + t = (int64_t)a * (int64_t)b; EV_SET_REG1(*rSh, *rS, t); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1144:EVX:e500:evmwumia %RS,%RA,%RB:Vector Multiply Word Unigned Modulo Integer and Accumulate - unsigned32 a, b; - unsigned64 t; + uint32_t a, b; + uint64_t t; int movl; a = *rA; b = *rB; - t = (signed64)a * (signed64)b; + t = (int64_t)a * (int64_t)b; EV_SET_REG1_ACC(*rSh, *rS, t); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1363:EVX:e500:evmwssfaa %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional Add and Accumulate - signed64 t1, t2; - signed32 a, b; + int64_t t1, t2; + int32_t a, b; int movl; a = *rA; b = *rB; @@ -2039,8 +2039,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1371:EVX:e500:evmwsmfaa %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional Add and Accumulate - signed64 t1, t2; - signed32 a, b; + int64_t t1, t2; + int32_t a, b; int movl; a = *rA; b = *rB; @@ -2050,29 +2050,29 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1369:EVX:e500:evmwsmiaa %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer And and Accumulate - signed64 t1, t2; - signed32 a, b; + int64_t t1, t2; + int32_t a, b; a = *rA; b = *rB; - t1 = (signed64)a * (signed64)b; + t1 = (int64_t)a * (int64_t)b; t2 = ACC + t1; EV_SET_REG1_ACC(*rSh, *rS, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1368:EVX:e500:evmwumiaa %RS,%RA,%RB:Vector Multiply Word Unsigned Modulo Integer Add and Accumulate - unsigned64 t1, t2; - unsigned32 a, b; + uint64_t t1, t2; + uint32_t a, b; a = *rA; b = *rB; - t1 = (unsigned64)a * (unsigned64)b; + t1 = (uint64_t)a * (uint64_t)b; t2 = ACC + t1; EV_SET_REG1_ACC(*rSh, *rS, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1491:EVX:e500:evmwssfan %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional and Accumulate Negative - signed64 t1, t2; - signed32 a, b; + int64_t t1, t2; + int32_t a, b; int movl; a = *rA; b = *rB; @@ -2083,8 +2083,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.1499:EVX:e500:evmwsmfan %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional and Accumulate Negative - signed64 t1, t2; - signed32 a, b; + int64_t t1, t2; + int32_t a, b; int movl; a = *rA; b = *rB; @@ -2094,61 +2094,61 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1497:EVX:e500:evmwsmian %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer and Accumulate Negative - signed64 t1, t2; - signed32 a, b; + int64_t t1, t2; + int32_t a, b; a = *rA; b = *rB; - t1 = (signed64)a * (signed64)b; + t1 = (int64_t)a * (int64_t)b; t2 = ACC - t1; EV_SET_REG1_ACC(*rSh, *rS, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1496:EVX:e500:evmwumian %RS,%RA,%RB:Vector Multiply Word Unsigned Modulo Integer and Accumulate Negative - unsigned64 t1, t2; - unsigned32 a, b; + uint64_t t1, t2; + uint32_t a, b; a = *rA; b = *rB; - t1 = (unsigned64)a * (unsigned64)b; + t1 = (uint64_t)a * (uint64_t)b; t2 = ACC - t1; EV_SET_REG1_ACC(*rSh, *rS, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 0.4,6.RS,11.RA,16.0,21.1217:EVX:e500:evaddssiaaw %RS,%RA:Vector Add Signed Saturate Integer to Accumulator Word - signed64 t1, t2; - signed32 al, ah; + int64_t t1, t2; + int32_t al, ah; int ovl, ovh; al = *rA; ah = *rAh; - t1 = (signed64)EV_ACCHIGH + (signed64)ah; - t2 = (signed64)EV_ACCLOW + (signed64)al; + t1 = (int64_t)EV_ACCHIGH + (int64_t)ah; + t2 = (int64_t)EV_ACCLOW + (int64_t)al; ovh = EV_SAT_P_S32(t1); ovl = EV_SAT_P_S32(t2); - EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, t1 & ((unsigned64)1 << 32), 0x80000000, 0x7fffffff, t1), - EV_SATURATE_ACC(ovl, t2 & ((unsigned64)1 << 32), 0x80000000, 0x7fffffff, t2)); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, t1 & ((uint64_t)1 << 32), 0x80000000, 0x7fffffff, t1), + EV_SATURATE_ACC(ovl, t2 & ((uint64_t)1 << 32), 0x80000000, 0x7fffffff, t2)); EV_SET_SPEFSCR_OV(ovl, ovh); PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.0,21.1225:EVX:e500:evaddsmiaaw %RS,%RA:Vector Add Signed Modulo Integer to Accumulator Word - signed64 t1, t2; - signed32 al, ah; + int64_t t1, t2; + int32_t al, ah; al = *rA; ah = *rAh; - t1 = (signed64)EV_ACCHIGH + (signed64)ah; - t2 = (signed64)EV_ACCLOW + (signed64)al; + t1 = (int64_t)EV_ACCHIGH + (int64_t)ah; + t2 = (int64_t)EV_ACCLOW + (int64_t)al; EV_SET_REG2_ACC(*rSh, *rS, t1, t2); //printf("evaddsmiaaw: al %d ah %d t1 %qd t2 %qd\n", al, ah, t1, t2); //printf("evaddsmiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.0,21.1216:EVX:e500:evaddusiaaw %RS,%RA:Vector Add Unsigned Saturate Integer to Accumulator Word - signed64 t1, t2; - unsigned32 al, ah; + int64_t t1, t2; + uint32_t al, ah; int ovl, ovh; al = *rA; ah = *rAh; - t1 = (signed64)EV_ACCHIGH + (signed64)ah; - t2 = (signed64)EV_ACCLOW + (signed64)al; + t1 = (int64_t)EV_ACCHIGH + (int64_t)ah; + t2 = (int64_t)EV_ACCLOW + (int64_t)al; ovh = EV_SAT_P_U32(t1); ovl = EV_SAT_P_U32(t2); EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0xffffffff, t1), @@ -2159,24 +2159,24 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.0,21.1224:EVX:e500:evaddumiaaw %RS,%RA:Vector Add Unsigned Modulo Integer to Accumulator Word - unsigned64 t1, t2; - unsigned32 al, ah; + uint64_t t1, t2; + uint32_t al, ah; al = *rA; ah = *rAh; - t1 = (unsigned64)EV_ACCHIGH + (unsigned64)ah; + t1 = (uint64_t)EV_ACCHIGH + (uint64_t)ah; t2 = EV_ACCLOW + al; EV_SET_REG2_ACC(*rSh, *rS, t1, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.0,21.1219:EVX:e500:evsubfssiaaw %RS,%RA:Vector Subtract Signed Saturate Integer to Accumulator Word - signed64 t1, t2; - signed32 al, ah; + int64_t t1, t2; + int32_t al, ah; int ovl, ovh; al = *rA; ah = *rAh; - t1 = (signed64)EV_ACCHIGH - (signed64)ah; - t2 = (signed64)EV_ACCLOW - (signed64)al; + t1 = (int64_t)EV_ACCHIGH - (int64_t)ah; + t2 = (int64_t)EV_ACCLOW - (int64_t)al; ovh = EV_SAT_P_S32(t1); ovl = EV_SAT_P_S32(t2); EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, t1, 0x80000000, 0x7fffffff, t1), @@ -2185,24 +2185,24 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.0,21.1227:EVX:e500:evsubfsmiaaw %RS,%RA:Vector Subtract Signed Modulo Integer to Accumulator Word - signed64 t1, t2; - signed32 al, ah; + int64_t t1, t2; + int32_t al, ah; al = *rA; ah = *rAh; - t1 = (signed64)EV_ACCHIGH - (signed64)ah; - t2 = (signed64)EV_ACCLOW - (signed64)al; + t1 = (int64_t)EV_ACCHIGH - (int64_t)ah; + t2 = (int64_t)EV_ACCLOW - (int64_t)al; EV_SET_REG2_ACC(*rSh, *rS, t1, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.0,21.1218:EVX:e500:evsubfusiaaw %RS,%RA:Vector Subtract Unsigned Saturate Integer to Accumulator Word - signed64 t1, t2; - unsigned32 al, ah; + int64_t t1, t2; + uint32_t al, ah; int ovl, ovh; al = *rA; ah = *rAh; - t1 = (signed64)EV_ACCHIGH - (signed64)ah; - t2 = (signed64)EV_ACCLOW - (signed64)al; + t1 = (int64_t)EV_ACCHIGH - (int64_t)ah; + t2 = (int64_t)EV_ACCLOW - (int64_t)al; ovh = EV_SAT_P_U32(t1); ovl = EV_SAT_P_U32(t2); EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0, t1), @@ -2211,12 +2211,12 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.0,21.1226:EVX:e500:evsubfumiaaw %RS,%RA:Vector Subtract Unsigned Modulo Integer to Accumulator Word - unsigned64 t1, t2; - unsigned32 al, ah; + uint64_t t1, t2; + uint32_t al, ah; al = *rA; ah = *rAh; - t1 = (unsigned64)EV_ACCHIGH - (unsigned64)ah; - t2 = (unsigned64)EV_ACCLOW - (unsigned64)al; + t1 = (uint64_t)EV_ACCHIGH - (uint64_t)ah; + t2 = (uint64_t)EV_ACCLOW - (uint64_t)al; EV_SET_REG2_ACC(*rSh, *rS, t1, t2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); @@ -2226,8 +2226,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.1222:EVX:e500:evdivws %RS,%RA,%RB:Vector Divide Word Signed - signed32 dividendh, dividendl, divisorh, divisorl; - signed32 w1, w2; + int32_t dividendh, dividendl, divisorh, divisorl; + int32_t w1, w2; int ovh, ovl; dividendh = *rAh; dividendl = *rA; @@ -2265,8 +2265,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.1223:EVX:e500:evdivwu %RS,%RA,%RB:Vector Divide Word Unsigned - unsigned32 dividendh, dividendl, divisorh, divisorl; - unsigned32 w1, w2; + uint32_t dividendh, dividendl, divisorh, divisorl; + uint32_t w1, w2; int ovh, ovl; dividendh = *rAh; dividendl = *rA; @@ -2296,21 +2296,21 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr # 0.4,6.RS,11.RA,16.0,21.644:EVX:e500:evfsabs %RS,%RA:Vector Floating-Point Absolute Value - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rAh & 0x7fffffff; w2 = *rA & 0x7fffffff; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.0,21.645:EVX:e500:evfsnabs %RS,%RA:Vector Floating-Point Negative Absolute Value - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rAh | 0x80000000; w2 = *rA | 0x80000000; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.0,21.646:EVX:e500:evfsneg %RS,%RA:Vector Floating-Point Negate - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rAh; w2 = *rA; w1 = (w1 & 0x7fffffff) | ((~w1) & 0x80000000); @@ -2319,28 +2319,28 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.640:EVX:e500:evfsadd %RS,%RA,%RB:Vector Floating-Point Add - unsigned32 w1, w2; + uint32_t w1, w2; w1 = ev_fs_add (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fgh, spefscr_fxh, processor); w2 = ev_fs_add (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.641:EVX:e500:evfssub %RS,%RA,%RB:Vector Floating-Point Subtract - unsigned32 w1, w2; + uint32_t w1, w2; w1 = ev_fs_sub (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fgh, spefscr_fxh, processor); w2 = ev_fs_sub (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.648:EVX:e500:evfsmul %RS,%RA,%RB:Vector Floating-Point Multiply - unsigned32 w1, w2; + uint32_t w1, w2; w1 = ev_fs_mul (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fgh, spefscr_fxh, processor); w2 = ev_fs_mul (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.649:EVX:e500:evfsdiv %RS,%RA,%RB:Vector Floating-Point Divide - signed32 w1, w2; + int32_t w1, w2; w1 = ev_fs_div (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fdbzh, spefscr_fgh, spefscr_fxh, processor); w2 = ev_fs_div (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fdbz, spefscr_fg, spefscr_fx, processor); EV_SET_REG2(*rSh, *rS, w1, w2); @@ -2473,7 +2473,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 0.4,6.RS,11.0,16.RB,21.656:EVX:e500:evfscfui %RS,%RB:Vector Convert Floating-Point from Unsigned Integer - unsigned32 f, w1, w2; + uint32_t f, w1, w2; sim_fpu b; sim_fpu_u32to (&b, *rBh, sim_fpu_round_default); @@ -2485,7 +2485,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.664:EVX:e500:evfsctuiz %RS,%RB:Vector Convert Floating-Point to Unsigned Integer with Round toward Zero - unsigned32 w1, w2; + uint32_t w1, w2; sim_fpu b; sim_fpu_32to (&b, *rBh); @@ -2497,7 +2497,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.657:EVX:e500:evfscfsi %RS,%RB:Vector Convert Floating-Point from Signed Integer - signed32 w1, w2; + int32_t w1, w2; sim_fpu b, x, y; sim_fpu_i32to (&b, *rBh, sim_fpu_round_default); @@ -2509,7 +2509,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.658:EVX:e500:evfscfuf %RS,%RB:Vector Convert Floating-Point from Unsigned Fraction - unsigned32 w1, w2, bh, bl; + uint32_t w1, w2, bh, bl; sim_fpu b, x, y; bh = *rBh; if (bh == 0xffffffff) @@ -2533,7 +2533,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.659:EVX:e500:evfscfsf %RS,%RB:Vector Convert Floating-Point from Signed Fraction - unsigned32 w1, w2; + uint32_t w1, w2; sim_fpu b, x, y; sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); @@ -2550,7 +2550,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.660:EVX:e500:evfsctui %RS,%RB:Vector Convert Floating-Point to Unsigned Integer - unsigned32 w1, w2; + uint32_t w1, w2; sim_fpu b; sim_fpu_32to (&b, *rBh); @@ -2562,7 +2562,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.661:EVX:e500:evfsctsi %RS,%RB:Vector Convert Floating-Point to Signed Integer - signed32 w1, w2; + int32_t w1, w2; sim_fpu b; sim_fpu_32to (&b, *rBh); @@ -2574,7 +2574,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.666:EVX:e500:evfsctsiz %RS,%RB:Vector Convert Floating-Point to Signed Integer with Round toward Zero - signed32 w1, w2; + int32_t w1, w2; sim_fpu b; sim_fpu_32to (&b, *rBh); @@ -2586,7 +2586,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.662:EVX:e500:evfsctuf %RS,%RB:Vector Convert Floating-Point to Unsigned Fraction - unsigned32 w1, w2; + uint32_t w1, w2; sim_fpu b, x, y; sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); @@ -2603,7 +2603,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.663:EVX:e500:evfsctsf %RS,%RB:Vector Convert Floating-Point to Signed Fraction - signed32 w1, w2; + int32_t w1, w2; sim_fpu b, x, y; sim_fpu_32to (&y, *rBh); @@ -2621,46 +2621,46 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.0,21.708:EVX:e500:efsabs %RS,%RA:Floating-Point Absolute Value - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rSh; w2 = *rA & 0x7fffffff; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.0,21.709:EVX:e500:efsnabs %RS,%RA:Floating-Point Negative Absolute Value - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rSh; w2 = *rA | 0x80000000; EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.0,21.710:EVX:e500:efsneg %RS,%RA:Floating-Point Negate - unsigned32 w1, w2; + uint32_t w1, w2; w1 = *rSh; w2 = (*rA & 0x7fffffff) | ((~*rA) & 0x80000000); EV_SET_REG2(*rSh, *rS, w1, w2); PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 0.4,6.RS,11.RA,16.RB,21.704:EVX:e500:efsadd %RS,%RA,%RB:Floating-Point Add - unsigned32 w; + uint32_t w; w = ev_fs_add (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); EV_SET_REG(*rS, w); PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.705:EVX:e500:efssub %RS,%RA,%RB:Floating-Point Subtract - unsigned32 w; + uint32_t w; w = ev_fs_sub (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); EV_SET_REG(*rS, w); PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.712:EVX:e500:efsmul %RS,%RA,%RB:Floating-Point Multiply - unsigned32 w; + uint32_t w; w = ev_fs_mul (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); EV_SET_REG(*rS, w); PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 0.4,6.RS,11.RA,16.RB,21.713:EVX:e500:efsdiv %RS,%RA,%RB:Floating-Point Divide - unsigned32 w; + uint32_t w; w = ev_fs_div (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fdbz, spefscr_fg, spefscr_fx, processor); EV_SET_REG(*rS, w); PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); @@ -2750,7 +2750,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 0.4,6.RS,11.0,16.RB,21.721:EVX:e500:efscfsi %RS,%RB:Convert Floating-Point from Signed Integer - signed32 f, w1, w2; + int32_t f, w1, w2; sim_fpu b; w1 = *rSh; sim_fpu_i32to (&b, *rB, sim_fpu_round_default); @@ -2759,7 +2759,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.720:EVX:e500:efscfui %RS,%RB:Convert Floating-Point from Unsigned Integer - unsigned32 w1, w2; + uint32_t w1, w2; sim_fpu b; w1 = *rSh; sim_fpu_u32to (&b, *rB, sim_fpu_round_default); @@ -2768,7 +2768,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.723:EVX:e500:efscfsf %RS,%RB:Convert Floating-Point from Signed Fraction - unsigned32 w1, w2; + uint32_t w1, w2; sim_fpu b, x, y; w1 = *rSh; sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); @@ -2779,7 +2779,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.722:EVX:e500:efscfuf %RS,%RB:Convert Floating-Point from Unsigned Fraction - unsigned32 w1, w2, bl; + uint32_t w1, w2, bl; sim_fpu b, x, y; w1 = *rSh; bl = *rB; @@ -2795,8 +2795,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.725:EVX:e500:efsctsi %RS,%RB:Convert Floating-Point to Signed Integer - signed64 temp; - signed32 w1, w2; + int64_t temp; + int32_t w1, w2; sim_fpu b; w1 = *rSh; sim_fpu_32to (&b, *rB); @@ -2805,8 +2805,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.730:EVX:e500:efsctsiz %RS,%RB:Convert Floating-Point to Signed Integer with Round toward Zero - signed64 temp; - signed32 w1, w2; + int64_t temp; + int32_t w1, w2; sim_fpu b; w1 = *rSh; sim_fpu_32to (&b, *rB); @@ -2815,8 +2815,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.724:EVX:e500:efsctui %RS,%RB:Convert Floating-Point to Unsigned Integer - unsigned64 temp; - signed32 w1, w2; + uint64_t temp; + int32_t w1, w2; sim_fpu b; w1 = *rSh; sim_fpu_32to (&b, *rB); @@ -2825,8 +2825,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.728:EVX:e500:efsctuiz %RS,%RB:Convert Floating-Point to Unsigned Integer with Round toward Zero - unsigned64 temp; - signed32 w1, w2; + uint64_t temp; + int32_t w1, w2; sim_fpu b; w1 = *rSh; sim_fpu_32to (&b, *rB); @@ -2835,7 +2835,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.727:EVX:e500:efsctsf %RS,%RB:Convert Floating-Point to Signed Fraction - unsigned32 w1, w2; + uint32_t w1, w2; sim_fpu b, x, y; w1 = *rSh; sim_fpu_32to (&y, *rB); @@ -2847,7 +2847,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 0.4,6.RS,11.0,16.RB,21.726:EVX:e500:efsctuf %RS,%RB:Convert Floating-Point to Unsigned Fraction - unsigned32 w1, w2; + uint32_t w1, w2; sim_fpu b, x, y; w1 = *rSh; sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); @@ -2863,7 +2863,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr # 0.4,6.RS,11.RA,16.UIMM,21.769:EVX:e500:evldd %RS,%RA,%UIMM:Vector Load Double Word into Double Word - unsigned64 m; + uint64_t m; unsigned_word b; unsigned_word EA; if (RA_is_0) b = 0; @@ -2875,7 +2875,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 0.4,6.RS,11.RA,16.RB,21.768:EVX:e500:evlddx %RS,%RA,%RB:Vector Load Double Word into Double Word Indexed - unsigned64 m; + uint64_t m; unsigned_word b; unsigned_word EA; if (RA_is_0) b = 0; @@ -2888,7 +2888,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.771:EVX:e500:evldw %RS,%RA,%UIMM:Vector Load Double into Two Words unsigned_word b; unsigned_word EA; - unsigned32 w1, w2; + uint32_t w1, w2; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 3); @@ -2900,7 +2900,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.770:EVX:e500:evldwx %RS,%RA,%RB:Vector Load Double into Two Words Indexed unsigned_word b; unsigned_word EA; - unsigned32 w1, w2; + uint32_t w1, w2; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; @@ -2912,7 +2912,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.773:EVX:e500:evldh %RS,%RA,%UIMM:Vector Load Double into 4 Half Words unsigned_word b; unsigned_word EA; - unsigned16 h1, h2, h3, h4; + uint16_t h1, h2, h3, h4; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 3); @@ -2926,7 +2926,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.772:EVX:e500:evldhx %RS,%RA,%RB:Vector Load Double into 4 Half Words Indexed unsigned_word b; unsigned_word EA; - unsigned16 h1, h2, h3, h4; + uint16_t h1, h2, h3, h4; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; @@ -2940,7 +2940,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.785:EVX:e500:evlwhe %RS,%RA,%UIMM:Vector Load Word into Two Half Words Even unsigned_word b; unsigned_word EA; - unsigned16 h1, h2, h3, h4; + uint16_t h1, h2, h3, h4; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 2); @@ -2954,7 +2954,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.784:EVX:e500:evlwhex %RS,%RA,%RB:Vector Load Word into Two Half Words Even Indexed unsigned_word b; unsigned_word EA; - unsigned16 h1, h2, h3, h4; + uint16_t h1, h2, h3, h4; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; @@ -2968,7 +2968,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.789:EVX:e500:evlwhou %RS,%RA,%UIMM:Vector Load Word into Two Half Words Odd Unsigned zero-extended unsigned_word b; unsigned_word EA; - unsigned16 h1, h2, h3, h4; + uint16_t h1, h2, h3, h4; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 2); @@ -2982,7 +2982,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.788:EVX:e500:evlwhoux %RS,%RA,%RB:Vector Load Word into Two Half Words Odd Unsigned Indexed zero-extended unsigned_word b; unsigned_word EA; - unsigned16 h1, h2, h3, h4; + uint16_t h1, h2, h3, h4; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; @@ -2996,7 +2996,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.791:EVX:e500:evlwhos %RS,%RA,%UIMM:Vector Load Word into Half Words Odd Signed with sign extension unsigned_word b; unsigned_word EA; - unsigned16 h1, h2, h3, h4; + uint16_t h1, h2, h3, h4; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 2); @@ -3016,7 +3016,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.790:EVX:e500:evlwhosx %RS,%RA,%RB:Vector Load Word into Half Words Odd Signed Indexed with sign extension unsigned_word b; unsigned_word EA; - unsigned16 h1, h2, h3, h4; + uint16_t h1, h2, h3, h4; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; @@ -3036,7 +3036,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.793:EVX:e500:evlwwsplat %RS,%RA,%UIMM:Vector Load Word into Word and Splat unsigned_word b; unsigned_word EA; - unsigned32 w1; + uint32_t w1; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 2); @@ -3047,7 +3047,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.792:EVX:e500:evlwwsplatx %RS,%RA,%RB:Vector Load Word into Word and Splat Indexed unsigned_word b; unsigned_word EA; - unsigned32 w1; + uint32_t w1; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; @@ -3058,7 +3058,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.797:EVX:e500:evlwhsplat %RS,%RA,%UIMM:Vector Load Word into 2 Half Words and Splat unsigned_word b; unsigned_word EA; - unsigned16 h1, h2; + uint16_t h1, h2; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 2); @@ -3070,7 +3070,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.796:EVX:e500:evlwhsplatx %RS,%RA,%RB:Vector Load Word into 2 Half Words and Splat Indexed unsigned_word b; unsigned_word EA; - unsigned16 h1, h2; + uint16_t h1, h2; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; @@ -3082,7 +3082,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.777:EVX:e500:evlhhesplat %RS,%RA,%UIMM:Vector Load Half Word into Half Words Even and Splat unsigned_word b; unsigned_word EA; - unsigned16 h; + uint16_t h; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 1); @@ -3093,7 +3093,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.776:EVX:e500:evlhhesplatx %RS,%RA,%RB:Vector Load Half Word into Half Words Even and Splat Indexed unsigned_word b; unsigned_word EA; - unsigned16 h; + uint16_t h; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; @@ -3104,7 +3104,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.781:EVX:e500:evlhhousplat %RS,%RA,%UIMM:Vector Load Half Word into Half Word Odd Unsigned and Splat unsigned_word b; unsigned_word EA; - unsigned16 h; + uint16_t h; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 1); @@ -3115,7 +3115,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.780:EVX:e500:evlhhousplatx %RS,%RA,%RB:Vector Load Half Word into Half Word Odd Unsigned and Splat Indexed unsigned_word b; unsigned_word EA; - unsigned16 h; + uint16_t h; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; @@ -3126,7 +3126,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.783:EVX:e500:evlhhossplat %RS,%RA,%UIMM:Vector Load Half Word into Half Word Odd Signed and Splat unsigned_word b; unsigned_word EA; - unsigned16 h1, h2; + uint16_t h1, h2; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 1); @@ -3141,7 +3141,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.782:EVX:e500:evlhhossplatx %RS,%RA,%RB:Vector Load Half Word into Half Word Odd Signed and Splat Indexed unsigned_word b; unsigned_word EA; - unsigned16 h1, h2; + uint16_t h1, h2; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; @@ -3177,7 +3177,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.803:EVX:e500:evstdw %RS,%RA,%UIMM:Vector Store Double of Two Words unsigned_word b; unsigned_word EA; - unsigned32 w1, w2; + uint32_t w1, w2; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 3); @@ -3190,7 +3190,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.802:EVX:e500:evstdwx %RS,%RA,%RB:Vector Store Double of Two Words Indexed unsigned_word b; unsigned_word EA; - unsigned32 w1, w2; + uint32_t w1, w2; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; @@ -3203,7 +3203,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.805:EVX:e500:evstdh %RS,%RA,%UIMM:Vector Store Double of Four Half Words unsigned_word b; unsigned_word EA; - unsigned16 h1, h2, h3, h4; + uint16_t h1, h2, h3, h4; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 3); @@ -3220,7 +3220,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.804:EVX:e500:evstdhx %RS,%RA,%RB:Vector Store Double of Four Half Words Indexed unsigned_word b; unsigned_word EA; - unsigned16 h1, h2, h3, h4; + uint16_t h1, h2, h3, h4; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; @@ -3237,7 +3237,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.825:EVX:e500:evstwwe %RS,%RA,%UIMM:Vector Store Word of Word from Even unsigned_word b; unsigned_word EA; - unsigned32 w; + uint32_t w; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 3); @@ -3248,7 +3248,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.824:EVX:e500:evstwwex %RS,%RA,%RB:Vector Store Word of Word from Even Indexed unsigned_word b; unsigned_word EA; - unsigned32 w; + uint32_t w; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; @@ -3259,7 +3259,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.829:EVX:e500:evstwwo %RS,%RA,%UIMM:Vector Store Word of Word from Odd unsigned_word b; unsigned_word EA; - unsigned32 w; + uint32_t w; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 3); @@ -3270,7 +3270,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.828:EVX:e500:evstwwox %RS,%RA,%RB:Vector Store Word of Word from Odd Indexed unsigned_word b; unsigned_word EA; - unsigned32 w; + uint32_t w; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; @@ -3281,7 +3281,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.817:EVX:e500:evstwhe %RS,%RA,%UIMM:Vector Store Word of Two Half Words from Even unsigned_word b; unsigned_word EA; - unsigned16 h1, h2; + uint16_t h1, h2; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 3); @@ -3294,7 +3294,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.816:EVX:e500:evstwhex %RS,%RA,%RB:Vector Store Word of Two Half Words from Even Indexed unsigned_word b; unsigned_word EA; - unsigned16 h1, h2; + uint16_t h1, h2; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; @@ -3307,7 +3307,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.UIMM,21.821:EVX:e500:evstwho %RS,%RA,%UIMM:Vector Store Word of Two Half Words from Odd unsigned_word b; unsigned_word EA; - unsigned16 h1, h2; + uint16_t h1, h2; if (RA_is_0) b = 0; else b = *rA; EA = b + (UIMM << 3); @@ -3320,7 +3320,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr 0.4,6.RS,11.RA,16.RB,21.820:EVX:e500:evstwhox %RS,%RA,%RB:Vector Store Word of Two Half Words from Odd Indexed unsigned_word b; unsigned_word EA; - unsigned16 h1, h2; + uint16_t h1, h2; if (RA_is_0) b = 0; else b = *rA; EA = b + *rB; |