aboutsummaryrefslogtreecommitdiff
path: root/sim/mips/mips3264r2.igen
diff options
context:
space:
mode:
Diffstat (limited to 'sim/mips/mips3264r2.igen')
-rw-r--r--sim/mips/mips3264r2.igen30
1 files changed, 30 insertions, 0 deletions
diff --git a/sim/mips/mips3264r2.igen b/sim/mips/mips3264r2.igen
index e0b838c..a28d989 100644
--- a/sim/mips/mips3264r2.igen
+++ b/sim/mips/mips3264r2.igen
@@ -193,6 +193,7 @@
011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT
"dext r<RT>, r<RS>, <LSB>, <SIZE+1>"
*mips64r2:
+*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dext (SD_, RT, RS, LSB, SIZE);
@@ -201,6 +202,7 @@
011111,5.RS,5.RT,5.SIZE,5.LSB,000001::64::DEXTM
"dextm r<RT>, r<RS>, <LSB>, <SIZE+33>"
*mips64r2:
+*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dextm (SD_, RT, RS, LSB, SIZE);
@@ -209,6 +211,7 @@
011111,5.RS,5.RT,5.SIZE,5.LSB,000010::64::DEXTU
"dextu r<RT>, r<RS>, <LSB+32>, <SIZE+1>"
*mips64r2:
+*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dextu (SD_, RT, RS, LSB, SIZE);
@@ -219,7 +222,9 @@
"di":RT == 0
"di r<RT>"
*mips32r2:
+*mips32r6:
*mips64r2:
+*mips64r6:
{
do_di (SD_, RT);
}
@@ -228,6 +233,7 @@
011111,5.RS,5.RT,5.MSB,5.LSB,000111::64::DINS
"dins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
*mips64r2:
+*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dins (SD_, RT, RS, LSB, MSB);
@@ -236,6 +242,7 @@
011111,5.RS,5.RT,5.MSB,5.LSB,000101::64::DINSM
"dinsm r<RT>, r<RS>, <LSB>, <MSB+32-LSB+1>"
*mips64r2:
+*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dinsm (SD_, RT, RS, LSB, MSB);
@@ -244,6 +251,7 @@
011111,5.RS,5.RT,5.MSB,5.LSB,000110::64::DINSU
"dinsu r<RT>, r<RS>, <LSB+32>, <MSB-LSB+1>"
*mips64r2:
+*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dinsu (SD_, RT, RS, LSB, MSB);
@@ -253,6 +261,7 @@
011111,00000,5.RT,5.RD,00010,100100::64::DSBH
"dsbh r<RD>, r<RT>"
*mips64r2:
+*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dsbh (SD_, RD, RT);
@@ -261,6 +270,7 @@
011111,00000,5.RT,5.RD,00101,100100::64::DSHD
"dshd r<RD>, r<RT>"
*mips64r2:
+*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dshd (SD_, RD, RT);
@@ -270,7 +280,9 @@
"ei":RT == 0
"ei r<RT>"
*mips32r2:
+*mips32r6:
*mips64r2:
+*mips64r6:
{
do_ei (SD_, RT);
}
@@ -279,7 +291,9 @@
011111,5.RS,5.RT,5.SIZE,5.LSB,000000::32::EXT
"ext r<RT>, r<RS>, <LSB>, <SIZE+1>"
*mips32r2:
+*mips32r6:
*mips64r2:
+*mips64r6:
{
do_ext (SD_, RT, RS, LSB, SIZE);
}
@@ -288,7 +302,9 @@
010001,00011,5.RT,5.FS,00000000000:COP1Sa:32,f::MFHC1
"mfhc1 r<RT>, f<FS>"
*mips32r2:
+*mips32r6:
*mips64r2:
+*mips64r6:
{
do_mfhc1 (SD_, RT, FS);
}
@@ -296,7 +312,9 @@
010001,00111,5.RT,5.FS,00000000000:COP1Sa:32,f::MTHC1
"mthc1 r<RT>, f<FS>"
*mips32r2:
+*mips32r6:
*mips64r2:
+*mips64r6:
{
do_mthc1 (SD_, RT, FS);
}
@@ -305,7 +323,9 @@
011111,5.RS,5.RT,5.MSB,5.LSB,000100::32::INS
"ins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
*mips32r2:
+*mips32r6:
*mips64r2:
+*mips64r6:
{
do_ins (SD_, RT, RS, LSB, MSB);
}
@@ -314,7 +334,9 @@
011111,00000,5.RT,5.RD,10000,100000::32::SEB
"seb r<RD>, r<RT>"
*mips32r2:
+*mips32r6:
*mips64r2:
+*mips64r6:
{
do_seb (SD_, RD, RT);
}
@@ -322,7 +344,9 @@
011111,00000,5.RT,5.RD,11000,100000::32::SEH
"seh r<RD>, r<RT>"
*mips32r2:
+*mips32r6:
*mips64r2:
+*mips64r6:
{
do_seh (SD_, RD, RT);
}
@@ -331,7 +355,9 @@
000001,5.BASE,11111,16.OFFSET::32::SYNCI
"synci <OFFSET>(r<BASE>)"
*mips32r2:
+*mips32r6:
*mips64r2:
+*mips64r6:
{
// sync i-cache - nothing to do currently
}
@@ -340,7 +366,9 @@
011111,00000,5.RT,5.RD,00000,111011::32::RDHWR
"rdhwr r<RT>, r<RD>"
*mips32r2:
+*mips32r6:
*mips64r2:
+*mips64r6:
{
do_rdhwr (SD_, RT, RD);
}
@@ -349,7 +377,9 @@
011111,00000,5.RT,5.RD,00010,100000::32::WSBH
"wsbh r<RD>, r<RT>"
*mips32r2:
+*mips32r6:
*mips64r2:
+*mips64r6:
{
do_wsbh (SD_, RD, RT);
}